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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [ultrasp10.c] - Blame information for rev 801

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/* PR target/11965 */
/* Originator: <jk@tools.de> */
 
/* { dg-do run } */
/* { dg-require-effective-target ultrasparc_hw } */
/* { dg-options "-O -mcpu=ultrasparc" } */
 
/* This used to fail on 32-bit Ultrasparc because GCC emitted
   an invalid shift instruction.  */
 
 
static inline unsigned int shift(int n, unsigned int value)
{
  return value << n;
}
 
unsigned int val = 1;
 
int main(void)
{
  int i;
 
  for (i = 0; i < 4; i++)
    val = shift(32, val);
 
  return 0;
}

Line No.	Rev	Author	Line
1	691	jeremybenn	`/* PR target/11965 */`
2			`/* Originator: <jk@tools.de> */`
3
4			`/* { dg-do run } */`
5			`/* { dg-require-effective-target ultrasparc_hw } */`
6			`/* { dg-options "-O -mcpu=ultrasparc" } */`
7
8			`/* This used to fail on 32-bit Ultrasparc because GCC emitted`
9			`an invalid shift instruction. */`
10
11
12			`static inline unsigned int shift(int n, unsigned int value)`
13			`{`
14			`return value << n;`
15			`}`
16
17			`unsigned int val = 1;`
18
19			`int main(void)`
20			`{`
21			`int i;`
22
23			`for (i = 0; i < 4; i++)`
24			`val = shift(32, val);`
25
26			`return 0;`
27			`}`

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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [ultrasp10.c] - Blame information for rev 801