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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [vec-init-3-vis3.c] - Blame information for rev 801


/* { dg-do run } */
/* { dg-require-effective-target ultrasparc_vis3_hw } */
/* { dg-options "-mcpu=niagara3 -O2" } */
 
#include "vec-init-3.inc"

Line No.	Rev	Author	Line
1	691	jeremybenn	`/* { dg-do run } */`
2			`/* { dg-require-effective-target ultrasparc_vis3_hw } */`
3			`/* { dg-options "-mcpu=niagara3 -O2" } */`
4
5			`#include "vec-init-3.inc"`