OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [vis3misc.c] - Blame information for rev 697

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-mvis3" } */
3
typedef int __v2si __attribute__((vector_size(8)));
4
typedef short __v4hi __attribute__((vector_size(8)));
5
typedef unsigned char __v8qi __attribute__((vector_size(8)));
6
typedef long long int64_t;
7
 
8
__v4hi test_fchksm16 (__v4hi x, __v4hi y)
9
{
10
  return __builtin_vis_fchksm16 (x, y);
11
}
12
 
13
long test_pdistn (__v8qi x, __v8qi y)
14
{
15
  return __builtin_vis_pdistn (x, y);
16
}
17
 
18
__v4hi test_fmean16 (__v4hi x, __v4hi y)
19
{
20
  return __builtin_vis_fmean16 (x, y);
21
}
22
 
23
int64_t test_fpadd64 (int64_t x, int64_t y)
24
{
25
  return __builtin_vis_fpadd64 (x, y);
26
}
27
 
28
int64_t test_fpsub64 (int64_t x, int64_t y)
29
{
30
  return __builtin_vis_fpsub64 (x, y);
31
}
32
 
33
/* { dg-final { scan-assembler "fchksm16\t%" } } */
34
/* { dg-final { scan-assembler "pdistn\t%" } } */
35
/* { dg-final { scan-assembler "fmean16\t%" } } */
36
/* { dg-final { scan-assembler "fpadd64\t%" } } */
37
/* { dg-final { scan-assembler "fpsub64\t%" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.