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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [wrgsr.c] - Blame information for rev 724

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/* { dg-do compile } */
/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
 
void set_gsr (void)
{
        __builtin_vis_write_gsr (2 << 3);
}
 
void set_gsr2 (long x)
{
        __builtin_vis_write_gsr (x);
}
 
/* { dg-final { scan-assembler "wr\t%g0, 16, %gsr" } } */
/* { dg-final { scan-assembler "wr\t%g0, %" } } */

Line No.	Rev	Author	Line
1	691	jeremybenn	`/* { dg-do compile } */`
2			`/* { dg-options "-O -mcpu=ultrasparc -mvis" } */`
3
4			`void set_gsr (void)`
5			`{`
6			`__builtin_vis_write_gsr (2 << 3);`
7			`}`
8
9			`void set_gsr2 (long x)`
10			`{`
11			`__builtin_vis_write_gsr (x);`
12			`}`
13
14			`/* { dg-final { scan-assembler "wr\t%g0, 16, %gsr" } } */`
15			`/* { dg-final { scan-assembler "wr\t%g0, %" } } */`

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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [wrgsr.c] - Blame information for rev 724