OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [xstormy16/] [sfr/] [24_set_sfrw_bitfield_0.c] - Blame information for rev 751

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
2
/* { dg-final { scan-assembler "set1 32532,#0" } } */
3
 
4
typedef struct
5
{
6
  unsigned short b0:1;
7
  unsigned short b1:1;
8
  unsigned short b2:1;
9
  unsigned short b3:1;
10
  unsigned short b4:1;
11
  unsigned short b5:1;
12
  unsigned short b6:1;
13
  unsigned short b7:1;
14
  unsigned short b8:1;
15
  unsigned short b9:1;
16
  unsigned short b10:1;
17
  unsigned short b11:1;
18
  unsigned short b12:1;
19
  unsigned short b13:1;
20
  unsigned short b14:1;
21
  unsigned short b15:1;
22
} BitField;
23
 
24
#define SFR (*((volatile BitField*)0x7f14))
25
unsigned short *p = (unsigned short *) 0x7f14;
26
 
27
void
28
Do (void)
29
{
30
  SFR.b0 = 1;
31
}
32
 
33
int
34
main (void)
35
{
36
  *p = 0x1234;
37
  Do ();
38
  return (*p == 0x1235) ? 0 : 1;
39
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.