OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [trans-mem.h] - Blame information for rev 824

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 684 jeremybenn
/* Miscellaneous transactional memory support definitions.
2
   Copyright (C) 2009, 2011 Free Software Foundation, Inc.
3
 
4
   This file is part of GCC.
5
 
6
   GCC is free software; you can redistribute it and/or modify it under
7
   the terms of the GNU General Public License as published by the Free
8
   Software Foundation; either version 3, or (at your option) any later
9
   version.
10
 
11
   GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12
   WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
   for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with GCC; see the file COPYING3.  If not see
18
   <http://www.gnu.org/licenses/>.  */
19
 
20
 
21
/* These defines must match the enumerations in libitm.h.  */
22
#define PR_INSTRUMENTEDCODE     0x0001
23
#define PR_UNINSTRUMENTEDCODE   0x0002
24
#define PR_HASNOXMMUPDATE       0x0004
25
#define PR_HASNOABORT           0x0008
26
#define PR_HASNOIRREVOCABLE     0x0020
27
#define PR_DOESGOIRREVOCABLE    0x0040
28
#define PR_HASNOSIMPLEREADS     0x0080
29
#define PR_AWBARRIERSOMITTED    0x0100
30
#define PR_RARBARRIERSOMITTED   0x0200
31
#define PR_UNDOLOGCODE          0x0400
32
#define PR_PREFERUNINSTRUMENTED 0x0800
33
#define PR_EXCEPTIONBLOCK       0x1000
34
#define PR_HASELSE              0x2000
35
#define PR_READONLY             0x4000

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.