OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libgcc/] [config/] [arm/] [bpabi.S] - Blame information for rev 777

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 734 jeremybenn
/* Miscellaneous BPABI functions.
2
 
3
   Copyright (C) 2003, 2004, 2007, 2008, 2009, 2010
4
   Free Software Foundation, Inc.
5
   Contributed by CodeSourcery, LLC.
6
 
7
   This file is free software; you can redistribute it and/or modify it
8
   under the terms of the GNU General Public License as published by the
9
   Free Software Foundation; either version 3, or (at your option) any
10
   later version.
11
 
12
   This file is distributed in the hope that it will be useful, but
13
   WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
   General Public License for more details.
16
 
17
   Under Section 7 of GPL version 3, you are granted additional
18
   permissions described in the GCC Runtime Library Exception, version
19
   3.1, as published by the Free Software Foundation.
20
 
21
   You should have received a copy of the GNU General Public License and
22
   a copy of the GCC Runtime Library Exception along with this program;
23
   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
24
   .  */
25
 
26
#ifdef __ARM_EABI__
27
/* Some attributes that are common to all routines in this file.  */
28
        /* Tag_ABI_align_needed: This code does not require 8-byte
29
           alignment from the caller.  */
30
        /* .eabi_attribute 24, 0  -- default setting.  */
31
        /* Tag_ABI_align_preserved: This code preserves 8-byte
32
           alignment in any callee.  */
33
        .eabi_attribute 25, 1
34
#endif /* __ARM_EABI__ */
35
 
36
#ifdef L_aeabi_lcmp
37
 
38
ARM_FUNC_START aeabi_lcmp
39
        cmp     xxh, yyh
40
        do_it   lt
41
        movlt   r0, #-1
42
        do_it   gt
43
        movgt   r0, #1
44
        do_it   ne
45
        RETc(ne)
46
        subs    r0, xxl, yyl
47
        do_it   lo
48
        movlo   r0, #-1
49
        do_it   hi
50
        movhi   r0, #1
51
        RET
52
        FUNC_END aeabi_lcmp
53
 
54
#endif /* L_aeabi_lcmp */
55
 
56
#ifdef L_aeabi_ulcmp
57
 
58
ARM_FUNC_START aeabi_ulcmp
59
        cmp     xxh, yyh
60
        do_it   lo
61
        movlo   r0, #-1
62
        do_it   hi
63
        movhi   r0, #1
64
        do_it   ne
65
        RETc(ne)
66
        cmp     xxl, yyl
67
        do_it   lo
68
        movlo   r0, #-1
69
        do_it   hi
70
        movhi   r0, #1
71
        do_it   eq
72
        moveq   r0, #0
73
        RET
74
        FUNC_END aeabi_ulcmp
75
 
76
#endif /* L_aeabi_ulcmp */
77
 
78
.macro test_div_by_zero signed
79
/* Tail-call to divide-by-zero handlers which may be overridden by the user,
80
   so unwinding works properly.  */
81
#if defined(__thumb2__)
82
        cbnz    yyh, 1f
83
        cbnz    yyl, 1f
84
        cmp     xxh, #0
85
        do_it   eq
86
        cmpeq   xxl, #0
87
        .ifc \signed, unsigned
88
        beq     2f
89
        mov     xxh, #0xffffffff
90
        mov     xxl, xxh
91
2:
92
        .else
93
        do_it   lt, t
94
        movlt   xxl, #0
95
        movlt   xxh, #0x80000000
96
        do_it   gt, t
97
        movgt   xxh, #0x7fffffff
98
        movgt   xxl, #0xffffffff
99
        .endif
100
        b       SYM (__aeabi_ldiv0) __PLT__
101
1:
102
#else
103
        /* Note: Thumb-1 code calls via an ARM shim on processors which
104
           support ARM mode.  */
105
        cmp     yyh, #0
106
        cmpeq   yyl, #0
107
        bne     2f
108
        cmp     xxh, #0
109
        cmpeq   xxl, #0
110
        .ifc \signed, unsigned
111
        movne   xxh, #0xffffffff
112
        movne   xxl, #0xffffffff
113
        .else
114
        movlt   xxh, #0x80000000
115
        movlt   xxl, #0
116
        movgt   xxh, #0x7fffffff
117
        movgt   xxl, #0xffffffff
118
        .endif
119
        b       SYM (__aeabi_ldiv0) __PLT__
120
2:
121
#endif
122
.endm
123
 
124
#ifdef L_aeabi_ldivmod
125
 
126
ARM_FUNC_START aeabi_ldivmod
127
        test_div_by_zero signed
128
 
129
        sub sp, sp, #8
130
#if defined(__thumb2__)
131
        mov ip, sp
132
        push {ip, lr}
133
#else
134
        do_push {sp, lr}
135
#endif
136
        bl SYM(__gnu_ldivmod_helper) __PLT__
137
        ldr lr, [sp, #4]
138
        add sp, sp, #8
139
        do_pop {r2, r3}
140
        RET
141
 
142
#endif /* L_aeabi_ldivmod */
143
 
144
#ifdef L_aeabi_uldivmod
145
 
146
ARM_FUNC_START aeabi_uldivmod
147
        test_div_by_zero unsigned
148
 
149
        sub sp, sp, #8
150
#if defined(__thumb2__)
151
        mov ip, sp
152
        push {ip, lr}
153
#else
154
        do_push {sp, lr}
155
#endif
156
        bl SYM(__gnu_uldivmod_helper) __PLT__
157
        ldr lr, [sp, #4]
158
        add sp, sp, #8
159
        do_pop {r2, r3}
160
        RET
161
 
162
#endif /* L_aeabi_divmod */
163
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.