OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libgcc/] [config/] [cr16/] [divmodhi3.c] - Blame information for rev 818

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 734 jeremybenn
/* Libgcc Target specific implementation - Emulating div and mod.
2
   Copyright (C) 2012 Free Software Foundation, Inc.
3
   Contributed by KPIT Cummins Infosystems Limited.
4
 
5
   This file is part of GCC.
6
 
7
   GCC is free software; you can redistribute it and/or modify it
8
   under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   GCC is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   Under Section 7 of GPL version 3, you are granted additional
18
   permissions described in the GCC Runtime Library Exception, version
19
   3.1, as published by the Free Software Foundation.
20
 
21
   You should have received a copy of the GNU General Public License and
22
   a copy of the GCC Runtime Library Exception along with this program;
23
   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
24
   <http://www.gnu.org/licenses/>.  */
25
 
26
 
27
/* Emulate the division and modulus operation.  */
28
 
29
unsigned short
30
udivmodhi4 (unsigned short num, unsigned short den, short modwanted)
31
{
32
  unsigned short bit = 1;
33
  unsigned short res = 0;
34
 
35
  while (den < num && bit && !(den & (1 << 15)))
36
    {
37
      den <<= 1;
38
      bit <<= 1;
39
    }
40
  while (bit)
41
    {
42
      if (num >= den)
43
        {
44
          num -= den;
45
          res |= bit;
46
        }
47
      bit >>= 1;
48
      den >>= 1;
49
    }
50
 
51
  if (modwanted)
52
    return num;
53
  return res;
54
}
55
 
56
short
57
__divhi3 (short a, short b)
58
{
59
  short neg = 0;
60
  short res;
61
 
62
  if (a < 0)
63
    {
64
      a = -a;
65
      neg = !neg;
66
    }
67
 
68
  if (b < 0)
69
    {
70
      b = -b;
71
      neg = !neg;
72
    }
73
 
74
  res = udivmodhi4 (a, b, 0);
75
 
76
  if (neg)
77
    res = -res;
78
 
79
  return res;
80
}
81
 
82
short
83
__modhi3 (short a, short b)
84
{
85
  short neg = 0;
86
  short res;
87
 
88
  if (a < 0)
89
    {
90
      a = -a;
91
      neg = 1;
92
    }
93
 
94
  if (b < 0)
95
    b = -b;
96
 
97
  res = udivmodhi4 (a, b, 1);
98
 
99
  if (neg)
100
    res = -res;
101
 
102
  return res;
103
}
104
 
105
short
106
__udivhi3 (short a, short b)
107
{
108
  return udivmodhi4 (a, b, 0);
109
}
110
 
111
short
112
__umodhi3 (short a, short b)
113
{
114
  return udivmodhi4 (a, b, 1);
115
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.