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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libgcc/] [config/] [epiphany/] [ieee-754/] [ordsf2.S] - Blame information for rev 734

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1 734 jeremybenn
/* Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
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   Contributed by Embecosm on behalf of Adapteva, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
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.  */
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#include "../epiphany-asm.h"
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        FSTAB (__ordsf2,T_INT)
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        .global SYM(__ordsf2)
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        .balign 8,,2
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        HIDDEN_FUNC(__ordsf2)
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SYM(__ordsf2):
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#ifndef FLOAT_FORMAT_MOTOROLA
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        mov     TMP0,0
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        movt    TMP0,0xff00
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        lsl     TMP1,r0,1
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        sub     TMP1,TMP1,TMP0
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        bgtu    .Lret
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        lsl     TMP1,r1,1
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        sub     TMP1,TMP1,TMP0
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.Lret:  rts /* ordered: lteu */
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#else
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        /* Assumption: NaNs have all bits 9..30 and one of bit 0..8 set.  */
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        lsl     TMP0,r0,1
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        add     TMP0,TMP0,0x3fe
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        bgteu   .Lret
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        lsl     TMP0,r1,1
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        add     TMP0,TMP0,0x3fe
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.Lret:  rts /* ordered: ltu */
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#endif
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        ENDFUNC(__ordsf2)

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