OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libgcc/] [config/] [epiphany/] [modsi3-float.S] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 734 jeremybenn
/* Unsigned 32 bit division optimized for Epiphany.
2
   Copyright (C) 2009, 2011 Free Software Foundation, Inc.
3
   Contributed by Embecosm on behalf of Adapteva, Inc.
4
 
5
This file is part of GCC.
6
 
7
This file is free software; you can redistribute it and/or modify it
8
under the terms of the GNU General Public License as published by the
9
Free Software Foundation; either version 3, or (at your option) any
10
later version.
11
 
12
This file is distributed in the hope that it will be useful, but
13
WITHOUT ANY WARRANTY; without even the implied warranty of
14
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
General Public License for more details.
16
 
17
Under Section 7 of GPL version 3, you are granted additional
18
permissions described in the GCC Runtime Library Exception, version
19
3.1, as published by the Free Software Foundation.
20
 
21
You should have received a copy of the GNU General Public License and
22
a copy of the GCC Runtime Library Exception along with this program;
23
see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
24
.  */
25
 
26
#include "epiphany-asm.h"
27
 
28
        FSTAB (__modsi3,T_UINT)
29
        .global SYM(__modsi3)
30
        .balign 4
31
        HIDDEN_FUNC(__modsi3)
32
SYM(__modsi3):
33
        asr TMP3,r0,31 ; save sign
34
         float TMP0,r0
35
        float TMP1,r1
36
         mov r2,0
37
        sub TMP4,r2,r0
38
        beq .Lret_r0
39
        movgt r0,TMP4
40
        sub TMP2,r2,r1
41
        movlte TMP2,r1
42
        sub r2,TMP0,TMP1
43
        lsl r2,r2,1
44
        blte .L0step
45
        asr TMP4,r2,24
46
        lsl r2,TMP4,3
47
        mov TMP4,%low(.L0step)
48
        movt TMP4,%high(.L0step)
49
        sub r2,TMP4,r2
50
        jr r2
51
#define STEP(n) lsl.l r2,TMP2,n` sub r2,r0,r2` movgteu r0,r2
52
        .balign 8,,2
53
        STEP(31)` STEP(30)` STEP(29)` STEP(28)`
54
        STEP(27)` STEP(26)` STEP(25)` STEP(24)`
55
        STEP(23)` STEP(22)` STEP(21)` STEP(20)`
56
        STEP(19)` STEP(18)` STEP(17)` STEP(16)`
57
        STEP(15)` STEP(14)` STEP(13)` STEP(12)`
58
        STEP(11)` STEP(10)` STEP(9)`  STEP(8)`
59
        STEP(7)` STEP(6)` STEP(5)` STEP(4)` STEP(3)` STEP(2)` STEP(1)
60
.L0step:STEP(0)
61
        eor r0,r0,TMP3 ; restore sign
62
        sub r0,r0,TMP3
63
.Lret_r0:
64
        rts
65
        ENDFUNC(__modsi3)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.