OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libgcc/] [config/] [epiphany/] [umodsi3.S] - Blame information for rev 734

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 734 jeremybenn
/* Unsigned 32 bit modulo optimized for Epiphany.
2
   Copyright (C) 2009 Free Software Foundation, Inc.
3
   Contributed by Embecosm on behalf of Adapteva, Inc.
4
 
5
This file is part of GCC.
6
 
7
This file is free software; you can redistribute it and/or modify it
8
under the terms of the GNU General Public License as published by the
9
Free Software Foundation; either version 3, or (at your option) any
10
later version.
11
 
12
This file is distributed in the hope that it will be useful, but
13
WITHOUT ANY WARRANTY; without even the implied warranty of
14
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
General Public License for more details.
16
 
17
Under Section 7 of GPL version 3, you are granted additional
18
permissions described in the GCC Runtime Library Exception, version
19
3.1, as published by the Free Software Foundation.
20
 
21
You should have received a copy of the GNU General Public License and
22
a copy of the GCC Runtime Library Exception along with this program;
23
see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
24
.  */
25
 
26
#include "epiphany-asm.h"
27
 
28
        FSTAB (__umodsi3,T_UINT)
29
        .global SYM(__umodsi3)
30
        .balign 4
31
        HIDDEN_FUNC(__umodsi3)
32
SYM(__umodsi3):
33
        mov r2,5
34
        lsl r2,r2,29 ; 0xa0000000
35
        orr r3,r2,r0
36
        lsr r15,r0,16
37
        movt r15,0xa800
38
        movne r3,r15
39
        lsr r16,r2,2 ; 0x28000000
40
        and r15,r3,r16
41
        fadd r12,r3,r15
42
         orr r3,r2,r1
43
        lsr r2,r1,16
44
        movt r2,0xa800
45
        movne r3,r2
46
        and r2,r16,r3
47
        fadd r3,r3,r2
48
         sub r2,r0,r1
49
        bltu .Lret_a
50
        lsr r12,r12,23
51
        mov r2,%low(.L0step)
52
        movt r2,%high(.L0step)
53
        lsr r3,r3,23
54
        sub r3,r12,r3 ; calculate bit number difference.
55
        lsl r3,r3,3
56
        sub r2,r2,r3
57
        jr r2
58
/*              lsl_l r2,r1,n`               sub r2,r0,r2` movgteu r0,r2  */
59
#define STEP(n) .long 0x0006441f | (n) << 5` sub r2,r0,r2` movgteu r0,r2
60
        .balign 8,,2
61
        STEP(31)` STEP(30)` STEP(29)` STEP(28)`
62
        STEP(27)` STEP(26)` STEP(25)` STEP(24)`
63
        STEP(23)` STEP(22)` STEP(21)` STEP(20)`
64
        STEP(19)` STEP(18)` STEP(17)` STEP(16)`
65
        STEP(15)` STEP(14)` STEP(13)` STEP(12)`
66
        STEP(11)` STEP(10)` STEP(9)`  STEP(8)`
67
        STEP(7)` STEP(6)` STEP(5)` STEP(4)` STEP(3)` STEP(2)` STEP(1)
68
.L0step:STEP(0)
69
.Lret_a:rts
70
        ENDFUNC(__umodsi3)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.