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734 |
jeremybenn |
#define _FP_W_TYPE_SIZE 64
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#define _FP_W_TYPE unsigned long long
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#define _FP_WS_TYPE signed long long
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#define _FP_I_TYPE long long
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typedef int TItype __attribute__ ((mode (TI)));
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typedef unsigned int UTItype __attribute__ ((mode (TI)));
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#define TI_BITS (__CHAR_BIT__ * (int)sizeof(TItype))
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/* The type of the result of a floating point comparison. This must
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match `__libgcc_cmp_return__' in GCC for the target. */
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typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
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#define CMPtype __gcc_CMPtype
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#define _FP_MUL_MEAT_Q(R,X,Y) \
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_FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
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#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
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#define _FP_NANFRAC_S _FP_QNANBIT_S
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#define _FP_NANFRAC_D _FP_QNANBIT_D
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#define _FP_NANFRAC_E _FP_QNANBIT_E, 0
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#define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0
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#define _FP_NANSIGN_S 1
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#define _FP_NANSIGN_D 1
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#define _FP_NANSIGN_E 1
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#define _FP_NANSIGN_Q 1
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#define _FP_KEEPNANFRACP 1
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/* Here is something Intel misdesigned: the specs don't define
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the case where we have two NaNs with same mantissas, but
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different sign. Different operations pick up different NaNs. */
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#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
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do { \
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if (_FP_FRAC_GT_##wc(X, Y) \
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|| (_FP_FRAC_EQ_##wc(X,Y) && (OP == '+' || OP == '*'))) \
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{ \
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R##_s = X##_s; \
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_FP_FRAC_COPY_##wc(R,X); \
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} \
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else \
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{ \
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R##_s = Y##_s; \
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_FP_FRAC_COPY_##wc(R,Y); \
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} \
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R##_c = FP_CLS_NAN; \
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} while (0)
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#define FP_EX_INVALID 0x01
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#define FP_EX_DENORM 0x02
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#define FP_EX_DIVZERO 0x04
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#define FP_EX_OVERFLOW 0x08
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#define FP_EX_UNDERFLOW 0x10
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#define FP_EX_INEXACT 0x20
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struct fenv
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{
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unsigned short int __control_word;
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unsigned short int __unused1;
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unsigned short int __status_word;
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unsigned short int __unused2;
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unsigned short int __tags;
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unsigned short int __unused3;
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unsigned int __eip;
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unsigned short int __cs_selector;
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unsigned int __opcode:11;
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unsigned int __unused4:5;
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unsigned int __data_offset;
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unsigned short int __data_selector;
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unsigned short int __unused5;
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};
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#ifdef __AVX__
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#define ASM_INVALID "vdivss %0, %0, %0"
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#define ASM_DIVZERO "vdivss %1, %0, %0"
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#else
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#define ASM_INVALID "divss %0, %0"
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#define ASM_DIVZERO "divss %1, %0"
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#endif
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#define FP_HANDLE_EXCEPTIONS \
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do { \
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if (_fex & FP_EX_INVALID) \
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{ \
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float f = 0.0; \
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__asm__ __volatile__ (ASM_INVALID : : "x" (f)); \
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} \
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if (_fex & FP_EX_DIVZERO) \
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{ \
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float f = 1.0, g = 0.0; \
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__asm__ __volatile__ (ASM_DIVZERO : : "x" (f), "x" (g)); \
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} \
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if (_fex & FP_EX_OVERFLOW) \
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{ \
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struct fenv temp; \
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__asm__ __volatile__ ("fnstenv %0" : "=m" (temp)); \
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temp.__status_word |= FP_EX_OVERFLOW; \
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__asm__ __volatile__ ("fldenv %0" : : "m" (temp)); \
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__asm__ __volatile__ ("fwait"); \
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} \
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if (_fex & FP_EX_UNDERFLOW) \
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{ \
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struct fenv temp; \
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__asm__ __volatile__ ("fnstenv %0" : "=m" (temp)); \
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temp.__status_word |= FP_EX_UNDERFLOW; \
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__asm__ __volatile__ ("fldenv %0" : : "m" (temp)); \
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__asm__ __volatile__ ("fwait"); \
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} \
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if (_fex & FP_EX_INEXACT) \
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{ \
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struct fenv temp; \
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__asm__ __volatile__ ("fnstenv %0" : "=m" (temp)); \
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temp.__status_word |= FP_EX_INEXACT; \
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__asm__ __volatile__ ("fldenv %0" : : "m" (temp)); \
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__asm__ __volatile__ ("fwait"); \
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} \
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} while (0)
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#define FP_RND_NEAREST 0
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#define FP_RND_ZERO 0xc00
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#define FP_RND_PINF 0x800
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#define FP_RND_MINF 0x400
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#define _FP_DECL_EX \
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unsigned short _fcw __attribute__ ((unused)) = FP_RND_NEAREST
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#define FP_INIT_ROUNDMODE \
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do { \
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__asm__ ("fnstcw %0" : "=m" (_fcw)); \
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} while (0)
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#define FP_ROUNDMODE (_fcw & 0xc00)
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#define __LITTLE_ENDIAN 1234
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#define __BIG_ENDIAN 4321
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#define __BYTE_ORDER __LITTLE_ENDIAN
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/* Define ALIASNAME as a strong alias for NAME. */
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#if defined __MACH__
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/* Mach-O doesn't support aliasing. If these functions ever return
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anything but CMPtype we need to revisit this... */
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#define strong_alias(name, aliasname) \
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CMPtype aliasname (TFtype a, TFtype b) { return name(a, b); }
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#else
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# define strong_alias(name, aliasname) _strong_alias(name, aliasname)
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# define _strong_alias(name, aliasname) \
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extern __typeof (name) aliasname __attribute__ ((alias (#name)));
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#endif
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