URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libgcc/] [config/] [rl78/] [mulsi3.S] - Blame information for rev 849

Go to most recent revision | Details | Compare with Previous | View Log


;   Copyright (C) 2011 Free Software Foundation, Inc.
;   Contributed by Red Hat.
;
; This file is free software; you can redistribute it and/or modify it
; under the terms of the GNU General Public License as published by the
; Free Software Foundation; either version 3, or (at your option) any
; later version.
;
; This file is distributed in the hope that it will be useful, but
; WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
; General Public License for more details.
;
; Under Section 7 of GPL version 3, you are granted additional
; permissions described in the GCC Runtime Library Exception, version
; 3.1, as published by the Free Software Foundation.
;
; You should have received a copy of the GNU General Public License and
; a copy of the GCC Runtime Library Exception along with this program;
; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
; .
 
;; 32x32=32 multiply
 
; real
; GAS defines r0..r7 as aliases for real registers; we want the saddr
; forms here.
r_0     =       0xffef8
r_1     =       0xffef9
r_2     =       0xffefa
r_3     =       0xffefb
r_4     =       0xffefc
r_5     =       0xffefd
r_6     =       0xffefe
r_7     =       0xffeff
; clobberable
r8      =       0xffef0
r9      =       0xffef1
r10     =       0xffef2
r11     =       0xffef3
r12     =       0xffef4
r13     =       0xffef5
r14     =       0xffef6
r15     =       0xffef7
; preserved
r16     =       0xffee8
r17     =       0xffee9
r18     =       0xffeea
r19     =       0xffeeb
r20     =       0xffeec
r21     =       0xffeed
r22     =       0xffeee
r23     =       0xffeef
 
 
;----------------------------------------------------------------------
 
; Register use:
;       RB0     RB1     RB2
; AX    op2L    res32L  res32H
; BC    op2H    (resH)  op1
; DE    count   (resL-tmp)
; HL    [sp+4]
 
        .text
        nop
        .global ___mulsi3               ; (USI a, USI b)
___mulsi3:
        ;; A is at [sp+4]
        ;; B is at [sp+8]
        ;; result is in R8..R11
 
        movw    ax, sp
        addw    ax, #4
        movw    hl, ax
 
        sel     rb2
        push    ax
        push    bc
        sel     rb0
 
        clrw    ax
        movw    r8, ax
        movw    r16, ax
 
        movw    ax, [hl+6]
        cmpw    ax, #0
        bz      $1f
        cmpw    ax, #0xffff
        bnz     $2f
        movw    ax, [hl]
        sel     rb1
        subw    ax, r_0
        sel     rb0
        br      $1f
2:
        movw    bc, ax
        movw    ax, [hl]
        cmpw    ax, #0
        skz
        call    !.Lmul_hi
1:
 
        movw    ax, [hl+2]
        cmpw    ax, #0
        bz      $1f
        cmpw    ax, #0xffff
        bnz     $2f
        movw    ax, [hl+4]
        sel     rb1
        subw    ax, r_0
        sel     rb0
        br      $1f
2:
        movw    bc, ax
        movw    ax, [hl+4]
        cmpw    ax, #0
        skz
        call    !.Lmul_hi
1:
 
        movw    ax, r8
        movw    r16, ax
        clrw    ax
        movw    r8, ax
 
        ;; now do R16:R8 += op1L * op2L
 
        ;; op1 is in AX.0 (needs to shrw)
        ;; op2 is in BC.2 and BC.1 (bc can shlw/rolcw)
        ;; res is in AX.2 and AX.1 (needs to addw)
 
        movw    ax, [hl]
        movw    r10, ax         ; BC.1
        movw    ax, [hl+4]
 
        cmpw    ax, r10
        bc      $.Lmul_hisi_top
        movw    bc, r10
        movw    r10, ax
        movw    ax, bc
 
 
.Lmul_hisi_top:
        movw    bc, #0
 
.Lmul_hisi_loop:
        shrw    ax, 1
        bnc     $.Lmul_hisi_no_add
        sel     rb1
        addw    ax, bc
        sel     rb2
        sknc
        incw    ax
        addw    ax, r_2
.Lmul_hisi_no_add:
        sel     rb1
        shlw    bc, 1
        sel     rb0
        rolwc   bc, 1
        cmpw    ax, #0
        bz      $.Lmul_hisi_done
 
        shrw    ax, 1
        bnc     $.Lmul_hisi_no_add2
        sel     rb1
        addw    ax, bc
        sel     rb2
        sknc
        incw    ax
        addw    ax, r_2
.Lmul_hisi_no_add2:
        sel     rb1
        shlw    bc, 1
        sel     rb0
        rolwc   bc, 1
        cmpw    ax, #0
        bnz     $.Lmul_hisi_loop
 
.Lmul_hisi_done:
 
        movw    ax, r16
        movw    r10, ax
 
        sel     rb2
        pop     bc
        pop     ax
        sel     rb0
 
        ret
 
;----------------------------------------------------------------------
 
        ;; R8 += AX * BC
.Lmul_hi:
        cmpw    ax, bc
        skc
        xchw    ax, bc
        br      $.Lmul_hi_loop
 
.Lmul_hi_top:
        sel     rb1
        addw    ax, r_2
        sel     rb0
.Lmul_hi_no_add:
        shlw    bc, 1
.Lmul_hi_loop:
        shrw    ax, 1
        bc      $.Lmul_hi_top
        cmpw    ax, #0
        bz      $.Lmul_hi_done
 
        shlw    bc, 1
        shrw    ax, 1
        bc      $.Lmul_hi_top
        cmpw    ax, #0
        bnz     $.Lmul_hi_no_add
 
.Lmul_hi_done:
        ret
 
;----------------------------------------------------------------------
 
        .global ___mulhi3
___mulhi3:
        sel     rb1
        clrw    ax
        sel     rb0
        movw    ax, sp
        addw    ax, #4
        movw    hl, ax
        movw    ax, [hl+2]
        movw    bc, ax
        movw    ax, [hl]
        br      $.Lmul_hi

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libgcc/] [config/] [rl78/] [mulsi3.S] - Blame information for rev 849

Line No.	Rev	Author	Line
1	734	jeremybenn	`; Copyright (C) 2011 Free Software Foundation, Inc.`
2			`; Contributed by Red Hat.`
3			`;`
4			`; This file is free software; you can redistribute it and/or modify it`
5			`; under the terms of the GNU General Public License as published by the`
6			`; Free Software Foundation; either version 3, or (at your option) any`
7			`; later version.`
8			`;`
9			`; This file is distributed in the hope that it will be useful, but`
10			`; WITHOUT ANY WARRANTY; without even the implied warranty of`
11			`; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
12			`; General Public License for more details.`
13			`;`
14			`; Under Section 7 of GPL version 3, you are granted additional`
15			`; permissions described in the GCC Runtime Library Exception, version`
16			`; 3.1, as published by the Free Software Foundation.`
17			`;`
18			`; You should have received a copy of the GNU General Public License and`
19			`; a copy of the GCC Runtime Library Exception along with this program;`
20			`; see the files COPYING3 and COPYING.RUNTIME respectively. If not, see`
21			`; .`
22
23			`;; 32x32=32 multiply`
24
25			`; real`
26			`; GAS defines r0..r7 as aliases for real registers; we want the saddr`
27			`; forms here.`
28			`r_0 = 0xffef8`
29			`r_1 = 0xffef9`
30			`r_2 = 0xffefa`
31			`r_3 = 0xffefb`
32			`r_4 = 0xffefc`
33			`r_5 = 0xffefd`
34			`r_6 = 0xffefe`
35			`r_7 = 0xffeff`
36			`; clobberable`
37			`r8 = 0xffef0`
38			`r9 = 0xffef1`
39			`r10 = 0xffef2`
40			`r11 = 0xffef3`
41			`r12 = 0xffef4`
42			`r13 = 0xffef5`
43			`r14 = 0xffef6`
44			`r15 = 0xffef7`
45			`; preserved`
46			`r16 = 0xffee8`
47			`r17 = 0xffee9`
48			`r18 = 0xffeea`
49			`r19 = 0xffeeb`
50			`r20 = 0xffeec`
51			`r21 = 0xffeed`
52			`r22 = 0xffeee`
53			`r23 = 0xffeef`
54
55
56			`;----------------------------------------------------------------------`
57
58			`; Register use:`
59			`; RB0 RB1 RB2`
60			`; AX op2L res32L res32H`
61			`; BC op2H (resH) op1`
62			`; DE count (resL-tmp)`
63			`; HL [sp+4]`
64
65			`.text`
66			`nop`
67			`.global ___mulsi3 ; (USI a, USI b)`
68			`___mulsi3:`
69			`;; A is at [sp+4]`
70			`;; B is at [sp+8]`
71			`;; result is in R8..R11`
72
73			`movw ax, sp`
74			`addw ax, #4`
75			`movw hl, ax`
76
77			`sel rb2`
78			`push ax`
79			`push bc`
80			`sel rb0`
81
82			`clrw ax`
83			`movw r8, ax`
84			`movw r16, ax`
85
86			`movw ax, [hl+6]`
87			`cmpw ax, #0`
88			`bz $1f`
89			`cmpw ax, #0xffff`
90			`bnz $2f`
91			`movw ax, [hl]`
92			`sel rb1`
93			`subw ax, r_0`
94			`sel rb0`
95			`br $1f`
96			`2:`
97			`movw bc, ax`
98			`movw ax, [hl]`
99			`cmpw ax, #0`
100			`skz`
101			`call !.Lmul_hi`
102			`1:`
103
104			`movw ax, [hl+2]`
105			`cmpw ax, #0`
106			`bz $1f`
107			`cmpw ax, #0xffff`
108			`bnz $2f`
109			`movw ax, [hl+4]`
110			`sel rb1`
111			`subw ax, r_0`
112			`sel rb0`
113			`br $1f`
114			`2:`
115			`movw bc, ax`
116			`movw ax, [hl+4]`
117			`cmpw ax, #0`
118			`skz`
119			`call !.Lmul_hi`
120			`1:`
121
122			`movw ax, r8`
123			`movw r16, ax`
124			`clrw ax`
125			`movw r8, ax`
126
127			`;; now do R16:R8 += op1L * op2L`
128
129			`;; op1 is in AX.0 (needs to shrw)`
130			`;; op2 is in BC.2 and BC.1 (bc can shlw/rolcw)`
131			`;; res is in AX.2 and AX.1 (needs to addw)`
132
133			`movw ax, [hl]`
134			`movw r10, ax ; BC.1`
135			`movw ax, [hl+4]`
136
137			`cmpw ax, r10`
138			`bc $.Lmul_hisi_top`
139			`movw bc, r10`
140			`movw r10, ax`
141			`movw ax, bc`
142
143
144			`.Lmul_hisi_top:`
145			`movw bc, #0`
146
147			`.Lmul_hisi_loop:`
148			`shrw ax, 1`
149			`bnc $.Lmul_hisi_no_add`
150			`sel rb1`
151			`addw ax, bc`
152			`sel rb2`
153			`sknc`
154			`incw ax`
155			`addw ax, r_2`
156			`.Lmul_hisi_no_add:`
157			`sel rb1`
158			`shlw bc, 1`
159			`sel rb0`
160			`rolwc bc, 1`
161			`cmpw ax, #0`
162			`bz $.Lmul_hisi_done`
163
164			`shrw ax, 1`
165			`bnc $.Lmul_hisi_no_add2`
166			`sel rb1`
167			`addw ax, bc`
168			`sel rb2`
169			`sknc`
170			`incw ax`
171			`addw ax, r_2`
172			`.Lmul_hisi_no_add2:`
173			`sel rb1`
174			`shlw bc, 1`
175			`sel rb0`
176			`rolwc bc, 1`
177			`cmpw ax, #0`
178			`bnz $.Lmul_hisi_loop`
179
180			`.Lmul_hisi_done:`
181
182			`movw ax, r16`
183			`movw r10, ax`
184
185			`sel rb2`
186			`pop bc`
187			`pop ax`
188			`sel rb0`
189
190			`ret`
191
192			`;----------------------------------------------------------------------`
193
194			`;; R8 += AX * BC`
195			`.Lmul_hi:`
196			`cmpw ax, bc`
197			`skc`
198			`xchw ax, bc`
199			`br $.Lmul_hi_loop`
200
201			`.Lmul_hi_top:`
202			`sel rb1`
203			`addw ax, r_2`
204			`sel rb0`
205			`.Lmul_hi_no_add:`
206			`shlw bc, 1`
207			`.Lmul_hi_loop:`
208			`shrw ax, 1`
209			`bc $.Lmul_hi_top`
210			`cmpw ax, #0`
211			`bz $.Lmul_hi_done`
212
213			`shlw bc, 1`
214			`shrw ax, 1`
215			`bc $.Lmul_hi_top`
216			`cmpw ax, #0`
217			`bnz $.Lmul_hi_no_add`
218
219			`.Lmul_hi_done:`
220			`ret`
221
222			`;----------------------------------------------------------------------`
223
224			`.global ___mulhi3`
225			`___mulhi3:`
226			`sel rb1`
227			`clrw ax`
228			`sel rb0`
229			`movw ax, sp`
230			`addw ax, #4`
231			`movw hl, ax`
232			`movw ax, [hl+2]`
233			`movw bc, ax`
234			`movw ax, [hl]`
235			`br $.Lmul_hi`