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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libgcc/] [config/] [tilepro/] [softmpy.S] - Blame information for rev 777

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1 734 jeremybenn
/* 64-bit multiplication support for TILEPro.
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   Copyright (C) 2011, 2012
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   Free Software Foundation, Inc.
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   Contributed by Walter Lee (walt@tilera.com)
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   This file is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the
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   Free Software Foundation; either version 3, or (at your option) any
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   later version.
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   This file is distributed in the hope that it will be useful, but
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   WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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   General Public License for more details.
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   Under Section 7 of GPL version 3, you are granted additional
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   permissions described in the GCC Runtime Library Exception, version
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   3.1, as published by the Free Software Foundation.
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   You should have received a copy of the GNU General Public License and
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   a copy of the GCC Runtime Library Exception along with this program;
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   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
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   .  */
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/* 64-bit multiplication support.  */
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        .file "softmpy.S"
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/* Parameters */
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#define lo0             r9   /* low 32 bits of n0  */
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#define hi0             r1   /* high 32 bits of n0 */
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#define lo1             r2   /* low 32 bits of n1  */
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#define hi1             r3   /* high 32 bits of n1 */
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/* temps */
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#define result1_a       r4
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#define result1_b       r5
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#define tmp0            r6
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#define tmp0_left_16    r7
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#define tmp1            r8
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        .section .text.__muldi3, "ax"
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        .align 8
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        .globl __muldi3
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        .type __muldi3, @function
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__muldi3:
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        {
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         move        lo0, r0 /* so we can write "out r0" while "in r0" alive */
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         mulhl_uu    tmp0, lo1, r0
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        }
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        {
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         mulll_uu    result1_a, lo1, hi0
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        }
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        {
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         move        tmp1, tmp0
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         mulhla_uu   tmp0, lo0, lo1
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        }
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        {
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         mulhlsa_uu  result1_a, lo1, hi0
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        }
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        {
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         mulll_uu    result1_b, lo0, hi1
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         slt_u       tmp1, tmp0, tmp1
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        }
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        {
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         mulhlsa_uu  result1_a, lo0, hi1
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         shli        r0, tmp0, 16
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        }
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        {
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         move        tmp0_left_16, r0
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         mulhha_uu   result1_b, lo0, lo1
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        }
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        {
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         mullla_uu   r0, lo1, lo0
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         shli        tmp1, tmp1, 16
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        }
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        {
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         mulhlsa_uu  result1_b, hi0, lo1
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         inthh       tmp1, tmp1, tmp0
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        }
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        {
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         mulhlsa_uu  result1_a, hi1, lo0
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         slt_u       tmp0, r0, tmp0_left_16
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        }
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        /* NOTE: this will stall for a cycle here. Oh well. */
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        {
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         add         r1, tmp0, tmp1
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         add         result1_a, result1_a, result1_b
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        }
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        {
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         add         r1, r1, result1_a
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         jrp         lr
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        }
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        .size __muldi3,.-__muldi3

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