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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libitm/] [config/] [linux/] [x86/] [tls.h] - Blame information for rev 737

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1 737 jeremybenn
/* Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
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   Contributed by Richard Henderson <rth@redhat.com>.
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   This file is part of the GNU Transactional Memory Library (libitm).
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   Libitm is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3 of the License, or
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   (at your option) any later version.
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   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
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   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   Under Section 7 of GPL version 3, you are granted additional
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   permissions described in the GCC Runtime Library Exception, version
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   3.1, as published by the Free Software Foundation.
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   You should have received a copy of the GNU General Public License and
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   a copy of the GCC Runtime Library Exception along with this program;
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   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
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   <http://www.gnu.org/licenses/>.  */
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#ifndef LIBITM_X86_TLS_H
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#define LIBITM_X86_TLS_H 1
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#if defined(__GLIBC_PREREQ) && __GLIBC_PREREQ(2, 10)
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/* Use slots in the TCB head rather than __thread lookups.
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   GLIBC has reserved words 10 through 13 for TM.  */
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#define HAVE_ARCH_GTM_THREAD 1
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#define HAVE_ARCH_GTM_THREAD_DISP 1
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#endif
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#include "config/generic/tls.h"
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#if defined(__GLIBC_PREREQ) && __GLIBC_PREREQ(2, 10)
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namespace GTM HIDDEN {
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#ifdef __x86_64__
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#ifdef __LP64__
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# define SEG_READ(OFS)          "movq\t%%fs:(" #OFS "*8),%0"
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# define SEG_WRITE(OFS)         "movq\t%0,%%fs:(" #OFS "*8)"
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# define SEG_DECODE_READ(OFS)   SEG_READ(OFS) "\n\t" \
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                                "rorq\t$17,%0\n\t" \
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                                "xorq\t%%fs:48,%0"
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# define SEG_ENCODE_WRITE(OFS)  "xorq\t%%fs:48,%0\n\t" \
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                                "rolq\t$17,%0\n\t" \
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                                SEG_WRITE(OFS)
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#else
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// For X32.
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# define SEG_READ(OFS)          "movl\t%%fs:(" #OFS "*4),%0"
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# define SEG_WRITE(OFS)         "movl\t%0,%%fs:(" #OFS "*4)"
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# define SEG_DECODE_READ(OFS)   SEG_READ(OFS) "\n\t" \
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                                "rorl\t$9,%0\n\t" \
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                                "xorl\t%%fs:24,%0"
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# define SEG_ENCODE_WRITE(OFS)  "xorl\t%%fs:24,%0\n\t" \
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                                "roll\t$9,%0\n\t" \
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                                SEG_WRITE(OFS)
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#endif
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#else
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# define SEG_READ(OFS)  "movl\t%%gs:(" #OFS "*4),%0"
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# define SEG_WRITE(OFS) "movl\t%0,%%gs:(" #OFS "*4)"
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# define SEG_DECODE_READ(OFS)   SEG_READ(OFS) "\n\t" \
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                                "rorl\t$9,%0\n\t" \
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                                "xorl\t%%gs:24,%0"
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# define SEG_ENCODE_WRITE(OFS)  "xorl\t%%gs:24,%0\n\t" \
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                                "roll\t$9,%0\n\t" \
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                                SEG_WRITE(OFS)
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#endif
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static inline struct gtm_thread *gtm_thr(void)
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{
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  struct gtm_thread *r;
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  asm volatile (SEG_READ(10) : "=r"(r));
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  return r;
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}
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static inline void set_gtm_thr(struct gtm_thread *x)
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{
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  asm volatile (SEG_WRITE(10) : : "r"(x));
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}
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static inline struct abi_dispatch *abi_disp(void)
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{
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  struct abi_dispatch *r;
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  asm volatile (SEG_DECODE_READ(11) : "=r"(r));
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  return r;
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}
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static inline void set_abi_disp(struct abi_dispatch *x)
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{
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  void *scratch;
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  asm volatile (SEG_ENCODE_WRITE(11) : "=r"(scratch) : "0"(x));
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}
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#undef SEG_READ
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#undef SEG_WRITE
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#undef SEG_DECODE_READ
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#undef SEG_ENCODE_WRITE
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} // namespace GTM
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#endif /* >= GLIBC 2.10 */
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#endif // LIBITM_X86_TLS_H

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