OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libitm/] [config/] [sparc/] [target.h] - Blame information for rev 737

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 737 jeremybenn
/* Copyright (C) 2012 Free Software Foundation, Inc.
2
 
3
   This file is part of the GNU Transactional Memory Library (libitm).
4
 
5
   Libitm is free software; you can redistribute it and/or modify it
6
   under the terms of the GNU General Public License as published by
7
   the Free Software Foundation; either version 3 of the License, or
8
   (at your option) any later version.
9
 
10
   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
11
   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
12
   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
   more details.
14
 
15
   Under Section 7 of GPL version 3, you are granted additional
16
   permissions described in the GCC Runtime Library Exception, version
17
   3.1, as published by the Free Software Foundation.
18
 
19
   You should have received a copy of the GNU General Public License and
20
   a copy of the GCC Runtime Library Exception along with this program;
21
   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
22
   <http://www.gnu.org/licenses/>.  */
23
 
24
namespace GTM HIDDEN {
25
 
26
typedef struct gtm_jmpbuf
27
{
28
  void *cfa;
29
  unsigned long pc;
30
} gtm_jmpbuf;
31
 
32
/* UltraSPARC processors generally use a fixed page size of 8K.  */
33
#define PAGE_SIZE       8192
34
#define FIXED_PAGE_SIZE 1
35
 
36
/* The size of one line in hardware caches (in bytes).  We use the primary
37
   cache line size documented for the UltraSPARC T1/T2.  */
38
#define HW_CACHELINE_SIZE 16
39
 
40
static inline void
41
cpu_relax (void)
42
{
43
  __asm volatile ("rd %%ccr, %%g0" : : : "memory");
44
}
45
 
46
} // namespace GTM

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.