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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libjava/] [include/] [s390-signal.h] - Blame information for rev 791

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1 757 jeremybenn
// s390-signal.h - Catch runtime signals and turn them into exceptions
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// on an s390 based Linux system.
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/* Copyright (C) 2002, 2010  Free Software Foundation
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   This file is part of libgcj.
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This software is copyrighted work licensed under the terms of the
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Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
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details.  */
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#ifndef JAVA_SIGNAL_H
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#define JAVA_SIGNAL_H 1
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#include <signal.h>
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#include <sys/syscall.h>
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#include <ucontext.h>
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#include <limits.h>
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#define HANDLE_SEGV 1
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#define HANDLE_FPE 1
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#define SIGNAL_HANDLER(_name)   \
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static void _name (int, siginfo_t *_si __attribute__((unused)), \
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                   ucontext_t *_uc __attribute__((unused)))
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/* We no longer need to fiddle with the PSW address in the signal handler;
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   this is now all handled correctly in MD_FALLBACK_FRAME_STATE_FOR.  */
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#define MAKE_THROW_FRAME(_exception)
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/* According to the JVM spec, "if the dividend is the negative integer
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   of the smallest magnitude and the divisor is -1, then overflow occurs
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   and the result is equal to the dividend.  Despite the overflow, no
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   exception occurs".
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   We handle this by inspecting the instruction which generated the signal,
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   and if dividend and divisor are as above, we simply return from the signal
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   handler.  This causes execution to continue after the instruction.
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   Before returning, we the set result registers as expected.  */
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#define UC_EXTENDED     0x00000001
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#define HANDLE_DIVIDE_OVERFLOW                                          \
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do                                                                      \
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{                                                                       \
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  unsigned char *_eip = (unsigned char *)                               \
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    __builtin_extract_return_addr (_si->si_addr);                       \
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  unsigned long *_regs = _uc->uc_mcontext.gregs;                        \
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  int _r1, _r2, _d2, _x2, _b2;                                          \
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  struct                                                                \
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  {                                                                     \
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    unsigned long int uc_flags;                                         \
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    struct ucontext *uc_link;                                           \
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    stack_t uc_stack;                                                   \
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    mcontext_t uc_mcontext;                                             \
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    unsigned long sigmask[2];                                           \
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    unsigned long ext_regs[16];                                         \
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  } *_uc_ext = (typeof(_uc_ext))_uc;                                    \
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                                                                        \
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  /* First, a couple of helper routines to decode instructions.  */     \
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  struct _decode                                                        \
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    {                                                                   \
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      /* Decode RR instruction format.  */                              \
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      static inline int _is_rr (unsigned char *_eip,                    \
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                                unsigned char _op,                      \
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                                int *_r1, int *_r2)                     \
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      {                                                                 \
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        if (_eip[0] == _op)                                              \
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          {                                                             \
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            *_r1 = _eip[1] >> 4;                                        \
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            *_r2 = _eip[1] & 0xf;                                       \
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            return 1;                                                   \
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          }                                                             \
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        return 0;                                                        \
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      }                                                                 \
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                                                                        \
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      /* Decode RX instruction format.  */                              \
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      static inline int _is_rx (unsigned char *_eip,                    \
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                                unsigned char _op,                      \
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                                int *_r1, int *_d2, int *_x2, int *_b2) \
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      {                                                                 \
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        if (_eip[0] == _op)                                              \
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          {                                                             \
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            *_r1 = _eip[1] >> 4;                                        \
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            *_x2 = _eip[1] & 0xf;                                       \
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            *_b2 = _eip[2] >> 4;                                        \
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            *_d2 = ((_eip[2] & 0xf) << 8) + _eip[3];                    \
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            return 1;                                                   \
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          }                                                             \
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        return 0;                                                        \
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      }                                                                 \
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                                                                        \
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      /* Decode RRE instruction format.  */                             \
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      static inline int _is_rre (unsigned char *_eip,                   \
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                                 unsigned char _op1, unsigned char _op2,\
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                                 int *_r1, int *_r2)                    \
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      {                                                                 \
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        if (_eip[0] == _op1 && _eip[1] == _op2)                          \
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          {                                                             \
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            *_r1 = _eip[3] >> 4;                                        \
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            *_r2 = _eip[3] & 0xf;                                       \
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            return 1;                                                   \
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          }                                                             \
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        return 0;                                                        \
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      }                                                                 \
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                                                                        \
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      /* Decode RXY instruction format.  */                             \
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      static inline int _is_rxy (unsigned char *_eip,                   \
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                                 unsigned char _op1, unsigned char _op2,\
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                                 int *_r1, int *_d2, int *_x2, int *_b2)\
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      {                                                                 \
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        if (_eip[0] == _op1 && _eip[5] == _op2)                          \
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          {                                                             \
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            *_r1 = _eip[1] >> 4;                                        \
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            *_x2 = _eip[1] & 0xf;                                       \
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            *_b2 = _eip[2] >> 4;                                        \
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            *_d2 = ((_eip[2] & 0xf) << 8) + _eip[3] + (_eip[4] << 12);  \
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            /* We have a 20-bit signed displacement.  */                \
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            *_d2 = (*_d2 ^ 0x80000) - 0x80000;                          \
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            return 1;                                                   \
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          }                                                             \
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        return 0;                                                        \
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      }                                                                 \
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                                                                        \
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      /* Compute effective address.  */                                 \
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      static inline unsigned long _eff (unsigned long *_regs,           \
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                                        long _d, int _x, int _b)        \
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      {                                                                 \
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        return _d + (_x? _regs[_x] : 0) + (_b? _regs[_b] : 0);            \
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      }                                                                 \
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                                                                        \
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      static inline int is_long_long_min_p (unsigned long *_regs,       \
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                                            unsigned long *_ext_regs,   \
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                                            int _r)                     \
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      {                                                                 \
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        return ((long long)_regs[_r]                                    \
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                | (long long)_ext_regs[_r] << 32) ==                    \
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          LONG_LONG_MIN;                                                \
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      }                                                                 \
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  };                                                                    \
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                                                                        \
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  /* DR r1,r2 */                                                        \
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  if (_decode::_is_rr (_eip, 0x1d, &_r1, &_r2)                          \
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      && (int) _regs[_r1] == -1 && (int) _regs[_r1+1] == INT_MIN        \
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      && (int) _regs[_r2] == -1)                                        \
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    {                                                                   \
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      _regs[_r1] &= ~0xffffffff;                                        \
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      return;                                                           \
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    }                                                                   \
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                                                                        \
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  /* D r1,d2(x2,b2) */                                                  \
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  if (_decode::_is_rx (_eip, 0x5d, &_r1, &_d2, &_x2, &_b2)              \
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      && (int) _regs[_r1] == -1 && (int) _regs[_r1+1] == INT_MIN        \
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      && *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1)           \
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    {                                                                   \
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      _regs[_r1] &= ~0xffffffff;                                        \
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      return;                                                           \
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    }                                                                   \
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                                                                        \
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  /* DSGR r1,r2 */                                                      \
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  if (_decode::_is_rre (_eip, 0xb9, 0x0d, &_r1, &_r2)                   \
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      && (long) _regs[_r1+1] == LONG_MIN                                \
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      && (long) _regs[_r2] == -1L)                                      \
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    {                                                                   \
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      _regs[_r1] = 0;                                                    \
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      return;                                                           \
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    }                                                                   \
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                                                                        \
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  /* DSGFR r1,r2 */                                                     \
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  if (_decode::_is_rre (_eip, 0xb9, 0x1d, &_r1, &_r2)                   \
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      && (long) _regs[_r1+1] == LONG_MIN                                \
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      && (int) _regs[_r2] == -1)                                        \
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    {                                                                   \
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      _regs[_r1] = 0;                                                    \
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      return;                                                           \
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    }                                                                   \
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                                                                        \
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  /* DSG r1,d2(x2,b2) */                                                \
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  if (_decode::_is_rxy (_eip, 0xe3, 0x0d, &_r1, &_d2, &_x2, &_b2)       \
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      && (long) _regs[_r1+1] == LONG_MIN                                \
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      && *(long *) _decode::_eff (_regs, _d2, _x2, _b2) == -1L)         \
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    {                                                                   \
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      _regs[_r1] = 0;                                                    \
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      return;                                                           \
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    }                                                                   \
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                                                                        \
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  /* DSGF r1,d2(x2,b2) */                                               \
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  if (_decode::_is_rxy (_eip, 0xe3, 0x1d, &_r1, &_d2, &_x2, &_b2)       \
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      && (long) _regs[_r1+1] == LONG_MIN                                \
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      && *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1)           \
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    {                                                                   \
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      _regs[_r1] = 0;                                                    \
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      return;                                                           \
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    }                                                                   \
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                                                                        \
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  /* The extended ucontext contains the upper halfs of the 64bit        \
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     registers in 31bit applications.  */                               \
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  if (_uc->uc_flags & 1 == 1)                                           \
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    {                                                                   \
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      /* DSGR r1,r2 */                                                  \
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      if (_decode::_is_rre (_eip, 0xb9, 0x0d, &_r1, &_r2)               \
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          && (int) _regs[_r2] == -1                                     \
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          && (int) _uc_ext->ext_regs[_r2] == -1                         \
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          && _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs,     \
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                                          _r1 + 1))                     \
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        {                                                               \
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          _regs[_r1] = 0;                                                \
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          _uc_ext->ext_regs[_r1] = 0;                                    \
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          return;                                                       \
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        }                                                               \
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                                                                        \
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      /* DSGFR r1,r2 */                                                 \
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      if (_decode::_is_rre (_eip, 0xb9, 0x1d, &_r1, &_r2)               \
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          && (int) _regs[_r2] == -1                                     \
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          && _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs,     \
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                                          _r1 + 1))                     \
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        {                                                               \
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          _regs[_r1] = 0;                                                \
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          _uc_ext->ext_regs[_r1] = 0;                                    \
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          return;                                                       \
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        }                                                               \
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                                                                        \
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      /* DSG r1,d2(x2,b2) */                                            \
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      if (_decode::_is_rxy (_eip, 0xe3, 0x0d, &_r1, &_d2, &_x2, &_b2)   \
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          && *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1        \
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          && *(int *) _decode::_eff (_regs, _d2 + 4, _x2, _b2) == -1    \
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          && _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs,     \
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                                          _r1 + 1))                     \
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        {                                                               \
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          _regs[_r1] = 0;                                                \
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          _uc_ext->ext_regs[_r1] = 0;                                    \
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          return;                                                       \
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        }                                                               \
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                                                                        \
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      /* DSGF r1,d2(x2,b2) */                                           \
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      if (_decode::_is_rxy (_eip, 0xe3, 0x1d, &_r1, &_d2, &_x2, &_b2)   \
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          && *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1        \
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          && _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs,     \
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                                          _r1 + 1))                     \
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        {                                                               \
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          _regs[_r1] = 0;                                                \
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          _uc_ext->ext_regs[_r1] = 0;                                    \
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          return;                                                       \
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        }                                                               \
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    }                                                                   \
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 }                                                                      \
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while (0)
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/* For an explanation why we cannot simply use sigaction to
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   install the handlers, see i386-signal.h.  */
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/* We use old_kernel_sigaction here because we're calling the kernel
254
   directly rather than via glibc.  The sigaction structure that the
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   syscall uses is a different shape from the one in userland and not
256
   visible to us in a header file so we define it here.  */
257
 
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struct old_s390_kernel_sigaction {
259
        void (*k_sa_handler) (int, siginfo_t *, ucontext_t *);
260
        unsigned long k_sa_mask;
261
        unsigned long k_sa_flags;
262
        void (*sa_restorer) (void);
263
};
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#define INIT_SEGV                                       \
266
do                                                      \
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  {                                                     \
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    struct old_s390_kernel_sigaction kact;              \
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    kact.k_sa_handler = catch_segv;                     \
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    kact.k_sa_mask = 0;                                  \
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    kact.k_sa_flags = SA_SIGINFO;                       \
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    syscall (SYS_sigaction, SIGSEGV, &kact, NULL);      \
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  }                                                     \
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while (0)
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#define INIT_FPE                                                \
277
do                                                              \
278
  {                                                             \
279
    struct old_s390_kernel_sigaction kact;                      \
280
    kact.k_sa_handler = catch_fpe;                              \
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    kact.k_sa_mask = 0;                                          \
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    kact.k_sa_flags = SA_SIGINFO;                               \
283
    syscall (SYS_sigaction, SIGFPE, &kact, NULL);               \
284
  }                                                             \
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while (0)
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#endif /* JAVA_SIGNAL_H */
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