OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libjava/] [sysdep/] [i386/] [locks.h] - Blame information for rev 778

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 764 jeremybenn
/* locks.h - Thread synchronization primitives. X86/x86-64 implementation.
2
 
3
   Copyright (C) 2002, 2011  Free Software Foundation
4
 
5
   This file is part of libgcj.
6
 
7
This software is copyrighted work licensed under the terms of the
8
Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
9
details.  */
10
 
11
#ifndef __SYSDEP_LOCKS_H__
12
#define __SYSDEP_LOCKS_H__
13
 
14
typedef size_t obj_addr_t;      /* Integer type big enough for object   */
15
                                /* address.                             */
16
 
17
// Atomically replace *addr by new_val if it was initially equal to old.
18
// Return true if the comparison succeeded.
19
// Assumed to have acquire semantics, i.e. later memory operations
20
// cannot execute before the compare_and_swap finishes.
21
inline static bool
22
compare_and_swap(volatile obj_addr_t *addr,
23
                 obj_addr_t old,
24
                 obj_addr_t new_val)
25
{
26
  return __sync_bool_compare_and_swap (addr, old, new_val);
27
}
28
 
29
// Ensure that subsequent instructions do not execute on stale
30
// data that was loaded from memory before the barrier.
31
// On X86/x86-64, the hardware ensures that reads are properly ordered.
32
inline static void
33
read_barrier()
34
{
35
}
36
 
37
// Ensure that prior stores to memory are completed with respect to other
38
// processors.
39
inline static void
40
write_barrier()
41
{
42
  /* x86-64/X86 does not reorder writes. We just need to ensure that
43
     gcc also doesn't.  */
44
  __asm__ __volatile__(" " : : : "memory");
45
}
46
 
47
// Set *addr to new_val with release semantics, i.e. making sure
48
// that prior loads and stores complete before this
49
// assignment.
50
// On X86/x86-64, the hardware shouldn't reorder reads and writes,
51
// so we just have to convince gcc not to do it either.
52
inline static void
53
release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
54
{
55
  write_barrier ();
56
  *(addr) = new_val;
57
}
58
 
59
// Compare_and_swap with release semantics instead of acquire semantics.
60
// On many architecture, the operation makes both guarantees, so the
61
// implementation can be the same.
62
inline static bool
63
compare_and_swap_release(volatile obj_addr_t *addr,
64
                         obj_addr_t old,
65
                         obj_addr_t new_val)
66
{
67
  return compare_and_swap(addr, old, new_val);
68
}
69
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.