OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libjava/] [sysdep/] [sh/] [locks.h] - Blame information for rev 848

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 764 jeremybenn
// locks.h - Thread synchronization primitives. SuperH implementation.
2
 
3
/* Copyright (C) 2002, 2007  Free Software Foundation
4
 
5
   This file is part of libgcj.
6
 
7
This software is copyrighted work licensed under the terms of the
8
Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
9
details.  */
10
 
11
#ifndef __SYSDEP_LOCKS_H__
12
#define __SYSDEP_LOCKS_H__
13
 
14
typedef size_t obj_addr_t;      /* Integer type big enough for object   */
15
                                /* address.                             */
16
 
17
static unsigned char __cas_lock = 0;
18
 
19
inline static void
20
__cas_start_atomic (void)
21
{
22
  unsigned int val;
23
 
24
  do
25
    __asm__ __volatile__ ("tas.b @%1; movt %0"
26
                          : "=r" (val)
27
                          : "r" (&__cas_lock)
28
                          : "memory");
29
  while (val == 0);
30
}
31
 
32
inline static void
33
__cas_end_atomic (void)
34
{
35
  __asm__ __volatile__ (" " : : : "memory");
36
  __cas_lock = 0;
37
}
38
 
39
inline static bool
40
compare_and_swap (volatile obj_addr_t *addr, obj_addr_t old,
41
                  obj_addr_t new_val)
42
{
43
  bool ret;
44
 
45
  __cas_start_atomic ();
46
  if (*addr != old)
47
    ret = false;
48
  else
49
    {
50
      *addr = new_val;
51
      ret = true;
52
    }
53
  __cas_end_atomic ();
54
 
55
  return ret;
56
}
57
 
58
inline static void
59
release_set (volatile obj_addr_t *addr, obj_addr_t new_val)
60
{
61
  __asm__ __volatile__ (" " : : : "memory");
62
  *(addr) = new_val;
63
}
64
 
65
inline static bool
66
compare_and_swap_release (volatile obj_addr_t *addr, obj_addr_t old,
67
                          obj_addr_t new_val)
68
{
69
  return compare_and_swap (addr, old, new_val);
70
}
71
 
72
inline static void
73
read_barrier()
74
{
75
  __asm__ __volatile__(" " : : : "memory");
76
}
77
 
78
inline static void
79
write_barrier()
80
{
81
  __asm__ __volatile__(" " : : : "memory");
82
}
83
 
84
#endif /* ! __SYSDEP_LOCKS_H__ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.