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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [libjava/] [sysdep/] [sparc/] [locks.h] - Blame information for rev 764

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1 764 jeremybenn
// locks.h - Thread synchronization primitives. Sparc implementation.
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/* Copyright (C) 2002, 2007  Free Software Foundation
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   This file is part of libgcj.
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This software is copyrighted work licensed under the terms of the
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Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
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details.  */
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#ifndef __SYSDEP_LOCKS_H__
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#define __SYSDEP_LOCKS_H__
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typedef size_t obj_addr_t;      /* Integer type big enough for object   */
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                                /* address.                             */
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#ifdef __arch64__
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/* Sparc64 implementation, use cas instruction.  */
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inline static bool
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compare_and_swap(volatile obj_addr_t *addr,
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                 obj_addr_t old,
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                 obj_addr_t new_val)
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{
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  __asm__ __volatile__("casx [%2], %3, %0\n\t"
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                       "membar #StoreLoad | #StoreStore"
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                       : "=&r" (new_val)
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                       : "0" (new_val), "r" (addr), "r" (old)
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                       : "memory");
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  return (new_val == old) ? true : false;
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}
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inline static void
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release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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{
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  __asm__ __volatile__("membar #StoreStore | #LoadStore" : : : "memory");
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  *(addr) = new_val;
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}
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inline static bool
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compare_and_swap_release(volatile obj_addr_t *addr, obj_addr_t old,
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                         obj_addr_t new_val)
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{
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  return compare_and_swap(addr, old, new_val);
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}
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inline static void
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read_barrier()
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{
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  __asm__ __volatile__("membar #LoadLoad | #LoadStore" : : : "memory");
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}
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inline static void
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write_barrier()
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{
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  __asm__ __volatile__("membar #StoreLoad | #StoreStore" : : : "memory");
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}
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#else
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/* Sparc32 implementation, use a spinlock.  */
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static unsigned char __cas_lock = 0;
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inline static void
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__cas_start_atomic(void)
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{
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  unsigned int tmp;
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  __asm__ __volatile__(
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"1:     ldstub  [%1], %0\n"
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"       orcc    %0, 0x0, %%g0\n"
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"       be      3f\n"
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"        nop\n"
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"2:     ldub    [%1], %0\n"
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"       orcc    %0, 0x0, %%g0\n"
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"       bne     2b\n"
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"        nop\n"
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"3:"    : "=&r" (tmp)
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        : "r" (&__cas_lock)
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        : "memory", "cc");
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}
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inline static void
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__cas_end_atomic(void)
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{
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  __asm__ __volatile__(
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  "stb %%g0, [%0]"
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  : /* no outputs */
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  : "r" (&__cas_lock)
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  : "memory");
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}
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inline static bool
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compare_and_swap(volatile obj_addr_t *addr,
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                 obj_addr_t old,
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                 obj_addr_t new_val)
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{
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  bool ret;
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  __cas_start_atomic ();
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  if (*addr != old)
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    {
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      ret = false;
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    }
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  else
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    {
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      *addr = new_val;
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      ret = true;
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    }
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  __cas_end_atomic ();
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  return ret;
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}
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inline static void
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release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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{
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  /* Technically stbar would be needed here but no sparc32
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     system actually requires it.  Also the stbar would mean
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     this code would not work on sparcv7 chips.  */
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  __asm__ __volatile__("" : : : "memory");
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  *(addr) = new_val;
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}
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inline static bool
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compare_and_swap_release(volatile obj_addr_t *addr, obj_addr_t old,
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                         obj_addr_t new_val)
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{
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  return compare_and_swap(addr, old, new_val);
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}
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inline static void
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read_barrier()
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{
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  __asm__ __volatile__ ("" : : : "memory");
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}
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inline static void
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write_barrier()
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{
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  __asm__ __volatile__ ("" : : : "memory");
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}
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#endif /* __arch64__ */
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#endif /* ! __SYSDEP_LOCKS_H__ */

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