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@section Relocations
2
BFD maintains relocations in much the same way it maintains
3
symbols: they are left alone until required, then read in
4
en-masse and translated into an internal form.  A common
5
routine @code{bfd_perform_relocation} acts upon the
6
canonical form to do the fixup.
7
 
8
Relocations are maintained on a per section basis,
9
while symbols are maintained on a per BFD basis.
10
 
11
All that a back end has to do to fit the BFD interface is to create
12
a @code{struct reloc_cache_entry} for each relocation
13
in a particular section, and fill in the right bits of the structures.
14
 
15
@menu
16
* typedef arelent::
17
* howto manager::
18
@end menu
19
 
20
 
21
@node typedef arelent, howto manager, Relocations, Relocations
22
@subsection typedef arelent
23
This is the structure of a relocation entry:
24
 
25
 
26
@example
27
 
28
typedef enum bfd_reloc_status
29
@{
30
  /* No errors detected.  */
31
  bfd_reloc_ok,
32
 
33
  /* The relocation was performed, but there was an overflow.  */
34
  bfd_reloc_overflow,
35
 
36
  /* The address to relocate was not within the section supplied.  */
37
  bfd_reloc_outofrange,
38
 
39
  /* Used by special functions.  */
40
  bfd_reloc_continue,
41
 
42
  /* Unsupported relocation size requested.  */
43
  bfd_reloc_notsupported,
44
 
45
  /* Unused.  */
46
  bfd_reloc_other,
47
 
48
  /* The symbol to relocate against was undefined.  */
49
  bfd_reloc_undefined,
50
 
51
  /* The relocation was performed, but may not be ok - presently
52
     generated only when linking i960 coff files with i960 b.out
53
     symbols.  If this type is returned, the error_message argument
54
     to bfd_perform_relocation will be set.  */
55
  bfd_reloc_dangerous
56
 @}
57
 bfd_reloc_status_type;
58
 
59
 
60
typedef struct reloc_cache_entry
61
@{
62
  /* A pointer into the canonical table of pointers.  */
63
  struct bfd_symbol **sym_ptr_ptr;
64
 
65
  /* offset in section.  */
66
  bfd_size_type address;
67
 
68
  /* addend for relocation value.  */
69
  bfd_vma addend;
70
 
71
  /* Pointer to how to perform the required relocation.  */
72
  reloc_howto_type *howto;
73
 
74
@}
75
arelent;
76
 
77
@end example
78
@strong{Description}@*
79
Here is a description of each of the fields within an @code{arelent}:
80
 
81
@itemize @bullet
82
 
83
@item
84
@code{sym_ptr_ptr}
85
@end itemize
86
The symbol table pointer points to a pointer to the symbol
87
associated with the relocation request.  It is the pointer
88
into the table returned by the back end's
89
@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is
90
referenced through a pointer to a pointer so that tools like
91
the linker can fix up all the symbols of the same name by
92
modifying only one pointer. The relocation routine looks in
93
the symbol and uses the base of the section the symbol is
94
attached to and the value of the symbol as the initial
95
relocation offset. If the symbol pointer is zero, then the
96
section provided is looked up.
97
 
98
@itemize @bullet
99
 
100
@item
101
@code{address}
102
@end itemize
103
The @code{address} field gives the offset in bytes from the base of
104
the section data which owns the relocation record to the first
105
byte of relocatable information. The actual data relocated
106
will be relative to this point; for example, a relocation
107
type which modifies the bottom two bytes of a four byte word
108
would not touch the first byte pointed to in a big endian
109
world.
110
 
111
@itemize @bullet
112
 
113
@item
114
@code{addend}
115
@end itemize
116
The @code{addend} is a value provided by the back end to be added (!)
117
to the relocation offset. Its interpretation is dependent upon
118
the howto. For example, on the 68k the code:
119
 
120
@example
121
        char foo[];
122
        main()
123
                @{
124
                return foo[0x12345678];
125
                @}
126
@end example
127
 
128
Could be compiled into:
129
 
130
@example
131
        linkw fp,#-4
132
        moveb @@#12345678,d0
133
        extbl d0
134
        unlk fp
135
        rts
136
@end example
137
 
138
This could create a reloc pointing to @code{foo}, but leave the
139
offset in the data, something like:
140
 
141
@example
142
RELOCATION RECORDS FOR [.text]:
143
offset   type      value
144
00000006 32        _foo
145
 
146
00000000 4e56 fffc          ; linkw fp,#-4
147
00000004 1039 1234 5678     ; moveb @@#12345678,d0
148
0000000a 49c0               ; extbl d0
149
0000000c 4e5e               ; unlk fp
150
0000000e 4e75               ; rts
151
@end example
152
 
153
Using coff and an 88k, some instructions don't have enough
154
space in them to represent the full address range, and
155
pointers have to be loaded in two parts. So you'd get something like:
156
 
157
@example
158
        or.u     r13,r0,hi16(_foo+0x12345678)
159
        ld.b     r2,r13,lo16(_foo+0x12345678)
160
        jmp      r1
161
@end example
162
 
163
This should create two relocs, both pointing to @code{_foo}, and with
164
0x12340000 in their addend field. The data would consist of:
165
 
166
@example
167
RELOCATION RECORDS FOR [.text]:
168
offset   type      value
169
00000002 HVRT16    _foo+0x12340000
170
00000006 LVRT16    _foo+0x12340000
171
 
172
00000000 5da05678           ; or.u r13,r0,0x5678
173
00000004 1c4d5678           ; ld.b r2,r13,0x5678
174
00000008 f400c001           ; jmp r1
175
@end example
176
 
177
The relocation routine digs out the value from the data, adds
178
it to the addend to get the original offset, and then adds the
179
value of @code{_foo}. Note that all 32 bits have to be kept around
180
somewhere, to cope with carry from bit 15 to bit 16.
181
 
182
One further example is the sparc and the a.out format. The
183
sparc has a similar problem to the 88k, in that some
184
instructions don't have room for an entire offset, but on the
185
sparc the parts are created in odd sized lumps. The designers of
186
the a.out format chose to not use the data within the section
187
for storing part of the offset; all the offset is kept within
188
the reloc. Anything in the data should be ignored.
189
 
190
@example
191
        save %sp,-112,%sp
192
        sethi %hi(_foo+0x12345678),%g2
193
        ldsb [%g2+%lo(_foo+0x12345678)],%i0
194
        ret
195
        restore
196
@end example
197
 
198
Both relocs contain a pointer to @code{foo}, and the offsets
199
contain junk.
200
 
201
@example
202
RELOCATION RECORDS FOR [.text]:
203
offset   type      value
204
00000004 HI22      _foo+0x12345678
205
00000008 LO10      _foo+0x12345678
206
 
207
00000000 9de3bf90     ; save %sp,-112,%sp
208
00000004 05000000     ; sethi %hi(_foo+0),%g2
209
00000008 f048a000     ; ldsb [%g2+%lo(_foo+0)],%i0
210
0000000c 81c7e008     ; ret
211
00000010 81e80000     ; restore
212
@end example
213
 
214
@itemize @bullet
215
 
216
@item
217
@code{howto}
218
@end itemize
219
The @code{howto} field can be imagined as a
220
relocation instruction. It is a pointer to a structure which
221
contains information on what to do with all of the other
222
information in the reloc record and data section. A back end
223
would normally have a relocation instruction set and turn
224
relocations into pointers to the correct structure on input -
225
but it would be possible to create each howto field on demand.
226
 
227
@subsubsection @code{enum complain_overflow}
228
Indicates what sort of overflow checking should be done when
229
performing a relocation.
230
 
231
 
232
@example
233
 
234
enum complain_overflow
235
@{
236
  /* Do not complain on overflow.  */
237
  complain_overflow_dont,
238
 
239
  /* Complain if the value overflows when considered as a signed
240
     number one bit larger than the field.  ie. A bitfield of N bits
241
     is allowed to represent -2**n to 2**n-1.  */
242
  complain_overflow_bitfield,
243
 
244
  /* Complain if the value overflows when considered as a signed
245
     number.  */
246
  complain_overflow_signed,
247
 
248
  /* Complain if the value overflows when considered as an
249
     unsigned number.  */
250
  complain_overflow_unsigned
251
@};
252
@end example
253
@subsubsection @code{reloc_howto_type}
254
The @code{reloc_howto_type} is a structure which contains all the
255
information that libbfd needs to know to tie up a back end's data.
256
 
257
 
258
@example
259
struct bfd_symbol;             /* Forward declaration.  */
260
 
261
struct reloc_howto_struct
262
@{
263
  /*  The type field has mainly a documentary use - the back end can
264
      do what it wants with it, though normally the back end's
265
      external idea of what a reloc number is stored
266
      in this field.  For example, a PC relative word relocation
267
      in a coff environment has the type 023 - because that's
268
      what the outside world calls a R_PCRWORD reloc.  */
269
  unsigned int type;
270
 
271
  /*  The value the final relocation is shifted right by.  This drops
272
      unwanted data from the relocation.  */
273
  unsigned int rightshift;
274
 
275
  /*  The size of the item to be relocated.  This is *not* a
276
      power-of-two measure.  To get the number of bytes operated
277
      on by a type of relocation, use bfd_get_reloc_size.  */
278
  int size;
279
 
280
  /*  The number of bits in the item to be relocated.  This is used
281
      when doing overflow checking.  */
282
  unsigned int bitsize;
283
 
284
  /*  Notes that the relocation is relative to the location in the
285
      data section of the addend.  The relocation function will
286
      subtract from the relocation value the address of the location
287
      being relocated.  */
288
  bfd_boolean pc_relative;
289
 
290
  /*  The bit position of the reloc value in the destination.
291
      The relocated value is left shifted by this amount.  */
292
  unsigned int bitpos;
293
 
294
  /* What type of overflow error should be checked for when
295
     relocating.  */
296
  enum complain_overflow complain_on_overflow;
297
 
298
  /* If this field is non null, then the supplied function is
299
     called rather than the normal function.  This allows really
300
     strange relocation methods to be accommodated (e.g., i960 callj
301
     instructions).  */
302
  bfd_reloc_status_type (*special_function)
303
    (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
304
     bfd *, char **);
305
 
306
  /* The textual name of the relocation type.  */
307
  char *name;
308
 
309
  /* Some formats record a relocation addend in the section contents
310
     rather than with the relocation.  For ELF formats this is the
311
     distinction between USE_REL and USE_RELA (though the code checks
312
     for USE_REL == 1/0).  The value of this field is TRUE if the
313
     addend is recorded with the section contents; when performing a
314
     partial link (ld -r) the section contents (the data) will be
315
     modified.  The value of this field is FALSE if addends are
316
     recorded with the relocation (in arelent.addend); when performing
317
     a partial link the relocation will be modified.
318
     All relocations for all ELF USE_RELA targets should set this field
319
     to FALSE (values of TRUE should be looked on with suspicion).
320
     However, the converse is not true: not all relocations of all ELF
321
     USE_REL targets set this field to TRUE.  Why this is so is peculiar
322
     to each particular target.  For relocs that aren't used in partial
323
     links (e.g. GOT stuff) it doesn't matter what this is set to.  */
324
  bfd_boolean partial_inplace;
325
 
326
  /* src_mask selects the part of the instruction (or data) to be used
327
     in the relocation sum.  If the target relocations don't have an
328
     addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
329
     dst_mask to extract the addend from the section contents.  If
330
     relocations do have an addend in the reloc, eg. ELF USE_RELA, this
331
     field should be zero.  Non-zero values for ELF USE_RELA targets are
332
     bogus as in those cases the value in the dst_mask part of the
333
     section contents should be treated as garbage.  */
334
  bfd_vma src_mask;
335
 
336
  /* dst_mask selects which parts of the instruction (or data) are
337
     replaced with a relocated value.  */
338
  bfd_vma dst_mask;
339
 
340
  /* When some formats create PC relative instructions, they leave
341
     the value of the pc of the place being relocated in the offset
342
     slot of the instruction, so that a PC relative relocation can
343
     be made just by adding in an ordinary offset (e.g., sun3 a.out).
344
     Some formats leave the displacement part of an instruction
345
     empty (e.g., m88k bcs); this flag signals the fact.  */
346
  bfd_boolean pcrel_offset;
347
@};
348
 
349
@end example
350
@findex The HOWTO Macro
351
@subsubsection @code{The HOWTO Macro}
352
@strong{Description}@*
353
The HOWTO define is horrible and will go away.
354
@example
355
#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
356
  @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @}
357
@end example
358
 
359
@strong{Description}@*
360
And will be replaced with the totally magic way. But for the
361
moment, we are compatible, so do it this way.
362
@example
363
#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
364
  HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
365
         NAME, FALSE, 0, 0, IN)
366
 
367
@end example
368
 
369
@strong{Description}@*
370
This is used to fill in an empty howto entry in an array.
371
@example
372
#define EMPTY_HOWTO(C) \
373
  HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
374
         NULL, FALSE, 0, 0, FALSE)
375
 
376
@end example
377
 
378
@strong{Description}@*
379
Helper routine to turn a symbol into a relocation value.
380
@example
381
#define HOWTO_PREPARE(relocation, symbol)               \
382
  @{                                                     \
383
    if (symbol != NULL)                                 \
384
      @{                                                 \
385
        if (bfd_is_com_section (symbol->section))       \
386
          @{                                             \
387
            relocation = 0;                             \
388
          @}                                             \
389
        else                                            \
390
          @{                                             \
391
            relocation = symbol->value;                 \
392
          @}                                             \
393
      @}                                                 \
394
  @}
395
 
396
@end example
397
 
398
@findex bfd_get_reloc_size
399
@subsubsection @code{bfd_get_reloc_size}
400
@strong{Synopsis}
401
@example
402
unsigned int bfd_get_reloc_size (reloc_howto_type *);
403
@end example
404
@strong{Description}@*
405
For a reloc_howto_type that operates on a fixed number of bytes,
406
this returns the number of bytes operated on.
407
 
408
@findex arelent_chain
409
@subsubsection @code{arelent_chain}
410
@strong{Description}@*
411
How relocs are tied together in an @code{asection}:
412
@example
413
typedef struct relent_chain
414
@{
415
  arelent relent;
416
  struct relent_chain *next;
417
@}
418
arelent_chain;
419
 
420
@end example
421
 
422
@findex bfd_check_overflow
423
@subsubsection @code{bfd_check_overflow}
424
@strong{Synopsis}
425
@example
426
bfd_reloc_status_type bfd_check_overflow
427
   (enum complain_overflow how,
428
    unsigned int bitsize,
429
    unsigned int rightshift,
430
    unsigned int addrsize,
431
    bfd_vma relocation);
432
@end example
433
@strong{Description}@*
434
Perform overflow checking on @var{relocation} which has
435
@var{bitsize} significant bits and will be shifted right by
436
@var{rightshift} bits, on a machine with addresses containing
437
@var{addrsize} significant bits.  The result is either of
438
@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
439
 
440
@findex bfd_perform_relocation
441
@subsubsection @code{bfd_perform_relocation}
442
@strong{Synopsis}
443
@example
444
bfd_reloc_status_type bfd_perform_relocation
445
   (bfd *abfd,
446
    arelent *reloc_entry,
447
    void *data,
448
    asection *input_section,
449
    bfd *output_bfd,
450
    char **error_message);
451
@end example
452
@strong{Description}@*
453
If @var{output_bfd} is supplied to this function, the
454
generated image will be relocatable; the relocations are
455
copied to the output file after they have been changed to
456
reflect the new state of the world. There are two ways of
457
reflecting the results of partial linkage in an output file:
458
by modifying the output data in place, and by modifying the
459
relocation record.  Some native formats (e.g., basic a.out and
460
basic coff) have no way of specifying an addend in the
461
relocation type, so the addend has to go in the output data.
462
This is no big deal since in these formats the output data
463
slot will always be big enough for the addend. Complex reloc
464
types with addends were invented to solve just this problem.
465
The @var{error_message} argument is set to an error message if
466
this return @code{bfd_reloc_dangerous}.
467
 
468
@findex bfd_install_relocation
469
@subsubsection @code{bfd_install_relocation}
470
@strong{Synopsis}
471
@example
472
bfd_reloc_status_type bfd_install_relocation
473
   (bfd *abfd,
474
    arelent *reloc_entry,
475
    void *data, bfd_vma data_start,
476
    asection *input_section,
477
    char **error_message);
478
@end example
479
@strong{Description}@*
480
This looks remarkably like @code{bfd_perform_relocation}, except it
481
does not expect that the section contents have been filled in.
482
I.e., it's suitable for use when creating, rather than applying
483
a relocation.
484
 
485
For now, this function should be considered reserved for the
486
assembler.
487
 
488
 
489
@node howto manager,  , typedef arelent, Relocations
490
@subsection The howto manager
491
When an application wants to create a relocation, but doesn't
492
know what the target machine might call it, it can find out by
493
using this bit of code.
494
 
495
@findex bfd_reloc_code_type
496
@subsubsection @code{bfd_reloc_code_type}
497
@strong{Description}@*
498
The insides of a reloc code.  The idea is that, eventually, there
499
will be one enumerator for every type of relocation we ever do.
500
Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll
501
return a howto pointer.
502
 
503
This does mean that the application must determine the correct
504
enumerator value; you can't get a howto pointer from a random set
505
of attributes.
506
 
507
Here are the possible values for @code{enum bfd_reloc_code_real}:
508
 
509
@deffn {} BFD_RELOC_64
510
@deffnx {} BFD_RELOC_32
511
@deffnx {} BFD_RELOC_26
512
@deffnx {} BFD_RELOC_24
513
@deffnx {} BFD_RELOC_16
514
@deffnx {} BFD_RELOC_14
515
@deffnx {} BFD_RELOC_8
516
Basic absolute relocations of N bits.
517
@end deffn
518
@deffn {} BFD_RELOC_64_PCREL
519
@deffnx {} BFD_RELOC_32_PCREL
520
@deffnx {} BFD_RELOC_24_PCREL
521
@deffnx {} BFD_RELOC_16_PCREL
522
@deffnx {} BFD_RELOC_12_PCREL
523
@deffnx {} BFD_RELOC_8_PCREL
524
PC-relative relocations.  Sometimes these are relative to the address
525
of the relocation itself; sometimes they are relative to the start of
526
the section containing the relocation.  It depends on the specific target.
527
 
528
The 24-bit relocation is used in some Intel 960 configurations.
529
@end deffn
530
@deffn {} BFD_RELOC_32_SECREL
531
Section relative relocations.  Some targets need this for DWARF2.
532
@end deffn
533
@deffn {} BFD_RELOC_32_GOT_PCREL
534
@deffnx {} BFD_RELOC_16_GOT_PCREL
535
@deffnx {} BFD_RELOC_8_GOT_PCREL
536
@deffnx {} BFD_RELOC_32_GOTOFF
537
@deffnx {} BFD_RELOC_16_GOTOFF
538
@deffnx {} BFD_RELOC_LO16_GOTOFF
539
@deffnx {} BFD_RELOC_HI16_GOTOFF
540
@deffnx {} BFD_RELOC_HI16_S_GOTOFF
541
@deffnx {} BFD_RELOC_8_GOTOFF
542
@deffnx {} BFD_RELOC_64_PLT_PCREL
543
@deffnx {} BFD_RELOC_32_PLT_PCREL
544
@deffnx {} BFD_RELOC_24_PLT_PCREL
545
@deffnx {} BFD_RELOC_16_PLT_PCREL
546
@deffnx {} BFD_RELOC_8_PLT_PCREL
547
@deffnx {} BFD_RELOC_64_PLTOFF
548
@deffnx {} BFD_RELOC_32_PLTOFF
549
@deffnx {} BFD_RELOC_16_PLTOFF
550
@deffnx {} BFD_RELOC_LO16_PLTOFF
551
@deffnx {} BFD_RELOC_HI16_PLTOFF
552
@deffnx {} BFD_RELOC_HI16_S_PLTOFF
553
@deffnx {} BFD_RELOC_8_PLTOFF
554
For ELF.
555
@end deffn
556
@deffn {} BFD_RELOC_68K_GLOB_DAT
557
@deffnx {} BFD_RELOC_68K_JMP_SLOT
558
@deffnx {} BFD_RELOC_68K_RELATIVE
559
Relocations used by 68K ELF.
560
@end deffn
561
@deffn {} BFD_RELOC_32_BASEREL
562
@deffnx {} BFD_RELOC_16_BASEREL
563
@deffnx {} BFD_RELOC_LO16_BASEREL
564
@deffnx {} BFD_RELOC_HI16_BASEREL
565
@deffnx {} BFD_RELOC_HI16_S_BASEREL
566
@deffnx {} BFD_RELOC_8_BASEREL
567
@deffnx {} BFD_RELOC_RVA
568
Linkage-table relative.
569
@end deffn
570
@deffn {} BFD_RELOC_8_FFnn
571
Absolute 8-bit relocation, but used to form an address like 0xFFnn.
572
@end deffn
573
@deffn {} BFD_RELOC_32_PCREL_S2
574
@deffnx {} BFD_RELOC_16_PCREL_S2
575
@deffnx {} BFD_RELOC_23_PCREL_S2
576
These PC-relative relocations are stored as word displacements --
577
i.e., byte displacements shifted right two bits.  The 30-bit word
578
displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
579
SPARC.  (SPARC tools generally refer to this as <<WDISP30>>.)  The
580
signed 16-bit displacement is used on the MIPS, and the 23-bit
581
displacement is used on the Alpha.
582
@end deffn
583
@deffn {} BFD_RELOC_HI22
584
@deffnx {} BFD_RELOC_LO10
585
High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
586
the target word.  These are used on the SPARC.
587
@end deffn
588
@deffn {} BFD_RELOC_GPREL16
589
@deffnx {} BFD_RELOC_GPREL32
590
For systems that allocate a Global Pointer register, these are
591
displacements off that register.  These relocation types are
592
handled specially, because the value the register will have is
593
decided relatively late.
594
@end deffn
595
@deffn {} BFD_RELOC_I960_CALLJ
596
Reloc types used for i960/b.out.
597
@end deffn
598
@deffn {} BFD_RELOC_NONE
599
@deffnx {} BFD_RELOC_SPARC_WDISP22
600
@deffnx {} BFD_RELOC_SPARC22
601
@deffnx {} BFD_RELOC_SPARC13
602
@deffnx {} BFD_RELOC_SPARC_GOT10
603
@deffnx {} BFD_RELOC_SPARC_GOT13
604
@deffnx {} BFD_RELOC_SPARC_GOT22
605
@deffnx {} BFD_RELOC_SPARC_PC10
606
@deffnx {} BFD_RELOC_SPARC_PC22
607
@deffnx {} BFD_RELOC_SPARC_WPLT30
608
@deffnx {} BFD_RELOC_SPARC_COPY
609
@deffnx {} BFD_RELOC_SPARC_GLOB_DAT
610
@deffnx {} BFD_RELOC_SPARC_JMP_SLOT
611
@deffnx {} BFD_RELOC_SPARC_RELATIVE
612
@deffnx {} BFD_RELOC_SPARC_UA16
613
@deffnx {} BFD_RELOC_SPARC_UA32
614
@deffnx {} BFD_RELOC_SPARC_UA64
615
@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22
616
@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10
617
@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22
618
@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10
619
@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP
620
SPARC ELF relocations.  There is probably some overlap with other
621
relocation types already defined.
622
@end deffn
623
@deffn {} BFD_RELOC_SPARC_BASE13
624
@deffnx {} BFD_RELOC_SPARC_BASE22
625
I think these are specific to SPARC a.out (e.g., Sun 4).
626
@end deffn
627
@deffn {} BFD_RELOC_SPARC_64
628
@deffnx {} BFD_RELOC_SPARC_10
629
@deffnx {} BFD_RELOC_SPARC_11
630
@deffnx {} BFD_RELOC_SPARC_OLO10
631
@deffnx {} BFD_RELOC_SPARC_HH22
632
@deffnx {} BFD_RELOC_SPARC_HM10
633
@deffnx {} BFD_RELOC_SPARC_LM22
634
@deffnx {} BFD_RELOC_SPARC_PC_HH22
635
@deffnx {} BFD_RELOC_SPARC_PC_HM10
636
@deffnx {} BFD_RELOC_SPARC_PC_LM22
637
@deffnx {} BFD_RELOC_SPARC_WDISP16
638
@deffnx {} BFD_RELOC_SPARC_WDISP19
639
@deffnx {} BFD_RELOC_SPARC_7
640
@deffnx {} BFD_RELOC_SPARC_6
641
@deffnx {} BFD_RELOC_SPARC_5
642
@deffnx {} BFD_RELOC_SPARC_DISP64
643
@deffnx {} BFD_RELOC_SPARC_PLT32
644
@deffnx {} BFD_RELOC_SPARC_PLT64
645
@deffnx {} BFD_RELOC_SPARC_HIX22
646
@deffnx {} BFD_RELOC_SPARC_LOX10
647
@deffnx {} BFD_RELOC_SPARC_H44
648
@deffnx {} BFD_RELOC_SPARC_M44
649
@deffnx {} BFD_RELOC_SPARC_L44
650
@deffnx {} BFD_RELOC_SPARC_REGISTER
651
SPARC64 relocations
652
@end deffn
653
@deffn {} BFD_RELOC_SPARC_REV32
654
SPARC little endian relocation
655
@end deffn
656
@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22
657
@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10
658
@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD
659
@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL
660
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22
661
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10
662
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD
663
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL
664
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22
665
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10
666
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD
667
@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22
668
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10
669
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD
670
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX
671
@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD
672
@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22
673
@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10
674
@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32
675
@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64
676
@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32
677
@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64
678
@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32
679
@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64
680
SPARC TLS relocations
681
@end deffn
682
@deffn {} BFD_RELOC_SPU_IMM7
683
@deffnx {} BFD_RELOC_SPU_IMM8
684
@deffnx {} BFD_RELOC_SPU_IMM10
685
@deffnx {} BFD_RELOC_SPU_IMM10W
686
@deffnx {} BFD_RELOC_SPU_IMM16
687
@deffnx {} BFD_RELOC_SPU_IMM16W
688
@deffnx {} BFD_RELOC_SPU_IMM18
689
@deffnx {} BFD_RELOC_SPU_PCREL9a
690
@deffnx {} BFD_RELOC_SPU_PCREL9b
691
@deffnx {} BFD_RELOC_SPU_PCREL16
692
@deffnx {} BFD_RELOC_SPU_LO16
693
@deffnx {} BFD_RELOC_SPU_HI16
694
@deffnx {} BFD_RELOC_SPU_PPU32
695
@deffnx {} BFD_RELOC_SPU_PPU64
696
SPU Relocations.
697
@end deffn
698
@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16
699
Alpha ECOFF and ELF relocations.  Some of these treat the symbol or
700
"addend" in some special way.
701
For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
702
writing; when reading, it will be the absolute section symbol.  The
703
addend is the displacement in bytes of the "lda" instruction from
704
the "ldah" instruction (which is at the address of this reloc).
705
@end deffn
706
@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16
707
For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
708
with GPDISP_HI16 relocs.  The addend is ignored when writing the
709
relocations out, and is filled in with the file's GP value on
710
reading, for convenience.
711
@end deffn
712
@deffn {} BFD_RELOC_ALPHA_GPDISP
713
The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
714
relocation except that there is no accompanying GPDISP_LO16
715
relocation.
716
@end deffn
717
@deffn {} BFD_RELOC_ALPHA_LITERAL
718
@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL
719
@deffnx {} BFD_RELOC_ALPHA_LITUSE
720
The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
721
the assembler turns it into a LDQ instruction to load the address of
722
the symbol, and then fills in a register in the real instruction.
723
 
724
The LITERAL reloc, at the LDQ instruction, refers to the .lita
725
section symbol.  The addend is ignored when writing, but is filled
726
in with the file's GP value on reading, for convenience, as with the
727
GPDISP_LO16 reloc.
728
 
729
The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
730
It should refer to the symbol to be referenced, as with 16_GOTOFF,
731
but it generates output not based on the position within the .got
732
section, but relative to the GP value chosen for the file during the
733
final link stage.
734
 
735
The LITUSE reloc, on the instruction using the loaded address, gives
736
information to the linker that it might be able to use to optimize
737
away some literal section references.  The symbol is ignored (read
738
as the absolute section symbol), and the "addend" indicates the type
739
of instruction using the register:
740
1 - "memory" fmt insn
741
2 - byte-manipulation (byte offset reg)
742
3 - jsr (target of branch)
743
@end deffn
744
@deffn {} BFD_RELOC_ALPHA_HINT
745
The HINT relocation indicates a value that should be filled into the
746
"hint" field of a jmp/jsr/ret instruction, for possible branch-
747
prediction logic which may be provided on some processors.
748
@end deffn
749
@deffn {} BFD_RELOC_ALPHA_LINKAGE
750
The LINKAGE relocation outputs a linkage pair in the object file,
751
which is filled by the linker.
752
@end deffn
753
@deffn {} BFD_RELOC_ALPHA_CODEADDR
754
The CODEADDR relocation outputs a STO_CA in the object file,
755
which is filled by the linker.
756
@end deffn
757
@deffn {} BFD_RELOC_ALPHA_GPREL_HI16
758
@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16
759
The GPREL_HI/LO relocations together form a 32-bit offset from the
760
GP register.
761
@end deffn
762
@deffn {} BFD_RELOC_ALPHA_BRSGP
763
Like BFD_RELOC_23_PCREL_S2, except that the source and target must
764
share a common GP, and the target address is adjusted for
765
STO_ALPHA_STD_GPLOAD.
766
@end deffn
767
@deffn {} BFD_RELOC_ALPHA_TLSGD
768
@deffnx {} BFD_RELOC_ALPHA_TLSLDM
769
@deffnx {} BFD_RELOC_ALPHA_DTPMOD64
770
@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16
771
@deffnx {} BFD_RELOC_ALPHA_DTPREL64
772
@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16
773
@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16
774
@deffnx {} BFD_RELOC_ALPHA_DTPREL16
775
@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16
776
@deffnx {} BFD_RELOC_ALPHA_TPREL64
777
@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16
778
@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16
779
@deffnx {} BFD_RELOC_ALPHA_TPREL16
780
Alpha thread-local storage relocations.
781
@end deffn
782
@deffn {} BFD_RELOC_MIPS_JMP
783
Bits 27..2 of the relocation address shifted right 2 bits;
784
simple reloc otherwise.
785
@end deffn
786
@deffn {} BFD_RELOC_MIPS16_JMP
787
The MIPS16 jump instruction.
788
@end deffn
789
@deffn {} BFD_RELOC_MIPS16_GPREL
790
MIPS16 GP relative reloc.
791
@end deffn
792
@deffn {} BFD_RELOC_HI16
793
High 16 bits of 32-bit value; simple reloc.
794
@end deffn
795
@deffn {} BFD_RELOC_HI16_S
796
High 16 bits of 32-bit value but the low 16 bits will be sign
797
extended and added to form the final result.  If the low 16
798
bits form a negative number, we need to add one to the high value
799
to compensate for the borrow when the low bits are added.
800
@end deffn
801
@deffn {} BFD_RELOC_LO16
802
Low 16 bits.
803
@end deffn
804
@deffn {} BFD_RELOC_HI16_PCREL
805
High 16 bits of 32-bit pc-relative value
806
@end deffn
807
@deffn {} BFD_RELOC_HI16_S_PCREL
808
High 16 bits of 32-bit pc-relative value, adjusted
809
@end deffn
810
@deffn {} BFD_RELOC_LO16_PCREL
811
Low 16 bits of pc-relative value
812
@end deffn
813
@deffn {} BFD_RELOC_MIPS16_HI16
814
MIPS16 high 16 bits of 32-bit value.
815
@end deffn
816
@deffn {} BFD_RELOC_MIPS16_HI16_S
817
MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
818
extended and added to form the final result.  If the low 16
819
bits form a negative number, we need to add one to the high value
820
to compensate for the borrow when the low bits are added.
821
@end deffn
822
@deffn {} BFD_RELOC_MIPS16_LO16
823
MIPS16 low 16 bits.
824
@end deffn
825
@deffn {} BFD_RELOC_MIPS_LITERAL
826
Relocation against a MIPS literal section.
827
@end deffn
828
@deffn {} BFD_RELOC_MIPS_GOT16
829
@deffnx {} BFD_RELOC_MIPS_CALL16
830
@deffnx {} BFD_RELOC_MIPS_GOT_HI16
831
@deffnx {} BFD_RELOC_MIPS_GOT_LO16
832
@deffnx {} BFD_RELOC_MIPS_CALL_HI16
833
@deffnx {} BFD_RELOC_MIPS_CALL_LO16
834
@deffnx {} BFD_RELOC_MIPS_SUB
835
@deffnx {} BFD_RELOC_MIPS_GOT_PAGE
836
@deffnx {} BFD_RELOC_MIPS_GOT_OFST
837
@deffnx {} BFD_RELOC_MIPS_GOT_DISP
838
@deffnx {} BFD_RELOC_MIPS_SHIFT5
839
@deffnx {} BFD_RELOC_MIPS_SHIFT6
840
@deffnx {} BFD_RELOC_MIPS_INSERT_A
841
@deffnx {} BFD_RELOC_MIPS_INSERT_B
842
@deffnx {} BFD_RELOC_MIPS_DELETE
843
@deffnx {} BFD_RELOC_MIPS_HIGHEST
844
@deffnx {} BFD_RELOC_MIPS_HIGHER
845
@deffnx {} BFD_RELOC_MIPS_SCN_DISP
846
@deffnx {} BFD_RELOC_MIPS_REL16
847
@deffnx {} BFD_RELOC_MIPS_RELGOT
848
@deffnx {} BFD_RELOC_MIPS_JALR
849
@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32
850
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32
851
@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64
852
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64
853
@deffnx {} BFD_RELOC_MIPS_TLS_GD
854
@deffnx {} BFD_RELOC_MIPS_TLS_LDM
855
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16
856
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16
857
@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL
858
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32
859
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64
860
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16
861
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16
862
MIPS ELF relocations.
863
@end deffn
864
@deffn {} BFD_RELOC_MIPS_COPY
865
@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT
866
MIPS ELF relocations (VxWorks extensions).
867
@end deffn
868
@deffn {} BFD_RELOC_FRV_LABEL16
869
@deffnx {} BFD_RELOC_FRV_LABEL24
870
@deffnx {} BFD_RELOC_FRV_LO16
871
@deffnx {} BFD_RELOC_FRV_HI16
872
@deffnx {} BFD_RELOC_FRV_GPREL12
873
@deffnx {} BFD_RELOC_FRV_GPRELU12
874
@deffnx {} BFD_RELOC_FRV_GPREL32
875
@deffnx {} BFD_RELOC_FRV_GPRELHI
876
@deffnx {} BFD_RELOC_FRV_GPRELLO
877
@deffnx {} BFD_RELOC_FRV_GOT12
878
@deffnx {} BFD_RELOC_FRV_GOTHI
879
@deffnx {} BFD_RELOC_FRV_GOTLO
880
@deffnx {} BFD_RELOC_FRV_FUNCDESC
881
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12
882
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI
883
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO
884
@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE
885
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12
886
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
887
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
888
@deffnx {} BFD_RELOC_FRV_GOTOFF12
889
@deffnx {} BFD_RELOC_FRV_GOTOFFHI
890
@deffnx {} BFD_RELOC_FRV_GOTOFFLO
891
@deffnx {} BFD_RELOC_FRV_GETTLSOFF
892
@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE
893
@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12
894
@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI
895
@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO
896
@deffnx {} BFD_RELOC_FRV_TLSMOFF12
897
@deffnx {} BFD_RELOC_FRV_TLSMOFFHI
898
@deffnx {} BFD_RELOC_FRV_TLSMOFFLO
899
@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12
900
@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI
901
@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO
902
@deffnx {} BFD_RELOC_FRV_TLSOFF
903
@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX
904
@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX
905
@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX
906
@deffnx {} BFD_RELOC_FRV_TLSMOFF
907
Fujitsu Frv Relocations.
908
@end deffn
909
@deffn {} BFD_RELOC_MN10300_GOTOFF24
910
This is a 24bit GOT-relative reloc for the mn10300.
911
@end deffn
912
@deffn {} BFD_RELOC_MN10300_GOT32
913
This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
914
in the instruction.
915
@end deffn
916
@deffn {} BFD_RELOC_MN10300_GOT24
917
This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
918
in the instruction.
919
@end deffn
920
@deffn {} BFD_RELOC_MN10300_GOT16
921
This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
922
in the instruction.
923
@end deffn
924
@deffn {} BFD_RELOC_MN10300_COPY
925
Copy symbol at runtime.
926
@end deffn
927
@deffn {} BFD_RELOC_MN10300_GLOB_DAT
928
Create GOT entry.
929
@end deffn
930
@deffn {} BFD_RELOC_MN10300_JMP_SLOT
931
Create PLT entry.
932
@end deffn
933
@deffn {} BFD_RELOC_MN10300_RELATIVE
934
Adjust by program base.
935
@end deffn
936
@deffn {} BFD_RELOC_MN10300_SYM_DIFF
937
Together with another reloc targeted at the same location,
938
allows for a value that is the difference of two symbols
939
in the same section.
940
@end deffn
941
@deffn {} BFD_RELOC_MN10300_ALIGN
942
The addend of this reloc is an alignment power that must
943
be honoured at the offset's location, regardless of linker
944
relaxation.
945
@end deffn
946
@deffn {} BFD_RELOC_386_GOT32
947
@deffnx {} BFD_RELOC_386_PLT32
948
@deffnx {} BFD_RELOC_386_COPY
949
@deffnx {} BFD_RELOC_386_GLOB_DAT
950
@deffnx {} BFD_RELOC_386_JUMP_SLOT
951
@deffnx {} BFD_RELOC_386_RELATIVE
952
@deffnx {} BFD_RELOC_386_GOTOFF
953
@deffnx {} BFD_RELOC_386_GOTPC
954
@deffnx {} BFD_RELOC_386_TLS_TPOFF
955
@deffnx {} BFD_RELOC_386_TLS_IE
956
@deffnx {} BFD_RELOC_386_TLS_GOTIE
957
@deffnx {} BFD_RELOC_386_TLS_LE
958
@deffnx {} BFD_RELOC_386_TLS_GD
959
@deffnx {} BFD_RELOC_386_TLS_LDM
960
@deffnx {} BFD_RELOC_386_TLS_LDO_32
961
@deffnx {} BFD_RELOC_386_TLS_IE_32
962
@deffnx {} BFD_RELOC_386_TLS_LE_32
963
@deffnx {} BFD_RELOC_386_TLS_DTPMOD32
964
@deffnx {} BFD_RELOC_386_TLS_DTPOFF32
965
@deffnx {} BFD_RELOC_386_TLS_TPOFF32
966
@deffnx {} BFD_RELOC_386_TLS_GOTDESC
967
@deffnx {} BFD_RELOC_386_TLS_DESC_CALL
968
@deffnx {} BFD_RELOC_386_TLS_DESC
969
i386/elf relocations
970
@end deffn
971
@deffn {} BFD_RELOC_X86_64_GOT32
972
@deffnx {} BFD_RELOC_X86_64_PLT32
973
@deffnx {} BFD_RELOC_X86_64_COPY
974
@deffnx {} BFD_RELOC_X86_64_GLOB_DAT
975
@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT
976
@deffnx {} BFD_RELOC_X86_64_RELATIVE
977
@deffnx {} BFD_RELOC_X86_64_GOTPCREL
978
@deffnx {} BFD_RELOC_X86_64_32S
979
@deffnx {} BFD_RELOC_X86_64_DTPMOD64
980
@deffnx {} BFD_RELOC_X86_64_DTPOFF64
981
@deffnx {} BFD_RELOC_X86_64_TPOFF64
982
@deffnx {} BFD_RELOC_X86_64_TLSGD
983
@deffnx {} BFD_RELOC_X86_64_TLSLD
984
@deffnx {} BFD_RELOC_X86_64_DTPOFF32
985
@deffnx {} BFD_RELOC_X86_64_GOTTPOFF
986
@deffnx {} BFD_RELOC_X86_64_TPOFF32
987
@deffnx {} BFD_RELOC_X86_64_GOTOFF64
988
@deffnx {} BFD_RELOC_X86_64_GOTPC32
989
@deffnx {} BFD_RELOC_X86_64_GOT64
990
@deffnx {} BFD_RELOC_X86_64_GOTPCREL64
991
@deffnx {} BFD_RELOC_X86_64_GOTPC64
992
@deffnx {} BFD_RELOC_X86_64_GOTPLT64
993
@deffnx {} BFD_RELOC_X86_64_PLTOFF64
994
@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC
995
@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL
996
@deffnx {} BFD_RELOC_X86_64_TLSDESC
997
x86-64/elf relocations
998
@end deffn
999
@deffn {} BFD_RELOC_NS32K_IMM_8
1000
@deffnx {} BFD_RELOC_NS32K_IMM_16
1001
@deffnx {} BFD_RELOC_NS32K_IMM_32
1002
@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL
1003
@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL
1004
@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL
1005
@deffnx {} BFD_RELOC_NS32K_DISP_8
1006
@deffnx {} BFD_RELOC_NS32K_DISP_16
1007
@deffnx {} BFD_RELOC_NS32K_DISP_32
1008
@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL
1009
@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL
1010
@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL
1011
ns32k relocations
1012
@end deffn
1013
@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL
1014
@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL
1015
PDP11 relocations
1016
@end deffn
1017
@deffn {} BFD_RELOC_PJ_CODE_HI16
1018
@deffnx {} BFD_RELOC_PJ_CODE_LO16
1019
@deffnx {} BFD_RELOC_PJ_CODE_DIR16
1020
@deffnx {} BFD_RELOC_PJ_CODE_DIR32
1021
@deffnx {} BFD_RELOC_PJ_CODE_REL16
1022
@deffnx {} BFD_RELOC_PJ_CODE_REL32
1023
Picojava relocs.  Not all of these appear in object files.
1024
@end deffn
1025
@deffn {} BFD_RELOC_PPC_B26
1026
@deffnx {} BFD_RELOC_PPC_BA26
1027
@deffnx {} BFD_RELOC_PPC_TOC16
1028
@deffnx {} BFD_RELOC_PPC_B16
1029
@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN
1030
@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN
1031
@deffnx {} BFD_RELOC_PPC_BA16
1032
@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN
1033
@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN
1034
@deffnx {} BFD_RELOC_PPC_COPY
1035
@deffnx {} BFD_RELOC_PPC_GLOB_DAT
1036
@deffnx {} BFD_RELOC_PPC_JMP_SLOT
1037
@deffnx {} BFD_RELOC_PPC_RELATIVE
1038
@deffnx {} BFD_RELOC_PPC_LOCAL24PC
1039
@deffnx {} BFD_RELOC_PPC_EMB_NADDR32
1040
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16
1041
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO
1042
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI
1043
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA
1044
@deffnx {} BFD_RELOC_PPC_EMB_SDAI16
1045
@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16
1046
@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL
1047
@deffnx {} BFD_RELOC_PPC_EMB_SDA21
1048
@deffnx {} BFD_RELOC_PPC_EMB_MRKREF
1049
@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16
1050
@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO
1051
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI
1052
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA
1053
@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD
1054
@deffnx {} BFD_RELOC_PPC_EMB_RELSDA
1055
@deffnx {} BFD_RELOC_PPC64_HIGHER
1056
@deffnx {} BFD_RELOC_PPC64_HIGHER_S
1057
@deffnx {} BFD_RELOC_PPC64_HIGHEST
1058
@deffnx {} BFD_RELOC_PPC64_HIGHEST_S
1059
@deffnx {} BFD_RELOC_PPC64_TOC16_LO
1060
@deffnx {} BFD_RELOC_PPC64_TOC16_HI
1061
@deffnx {} BFD_RELOC_PPC64_TOC16_HA
1062
@deffnx {} BFD_RELOC_PPC64_TOC
1063
@deffnx {} BFD_RELOC_PPC64_PLTGOT16
1064
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO
1065
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI
1066
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA
1067
@deffnx {} BFD_RELOC_PPC64_ADDR16_DS
1068
@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS
1069
@deffnx {} BFD_RELOC_PPC64_GOT16_DS
1070
@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS
1071
@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS
1072
@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS
1073
@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS
1074
@deffnx {} BFD_RELOC_PPC64_TOC16_DS
1075
@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS
1076
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS
1077
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS
1078
Power(rs6000) and PowerPC relocations.
1079
@end deffn
1080
@deffn {} BFD_RELOC_PPC_TLS
1081
@deffnx {} BFD_RELOC_PPC_DTPMOD
1082
@deffnx {} BFD_RELOC_PPC_TPREL16
1083
@deffnx {} BFD_RELOC_PPC_TPREL16_LO
1084
@deffnx {} BFD_RELOC_PPC_TPREL16_HI
1085
@deffnx {} BFD_RELOC_PPC_TPREL16_HA
1086
@deffnx {} BFD_RELOC_PPC_TPREL
1087
@deffnx {} BFD_RELOC_PPC_DTPREL16
1088
@deffnx {} BFD_RELOC_PPC_DTPREL16_LO
1089
@deffnx {} BFD_RELOC_PPC_DTPREL16_HI
1090
@deffnx {} BFD_RELOC_PPC_DTPREL16_HA
1091
@deffnx {} BFD_RELOC_PPC_DTPREL
1092
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16
1093
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO
1094
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI
1095
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA
1096
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16
1097
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO
1098
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI
1099
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA
1100
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16
1101
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO
1102
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI
1103
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA
1104
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16
1105
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO
1106
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI
1107
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA
1108
@deffnx {} BFD_RELOC_PPC64_TPREL16_DS
1109
@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS
1110
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER
1111
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA
1112
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST
1113
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA
1114
@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS
1115
@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS
1116
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER
1117
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA
1118
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST
1119
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA
1120
PowerPC and PowerPC64 thread-local storage relocations.
1121
@end deffn
1122
@deffn {} BFD_RELOC_I370_D12
1123
IBM 370/390 relocations
1124
@end deffn
1125
@deffn {} BFD_RELOC_CTOR
1126
The type of reloc used to build a constructor table - at the moment
1127
probably a 32 bit wide absolute relocation, but the target can choose.
1128
It generally does map to one of the other relocation types.
1129
@end deffn
1130
@deffn {} BFD_RELOC_ARM_PCREL_BRANCH
1131
ARM 26 bit pc-relative branch.  The lowest two bits must be zero and are
1132
not stored in the instruction.
1133
@end deffn
1134
@deffn {} BFD_RELOC_ARM_PCREL_BLX
1135
ARM 26 bit pc-relative branch.  The lowest bit must be zero and is
1136
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
1137
field in the instruction.
1138
@end deffn
1139
@deffn {} BFD_RELOC_THUMB_PCREL_BLX
1140
Thumb 22 bit pc-relative branch.  The lowest bit must be zero and is
1141
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
1142
field in the instruction.
1143
@end deffn
1144
@deffn {} BFD_RELOC_ARM_PCREL_CALL
1145
ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
1146
@end deffn
1147
@deffn {} BFD_RELOC_ARM_PCREL_JUMP
1148
ARM 26-bit pc-relative branch for B or conditional BL instruction.
1149
@end deffn
1150
@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7
1151
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9
1152
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12
1153
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20
1154
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23
1155
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25
1156
Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
1157
The lowest bit must be zero and is not stored in the instruction.
1158
Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
1159
"nn" one smaller in all cases.  Note further that BRANCH23
1160
corresponds to R_ARM_THM_CALL.
1161
@end deffn
1162
@deffn {} BFD_RELOC_ARM_OFFSET_IMM
1163
12-bit immediate offset, used in ARM-format ldr and str instructions.
1164
@end deffn
1165
@deffn {} BFD_RELOC_ARM_THUMB_OFFSET
1166
5-bit immediate offset, used in Thumb-format ldr and str instructions.
1167
@end deffn
1168
@deffn {} BFD_RELOC_ARM_TARGET1
1169
Pc-relative or absolute relocation depending on target.  Used for
1170
entries in .init_array sections.
1171
@end deffn
1172
@deffn {} BFD_RELOC_ARM_ROSEGREL32
1173
Read-only segment base relative address.
1174
@end deffn
1175
@deffn {} BFD_RELOC_ARM_SBREL32
1176
Data segment base relative address.
1177
@end deffn
1178
@deffn {} BFD_RELOC_ARM_TARGET2
1179
This reloc is used for references to RTTI data from exception handling
1180
tables.  The actual definition depends on the target.  It may be a
1181
pc-relative or some form of GOT-indirect relocation.
1182
@end deffn
1183
@deffn {} BFD_RELOC_ARM_PREL31
1184
31-bit PC relative address.
1185
@end deffn
1186
@deffn {} BFD_RELOC_ARM_MOVW
1187
@deffnx {} BFD_RELOC_ARM_MOVT
1188
@deffnx {} BFD_RELOC_ARM_MOVW_PCREL
1189
@deffnx {} BFD_RELOC_ARM_MOVT_PCREL
1190
@deffnx {} BFD_RELOC_ARM_THUMB_MOVW
1191
@deffnx {} BFD_RELOC_ARM_THUMB_MOVT
1192
@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL
1193
@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL
1194
Low and High halfword relocations for MOVW and MOVT instructions.
1195
@end deffn
1196
@deffn {} BFD_RELOC_ARM_JUMP_SLOT
1197
@deffnx {} BFD_RELOC_ARM_GLOB_DAT
1198
@deffnx {} BFD_RELOC_ARM_GOT32
1199
@deffnx {} BFD_RELOC_ARM_PLT32
1200
@deffnx {} BFD_RELOC_ARM_RELATIVE
1201
@deffnx {} BFD_RELOC_ARM_GOTOFF
1202
@deffnx {} BFD_RELOC_ARM_GOTPC
1203
Relocations for setting up GOTs and PLTs for shared libraries.
1204
@end deffn
1205
@deffn {} BFD_RELOC_ARM_TLS_GD32
1206
@deffnx {} BFD_RELOC_ARM_TLS_LDO32
1207
@deffnx {} BFD_RELOC_ARM_TLS_LDM32
1208
@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32
1209
@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32
1210
@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32
1211
@deffnx {} BFD_RELOC_ARM_TLS_IE32
1212
@deffnx {} BFD_RELOC_ARM_TLS_LE32
1213
ARM thread-local storage relocations.
1214
@end deffn
1215
@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC
1216
@deffnx {} BFD_RELOC_ARM_ALU_PC_G0
1217
@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC
1218
@deffnx {} BFD_RELOC_ARM_ALU_PC_G1
1219
@deffnx {} BFD_RELOC_ARM_ALU_PC_G2
1220
@deffnx {} BFD_RELOC_ARM_LDR_PC_G0
1221
@deffnx {} BFD_RELOC_ARM_LDR_PC_G1
1222
@deffnx {} BFD_RELOC_ARM_LDR_PC_G2
1223
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0
1224
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1
1225
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2
1226
@deffnx {} BFD_RELOC_ARM_LDC_PC_G0
1227
@deffnx {} BFD_RELOC_ARM_LDC_PC_G1
1228
@deffnx {} BFD_RELOC_ARM_LDC_PC_G2
1229
@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC
1230
@deffnx {} BFD_RELOC_ARM_ALU_SB_G0
1231
@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC
1232
@deffnx {} BFD_RELOC_ARM_ALU_SB_G1
1233
@deffnx {} BFD_RELOC_ARM_ALU_SB_G2
1234
@deffnx {} BFD_RELOC_ARM_LDR_SB_G0
1235
@deffnx {} BFD_RELOC_ARM_LDR_SB_G1
1236
@deffnx {} BFD_RELOC_ARM_LDR_SB_G2
1237
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0
1238
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1
1239
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2
1240
@deffnx {} BFD_RELOC_ARM_LDC_SB_G0
1241
@deffnx {} BFD_RELOC_ARM_LDC_SB_G1
1242
@deffnx {} BFD_RELOC_ARM_LDC_SB_G2
1243
ARM group relocations.
1244
@end deffn
1245
@deffn {} BFD_RELOC_ARM_V4BX
1246
Annotation of BX instructions.
1247
@end deffn
1248
@deffn {} BFD_RELOC_ARM_IMMEDIATE
1249
@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE
1250
@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE
1251
@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM
1252
@deffnx {} BFD_RELOC_ARM_T32_IMM12
1253
@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12
1254
@deffnx {} BFD_RELOC_ARM_SHIFT_IMM
1255
@deffnx {} BFD_RELOC_ARM_SMC
1256
@deffnx {} BFD_RELOC_ARM_SWI
1257
@deffnx {} BFD_RELOC_ARM_MULTI
1258
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM
1259
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2
1260
@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM
1261
@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
1262
@deffnx {} BFD_RELOC_ARM_ADR_IMM
1263
@deffnx {} BFD_RELOC_ARM_LDR_IMM
1264
@deffnx {} BFD_RELOC_ARM_LITERAL
1265
@deffnx {} BFD_RELOC_ARM_IN_POOL
1266
@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8
1267
@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8
1268
@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM
1269
@deffnx {} BFD_RELOC_ARM_HWLITERAL
1270
@deffnx {} BFD_RELOC_ARM_THUMB_ADD
1271
@deffnx {} BFD_RELOC_ARM_THUMB_IMM
1272
@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT
1273
These relocs are only used within the ARM assembler.  They are not
1274
(at present) written to any object files.
1275
@end deffn
1276
@deffn {} BFD_RELOC_SH_PCDISP8BY2
1277
@deffnx {} BFD_RELOC_SH_PCDISP12BY2
1278
@deffnx {} BFD_RELOC_SH_IMM3
1279
@deffnx {} BFD_RELOC_SH_IMM3U
1280
@deffnx {} BFD_RELOC_SH_DISP12
1281
@deffnx {} BFD_RELOC_SH_DISP12BY2
1282
@deffnx {} BFD_RELOC_SH_DISP12BY4
1283
@deffnx {} BFD_RELOC_SH_DISP12BY8
1284
@deffnx {} BFD_RELOC_SH_DISP20
1285
@deffnx {} BFD_RELOC_SH_DISP20BY8
1286
@deffnx {} BFD_RELOC_SH_IMM4
1287
@deffnx {} BFD_RELOC_SH_IMM4BY2
1288
@deffnx {} BFD_RELOC_SH_IMM4BY4
1289
@deffnx {} BFD_RELOC_SH_IMM8
1290
@deffnx {} BFD_RELOC_SH_IMM8BY2
1291
@deffnx {} BFD_RELOC_SH_IMM8BY4
1292
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2
1293
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4
1294
@deffnx {} BFD_RELOC_SH_SWITCH16
1295
@deffnx {} BFD_RELOC_SH_SWITCH32
1296
@deffnx {} BFD_RELOC_SH_USES
1297
@deffnx {} BFD_RELOC_SH_COUNT
1298
@deffnx {} BFD_RELOC_SH_ALIGN
1299
@deffnx {} BFD_RELOC_SH_CODE
1300
@deffnx {} BFD_RELOC_SH_DATA
1301
@deffnx {} BFD_RELOC_SH_LABEL
1302
@deffnx {} BFD_RELOC_SH_LOOP_START
1303
@deffnx {} BFD_RELOC_SH_LOOP_END
1304
@deffnx {} BFD_RELOC_SH_COPY
1305
@deffnx {} BFD_RELOC_SH_GLOB_DAT
1306
@deffnx {} BFD_RELOC_SH_JMP_SLOT
1307
@deffnx {} BFD_RELOC_SH_RELATIVE
1308
@deffnx {} BFD_RELOC_SH_GOTPC
1309
@deffnx {} BFD_RELOC_SH_GOT_LOW16
1310
@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16
1311
@deffnx {} BFD_RELOC_SH_GOT_MEDHI16
1312
@deffnx {} BFD_RELOC_SH_GOT_HI16
1313
@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16
1314
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16
1315
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16
1316
@deffnx {} BFD_RELOC_SH_GOTPLT_HI16
1317
@deffnx {} BFD_RELOC_SH_PLT_LOW16
1318
@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16
1319
@deffnx {} BFD_RELOC_SH_PLT_MEDHI16
1320
@deffnx {} BFD_RELOC_SH_PLT_HI16
1321
@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16
1322
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16
1323
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16
1324
@deffnx {} BFD_RELOC_SH_GOTOFF_HI16
1325
@deffnx {} BFD_RELOC_SH_GOTPC_LOW16
1326
@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16
1327
@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16
1328
@deffnx {} BFD_RELOC_SH_GOTPC_HI16
1329
@deffnx {} BFD_RELOC_SH_COPY64
1330
@deffnx {} BFD_RELOC_SH_GLOB_DAT64
1331
@deffnx {} BFD_RELOC_SH_JMP_SLOT64
1332
@deffnx {} BFD_RELOC_SH_RELATIVE64
1333
@deffnx {} BFD_RELOC_SH_GOT10BY4
1334
@deffnx {} BFD_RELOC_SH_GOT10BY8
1335
@deffnx {} BFD_RELOC_SH_GOTPLT10BY4
1336
@deffnx {} BFD_RELOC_SH_GOTPLT10BY8
1337
@deffnx {} BFD_RELOC_SH_GOTPLT32
1338
@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE
1339
@deffnx {} BFD_RELOC_SH_IMMU5
1340
@deffnx {} BFD_RELOC_SH_IMMS6
1341
@deffnx {} BFD_RELOC_SH_IMMS6BY32
1342
@deffnx {} BFD_RELOC_SH_IMMU6
1343
@deffnx {} BFD_RELOC_SH_IMMS10
1344
@deffnx {} BFD_RELOC_SH_IMMS10BY2
1345
@deffnx {} BFD_RELOC_SH_IMMS10BY4
1346
@deffnx {} BFD_RELOC_SH_IMMS10BY8
1347
@deffnx {} BFD_RELOC_SH_IMMS16
1348
@deffnx {} BFD_RELOC_SH_IMMU16
1349
@deffnx {} BFD_RELOC_SH_IMM_LOW16
1350
@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL
1351
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16
1352
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL
1353
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16
1354
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL
1355
@deffnx {} BFD_RELOC_SH_IMM_HI16
1356
@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL
1357
@deffnx {} BFD_RELOC_SH_PT_16
1358
@deffnx {} BFD_RELOC_SH_TLS_GD_32
1359
@deffnx {} BFD_RELOC_SH_TLS_LD_32
1360
@deffnx {} BFD_RELOC_SH_TLS_LDO_32
1361
@deffnx {} BFD_RELOC_SH_TLS_IE_32
1362
@deffnx {} BFD_RELOC_SH_TLS_LE_32
1363
@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32
1364
@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32
1365
@deffnx {} BFD_RELOC_SH_TLS_TPOFF32
1366
Renesas / SuperH SH relocs.  Not all of these appear in object files.
1367
@end deffn
1368
@deffn {} BFD_RELOC_ARC_B22_PCREL
1369
ARC Cores relocs.
1370
ARC 22 bit pc-relative branch.  The lowest two bits must be zero and are
1371
not stored in the instruction.  The high 20 bits are installed in bits 26
1372
through 7 of the instruction.
1373
@end deffn
1374
@deffn {} BFD_RELOC_ARC_B26
1375
ARC 26 bit absolute branch.  The lowest two bits must be zero and are not
1376
stored in the instruction.  The high 24 bits are installed in bits 23
1377
through 0.
1378
@end deffn
1379
@deffn {} BFD_RELOC_BFIN_16_IMM
1380
ADI Blackfin 16 bit immediate absolute reloc.
1381
@end deffn
1382
@deffn {} BFD_RELOC_BFIN_16_HIGH
1383
ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
1384
@end deffn
1385
@deffn {} BFD_RELOC_BFIN_4_PCREL
1386
ADI Blackfin 'a' part of LSETUP.
1387
@end deffn
1388
@deffn {} BFD_RELOC_BFIN_5_PCREL
1389
ADI Blackfin.
1390
@end deffn
1391
@deffn {} BFD_RELOC_BFIN_16_LOW
1392
ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
1393
@end deffn
1394
@deffn {} BFD_RELOC_BFIN_10_PCREL
1395
ADI Blackfin.
1396
@end deffn
1397
@deffn {} BFD_RELOC_BFIN_11_PCREL
1398
ADI Blackfin 'b' part of LSETUP.
1399
@end deffn
1400
@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP
1401
ADI Blackfin.
1402
@end deffn
1403
@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S
1404
ADI Blackfin Short jump, pcrel.
1405
@end deffn
1406
@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X
1407
ADI Blackfin Call.x not implemented.
1408
@end deffn
1409
@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L
1410
ADI Blackfin Long Jump pcrel.
1411
@end deffn
1412
@deffn {} BFD_RELOC_BFIN_GOT17M4
1413
@deffnx {} BFD_RELOC_BFIN_GOTHI
1414
@deffnx {} BFD_RELOC_BFIN_GOTLO
1415
@deffnx {} BFD_RELOC_BFIN_FUNCDESC
1416
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4
1417
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI
1418
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO
1419
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE
1420
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
1421
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
1422
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
1423
@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4
1424
@deffnx {} BFD_RELOC_BFIN_GOTOFFHI
1425
@deffnx {} BFD_RELOC_BFIN_GOTOFFLO
1426
ADI Blackfin FD-PIC relocations.
1427
@end deffn
1428
@deffn {} BFD_RELOC_BFIN_GOT
1429
ADI Blackfin GOT relocation.
1430
@end deffn
1431
@deffn {} BFD_RELOC_BFIN_PLTPC
1432
ADI Blackfin PLTPC relocation.
1433
@end deffn
1434
@deffn {} BFD_ARELOC_BFIN_PUSH
1435
ADI Blackfin arithmetic relocation.
1436
@end deffn
1437
@deffn {} BFD_ARELOC_BFIN_CONST
1438
ADI Blackfin arithmetic relocation.
1439
@end deffn
1440
@deffn {} BFD_ARELOC_BFIN_ADD
1441
ADI Blackfin arithmetic relocation.
1442
@end deffn
1443
@deffn {} BFD_ARELOC_BFIN_SUB
1444
ADI Blackfin arithmetic relocation.
1445
@end deffn
1446
@deffn {} BFD_ARELOC_BFIN_MULT
1447
ADI Blackfin arithmetic relocation.
1448
@end deffn
1449
@deffn {} BFD_ARELOC_BFIN_DIV
1450
ADI Blackfin arithmetic relocation.
1451
@end deffn
1452
@deffn {} BFD_ARELOC_BFIN_MOD
1453
ADI Blackfin arithmetic relocation.
1454
@end deffn
1455
@deffn {} BFD_ARELOC_BFIN_LSHIFT
1456
ADI Blackfin arithmetic relocation.
1457
@end deffn
1458
@deffn {} BFD_ARELOC_BFIN_RSHIFT
1459
ADI Blackfin arithmetic relocation.
1460
@end deffn
1461
@deffn {} BFD_ARELOC_BFIN_AND
1462
ADI Blackfin arithmetic relocation.
1463
@end deffn
1464
@deffn {} BFD_ARELOC_BFIN_OR
1465
ADI Blackfin arithmetic relocation.
1466
@end deffn
1467
@deffn {} BFD_ARELOC_BFIN_XOR
1468
ADI Blackfin arithmetic relocation.
1469
@end deffn
1470
@deffn {} BFD_ARELOC_BFIN_LAND
1471
ADI Blackfin arithmetic relocation.
1472
@end deffn
1473
@deffn {} BFD_ARELOC_BFIN_LOR
1474
ADI Blackfin arithmetic relocation.
1475
@end deffn
1476
@deffn {} BFD_ARELOC_BFIN_LEN
1477
ADI Blackfin arithmetic relocation.
1478
@end deffn
1479
@deffn {} BFD_ARELOC_BFIN_NEG
1480
ADI Blackfin arithmetic relocation.
1481
@end deffn
1482
@deffn {} BFD_ARELOC_BFIN_COMP
1483
ADI Blackfin arithmetic relocation.
1484
@end deffn
1485
@deffn {} BFD_ARELOC_BFIN_PAGE
1486
ADI Blackfin arithmetic relocation.
1487
@end deffn
1488
@deffn {} BFD_ARELOC_BFIN_HWPAGE
1489
ADI Blackfin arithmetic relocation.
1490
@end deffn
1491
@deffn {} BFD_ARELOC_BFIN_ADDR
1492
ADI Blackfin arithmetic relocation.
1493
@end deffn
1494
@deffn {} BFD_RELOC_D10V_10_PCREL_R
1495
Mitsubishi D10V relocs.
1496
This is a 10-bit reloc with the right 2 bits
1497
assumed to be 0.
1498
@end deffn
1499
@deffn {} BFD_RELOC_D10V_10_PCREL_L
1500
Mitsubishi D10V relocs.
1501
This is a 10-bit reloc with the right 2 bits
1502
assumed to be 0.  This is the same as the previous reloc
1503
except it is in the left container, i.e.,
1504
shifted left 15 bits.
1505
@end deffn
1506
@deffn {} BFD_RELOC_D10V_18
1507
This is an 18-bit reloc with the right 2 bits
1508
assumed to be 0.
1509
@end deffn
1510
@deffn {} BFD_RELOC_D10V_18_PCREL
1511
This is an 18-bit reloc with the right 2 bits
1512
assumed to be 0.
1513
@end deffn
1514
@deffn {} BFD_RELOC_D30V_6
1515
Mitsubishi D30V relocs.
1516
This is a 6-bit absolute reloc.
1517
@end deffn
1518
@deffn {} BFD_RELOC_D30V_9_PCREL
1519
This is a 6-bit pc-relative reloc with
1520
the right 3 bits assumed to be 0.
1521
@end deffn
1522
@deffn {} BFD_RELOC_D30V_9_PCREL_R
1523
This is a 6-bit pc-relative reloc with
1524
the right 3 bits assumed to be 0. Same
1525
as the previous reloc but on the right side
1526
of the container.
1527
@end deffn
1528
@deffn {} BFD_RELOC_D30V_15
1529
This is a 12-bit absolute reloc with the
1530
right 3 bitsassumed to be 0.
1531
@end deffn
1532
@deffn {} BFD_RELOC_D30V_15_PCREL
1533
This is a 12-bit pc-relative reloc with
1534
the right 3 bits assumed to be 0.
1535
@end deffn
1536
@deffn {} BFD_RELOC_D30V_15_PCREL_R
1537
This is a 12-bit pc-relative reloc with
1538
the right 3 bits assumed to be 0. Same
1539
as the previous reloc but on the right side
1540
of the container.
1541
@end deffn
1542
@deffn {} BFD_RELOC_D30V_21
1543
This is an 18-bit absolute reloc with
1544
the right 3 bits assumed to be 0.
1545
@end deffn
1546
@deffn {} BFD_RELOC_D30V_21_PCREL
1547
This is an 18-bit pc-relative reloc with
1548
the right 3 bits assumed to be 0.
1549
@end deffn
1550
@deffn {} BFD_RELOC_D30V_21_PCREL_R
1551
This is an 18-bit pc-relative reloc with
1552
the right 3 bits assumed to be 0. Same
1553
as the previous reloc but on the right side
1554
of the container.
1555
@end deffn
1556
@deffn {} BFD_RELOC_D30V_32
1557
This is a 32-bit absolute reloc.
1558
@end deffn
1559
@deffn {} BFD_RELOC_D30V_32_PCREL
1560
This is a 32-bit pc-relative reloc.
1561
@end deffn
1562
@deffn {} BFD_RELOC_DLX_HI16_S
1563
DLX relocs
1564
@end deffn
1565
@deffn {} BFD_RELOC_DLX_LO16
1566
DLX relocs
1567
@end deffn
1568
@deffn {} BFD_RELOC_DLX_JMP26
1569
DLX relocs
1570
@end deffn
1571
@deffn {} BFD_RELOC_M32C_HI8
1572
@deffnx {} BFD_RELOC_M32C_RL_JUMP
1573
@deffnx {} BFD_RELOC_M32C_RL_1ADDR
1574
@deffnx {} BFD_RELOC_M32C_RL_2ADDR
1575
Renesas M16C/M32C Relocations.
1576
@end deffn
1577
@deffn {} BFD_RELOC_M32R_24
1578
Renesas M32R (formerly Mitsubishi M32R) relocs.
1579
This is a 24 bit absolute address.
1580
@end deffn
1581
@deffn {} BFD_RELOC_M32R_10_PCREL
1582
This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
1583
@end deffn
1584
@deffn {} BFD_RELOC_M32R_18_PCREL
1585
This is an 18-bit reloc with the right 2 bits assumed to be 0.
1586
@end deffn
1587
@deffn {} BFD_RELOC_M32R_26_PCREL
1588
This is a 26-bit reloc with the right 2 bits assumed to be 0.
1589
@end deffn
1590
@deffn {} BFD_RELOC_M32R_HI16_ULO
1591
This is a 16-bit reloc containing the high 16 bits of an address
1592
used when the lower 16 bits are treated as unsigned.
1593
@end deffn
1594
@deffn {} BFD_RELOC_M32R_HI16_SLO
1595
This is a 16-bit reloc containing the high 16 bits of an address
1596
used when the lower 16 bits are treated as signed.
1597
@end deffn
1598
@deffn {} BFD_RELOC_M32R_LO16
1599
This is a 16-bit reloc containing the lower 16 bits of an address.
1600
@end deffn
1601
@deffn {} BFD_RELOC_M32R_SDA16
1602
This is a 16-bit reloc containing the small data area offset for use in
1603
add3, load, and store instructions.
1604
@end deffn
1605
@deffn {} BFD_RELOC_M32R_GOT24
1606
@deffnx {} BFD_RELOC_M32R_26_PLTREL
1607
@deffnx {} BFD_RELOC_M32R_COPY
1608
@deffnx {} BFD_RELOC_M32R_GLOB_DAT
1609
@deffnx {} BFD_RELOC_M32R_JMP_SLOT
1610
@deffnx {} BFD_RELOC_M32R_RELATIVE
1611
@deffnx {} BFD_RELOC_M32R_GOTOFF
1612
@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO
1613
@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO
1614
@deffnx {} BFD_RELOC_M32R_GOTOFF_LO
1615
@deffnx {} BFD_RELOC_M32R_GOTPC24
1616
@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO
1617
@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO
1618
@deffnx {} BFD_RELOC_M32R_GOT16_LO
1619
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO
1620
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO
1621
@deffnx {} BFD_RELOC_M32R_GOTPC_LO
1622
For PIC.
1623
@end deffn
1624
@deffn {} BFD_RELOC_V850_9_PCREL
1625
This is a 9-bit reloc
1626
@end deffn
1627
@deffn {} BFD_RELOC_V850_22_PCREL
1628
This is a 22-bit reloc
1629
@end deffn
1630
@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET
1631
This is a 16 bit offset from the short data area pointer.
1632
@end deffn
1633
@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET
1634
This is a 16 bit offset (of which only 15 bits are used) from the
1635
short data area pointer.
1636
@end deffn
1637
@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET
1638
This is a 16 bit offset from the zero data area pointer.
1639
@end deffn
1640
@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET
1641
This is a 16 bit offset (of which only 15 bits are used) from the
1642
zero data area pointer.
1643
@end deffn
1644
@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET
1645
This is an 8 bit offset (of which only 6 bits are used) from the
1646
tiny data area pointer.
1647
@end deffn
1648
@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET
1649
This is an 8bit offset (of which only 7 bits are used) from the tiny
1650
data area pointer.
1651
@end deffn
1652
@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET
1653
This is a 7 bit offset from the tiny data area pointer.
1654
@end deffn
1655
@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET
1656
This is a 16 bit offset from the tiny data area pointer.
1657
@end deffn
1658
@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET
1659
This is a 5 bit offset (of which only 4 bits are used) from the tiny
1660
data area pointer.
1661
@end deffn
1662
@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET
1663
This is a 4 bit offset from the tiny data area pointer.
1664
@end deffn
1665
@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
1666
This is a 16 bit offset from the short data area pointer, with the
1667
bits placed non-contiguously in the instruction.
1668
@end deffn
1669
@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
1670
This is a 16 bit offset from the zero data area pointer, with the
1671
bits placed non-contiguously in the instruction.
1672
@end deffn
1673
@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET
1674
This is a 6 bit offset from the call table base pointer.
1675
@end deffn
1676
@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET
1677
This is a 16 bit offset from the call table base pointer.
1678
@end deffn
1679
@deffn {} BFD_RELOC_V850_LONGCALL
1680
Used for relaxing indirect function calls.
1681
@end deffn
1682
@deffn {} BFD_RELOC_V850_LONGJUMP
1683
Used for relaxing indirect jumps.
1684
@end deffn
1685
@deffn {} BFD_RELOC_V850_ALIGN
1686
Used to maintain alignment whilst relaxing.
1687
@end deffn
1688
@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET
1689
This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
1690
instructions.
1691
@end deffn
1692
@deffn {} BFD_RELOC_MN10300_32_PCREL
1693
This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
1694
instruction.
1695
@end deffn
1696
@deffn {} BFD_RELOC_MN10300_16_PCREL
1697
This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
1698
instruction.
1699
@end deffn
1700
@deffn {} BFD_RELOC_TIC30_LDP
1701
This is a 8bit DP reloc for the tms320c30, where the most
1702
significant 8 bits of a 24 bit word are placed into the least
1703
significant 8 bits of the opcode.
1704
@end deffn
1705
@deffn {} BFD_RELOC_TIC54X_PARTLS7
1706
This is a 7bit reloc for the tms320c54x, where the least
1707
significant 7 bits of a 16 bit word are placed into the least
1708
significant 7 bits of the opcode.
1709
@end deffn
1710
@deffn {} BFD_RELOC_TIC54X_PARTMS9
1711
This is a 9bit DP reloc for the tms320c54x, where the most
1712
significant 9 bits of a 16 bit word are placed into the least
1713
significant 9 bits of the opcode.
1714
@end deffn
1715
@deffn {} BFD_RELOC_TIC54X_23
1716
This is an extended address 23-bit reloc for the tms320c54x.
1717
@end deffn
1718
@deffn {} BFD_RELOC_TIC54X_16_OF_23
1719
This is a 16-bit reloc for the tms320c54x, where the least
1720
significant 16 bits of a 23-bit extended address are placed into
1721
the opcode.
1722
@end deffn
1723
@deffn {} BFD_RELOC_TIC54X_MS7_OF_23
1724
This is a reloc for the tms320c54x, where the most
1725
significant 7 bits of a 23-bit extended address are placed into
1726
the opcode.
1727
@end deffn
1728
@deffn {} BFD_RELOC_FR30_48
1729
This is a 48 bit reloc for the FR30 that stores 32 bits.
1730
@end deffn
1731
@deffn {} BFD_RELOC_FR30_20
1732
This is a 32 bit reloc for the FR30 that stores 20 bits split up into
1733
two sections.
1734
@end deffn
1735
@deffn {} BFD_RELOC_FR30_6_IN_4
1736
This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
1737
4 bits.
1738
@end deffn
1739
@deffn {} BFD_RELOC_FR30_8_IN_8
1740
This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
1741
into 8 bits.
1742
@end deffn
1743
@deffn {} BFD_RELOC_FR30_9_IN_8
1744
This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
1745
into 8 bits.
1746
@end deffn
1747
@deffn {} BFD_RELOC_FR30_10_IN_8
1748
This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
1749
into 8 bits.
1750
@end deffn
1751
@deffn {} BFD_RELOC_FR30_9_PCREL
1752
This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
1753
short offset into 8 bits.
1754
@end deffn
1755
@deffn {} BFD_RELOC_FR30_12_PCREL
1756
This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
1757
short offset into 11 bits.
1758
@end deffn
1759
@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4
1760
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2
1761
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2
1762
@deffnx {} BFD_RELOC_MCORE_PCREL_32
1763
@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
1764
@deffnx {} BFD_RELOC_MCORE_RVA
1765
Motorola Mcore relocations.
1766
@end deffn
1767
@deffn {} BFD_RELOC_MEP_8
1768
@deffnx {} BFD_RELOC_MEP_16
1769
@deffnx {} BFD_RELOC_MEP_32
1770
@deffnx {} BFD_RELOC_MEP_PCREL8A2
1771
@deffnx {} BFD_RELOC_MEP_PCREL12A2
1772
@deffnx {} BFD_RELOC_MEP_PCREL17A2
1773
@deffnx {} BFD_RELOC_MEP_PCREL24A2
1774
@deffnx {} BFD_RELOC_MEP_PCABS24A2
1775
@deffnx {} BFD_RELOC_MEP_LOW16
1776
@deffnx {} BFD_RELOC_MEP_HI16U
1777
@deffnx {} BFD_RELOC_MEP_HI16S
1778
@deffnx {} BFD_RELOC_MEP_GPREL
1779
@deffnx {} BFD_RELOC_MEP_TPREL
1780
@deffnx {} BFD_RELOC_MEP_TPREL7
1781
@deffnx {} BFD_RELOC_MEP_TPREL7A2
1782
@deffnx {} BFD_RELOC_MEP_TPREL7A4
1783
@deffnx {} BFD_RELOC_MEP_UIMM24
1784
@deffnx {} BFD_RELOC_MEP_ADDR24A4
1785
@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT
1786
@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY
1787
Toshiba Media Processor Relocations.
1788
@end deffn
1789
@deffn {} BFD_RELOC_MMIX_GETA
1790
@deffnx {} BFD_RELOC_MMIX_GETA_1
1791
@deffnx {} BFD_RELOC_MMIX_GETA_2
1792
@deffnx {} BFD_RELOC_MMIX_GETA_3
1793
These are relocations for the GETA instruction.
1794
@end deffn
1795
@deffn {} BFD_RELOC_MMIX_CBRANCH
1796
@deffnx {} BFD_RELOC_MMIX_CBRANCH_J
1797
@deffnx {} BFD_RELOC_MMIX_CBRANCH_1
1798
@deffnx {} BFD_RELOC_MMIX_CBRANCH_2
1799
@deffnx {} BFD_RELOC_MMIX_CBRANCH_3
1800
These are relocations for a conditional branch instruction.
1801
@end deffn
1802
@deffn {} BFD_RELOC_MMIX_PUSHJ
1803
@deffnx {} BFD_RELOC_MMIX_PUSHJ_1
1804
@deffnx {} BFD_RELOC_MMIX_PUSHJ_2
1805
@deffnx {} BFD_RELOC_MMIX_PUSHJ_3
1806
@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE
1807
These are relocations for the PUSHJ instruction.
1808
@end deffn
1809
@deffn {} BFD_RELOC_MMIX_JMP
1810
@deffnx {} BFD_RELOC_MMIX_JMP_1
1811
@deffnx {} BFD_RELOC_MMIX_JMP_2
1812
@deffnx {} BFD_RELOC_MMIX_JMP_3
1813
These are relocations for the JMP instruction.
1814
@end deffn
1815
@deffn {} BFD_RELOC_MMIX_ADDR19
1816
This is a relocation for a relative address as in a GETA instruction or
1817
a branch.
1818
@end deffn
1819
@deffn {} BFD_RELOC_MMIX_ADDR27
1820
This is a relocation for a relative address as in a JMP instruction.
1821
@end deffn
1822
@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE
1823
This is a relocation for an instruction field that may be a general
1824
register or a value 0..255.
1825
@end deffn
1826
@deffn {} BFD_RELOC_MMIX_REG
1827
This is a relocation for an instruction field that may be a general
1828
register.
1829
@end deffn
1830
@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET
1831
This is a relocation for two instruction fields holding a register and
1832
an offset, the equivalent of the relocation.
1833
@end deffn
1834
@deffn {} BFD_RELOC_MMIX_LOCAL
1835
This relocation is an assertion that the expression is not allocated as
1836
a global register.  It does not modify contents.
1837
@end deffn
1838
@deffn {} BFD_RELOC_AVR_7_PCREL
1839
This is a 16 bit reloc for the AVR that stores 8 bit pc relative
1840
short offset into 7 bits.
1841
@end deffn
1842
@deffn {} BFD_RELOC_AVR_13_PCREL
1843
This is a 16 bit reloc for the AVR that stores 13 bit pc relative
1844
short offset into 12 bits.
1845
@end deffn
1846
@deffn {} BFD_RELOC_AVR_16_PM
1847
This is a 16 bit reloc for the AVR that stores 17 bit value (usually
1848
program memory address) into 16 bits.
1849
@end deffn
1850
@deffn {} BFD_RELOC_AVR_LO8_LDI
1851
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1852
data memory address) into 8 bit immediate value of LDI insn.
1853
@end deffn
1854
@deffn {} BFD_RELOC_AVR_HI8_LDI
1855
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1856
of data memory address) into 8 bit immediate value of LDI insn.
1857
@end deffn
1858
@deffn {} BFD_RELOC_AVR_HH8_LDI
1859
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1860
of program memory address) into 8 bit immediate value of LDI insn.
1861
@end deffn
1862
@deffn {} BFD_RELOC_AVR_MS8_LDI
1863
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1864
of 32 bit value) into 8 bit immediate value of LDI insn.
1865
@end deffn
1866
@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG
1867
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1868
(usually data memory address) into 8 bit immediate value of SUBI insn.
1869
@end deffn
1870
@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG
1871
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1872
(high 8 bit of data memory address) into 8 bit immediate value of
1873
SUBI insn.
1874
@end deffn
1875
@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG
1876
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1877
(most high 8 bit of program memory address) into 8 bit immediate value
1878
of LDI or SUBI insn.
1879
@end deffn
1880
@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG
1881
This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
1882
of 32 bit value) into 8 bit immediate value of LDI insn.
1883
@end deffn
1884
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM
1885
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1886
command address) into 8 bit immediate value of LDI insn.
1887
@end deffn
1888
@deffn {} BFD_RELOC_AVR_LO8_LDI_GS
1889
This is a 16 bit reloc for the AVR that stores 8 bit value
1890
(command address) into 8 bit immediate value of LDI insn. If the address
1891
is beyond the 128k boundary, the linker inserts a jump stub for this reloc
1892
in the lower 128k.
1893
@end deffn
1894
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM
1895
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1896
of command address) into 8 bit immediate value of LDI insn.
1897
@end deffn
1898
@deffn {} BFD_RELOC_AVR_HI8_LDI_GS
1899
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1900
of command address) into 8 bit immediate value of LDI insn.  If the address
1901
is beyond the 128k boundary, the linker inserts a jump stub for this reloc
1902
below 128k.
1903
@end deffn
1904
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM
1905
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1906
of command address) into 8 bit immediate value of LDI insn.
1907
@end deffn
1908
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG
1909
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1910
(usually command address) into 8 bit immediate value of SUBI insn.
1911
@end deffn
1912
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG
1913
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1914
(high 8 bit of 16 bit command address) into 8 bit immediate value
1915
of SUBI insn.
1916
@end deffn
1917
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG
1918
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1919
(high 6 bit of 22 bit command address) into 8 bit immediate
1920
value of SUBI insn.
1921
@end deffn
1922
@deffn {} BFD_RELOC_AVR_CALL
1923
This is a 32 bit reloc for the AVR that stores 23 bit value
1924
into 22 bits.
1925
@end deffn
1926
@deffn {} BFD_RELOC_AVR_LDI
1927
This is a 16 bit reloc for the AVR that stores all needed bits
1928
for absolute addressing with ldi with overflow check to linktime
1929
@end deffn
1930
@deffn {} BFD_RELOC_AVR_6
1931
This is a 6 bit reloc for the AVR that stores offset for ldd/std
1932
instructions
1933
@end deffn
1934
@deffn {} BFD_RELOC_AVR_6_ADIW
1935
This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
1936
instructions
1937
@end deffn
1938
@deffn {} BFD_RELOC_390_12
1939
Direct 12 bit.
1940
@end deffn
1941
@deffn {} BFD_RELOC_390_GOT12
1942
12 bit GOT offset.
1943
@end deffn
1944
@deffn {} BFD_RELOC_390_PLT32
1945
32 bit PC relative PLT address.
1946
@end deffn
1947
@deffn {} BFD_RELOC_390_COPY
1948
Copy symbol at runtime.
1949
@end deffn
1950
@deffn {} BFD_RELOC_390_GLOB_DAT
1951
Create GOT entry.
1952
@end deffn
1953
@deffn {} BFD_RELOC_390_JMP_SLOT
1954
Create PLT entry.
1955
@end deffn
1956
@deffn {} BFD_RELOC_390_RELATIVE
1957
Adjust by program base.
1958
@end deffn
1959
@deffn {} BFD_RELOC_390_GOTPC
1960
32 bit PC relative offset to GOT.
1961
@end deffn
1962
@deffn {} BFD_RELOC_390_GOT16
1963
16 bit GOT offset.
1964
@end deffn
1965
@deffn {} BFD_RELOC_390_PC16DBL
1966
PC relative 16 bit shifted by 1.
1967
@end deffn
1968
@deffn {} BFD_RELOC_390_PLT16DBL
1969
16 bit PC rel. PLT shifted by 1.
1970
@end deffn
1971
@deffn {} BFD_RELOC_390_PC32DBL
1972
PC relative 32 bit shifted by 1.
1973
@end deffn
1974
@deffn {} BFD_RELOC_390_PLT32DBL
1975
32 bit PC rel. PLT shifted by 1.
1976
@end deffn
1977
@deffn {} BFD_RELOC_390_GOTPCDBL
1978
32 bit PC rel. GOT shifted by 1.
1979
@end deffn
1980
@deffn {} BFD_RELOC_390_GOT64
1981
64 bit GOT offset.
1982
@end deffn
1983
@deffn {} BFD_RELOC_390_PLT64
1984
64 bit PC relative PLT address.
1985
@end deffn
1986
@deffn {} BFD_RELOC_390_GOTENT
1987
32 bit rel. offset to GOT entry.
1988
@end deffn
1989
@deffn {} BFD_RELOC_390_GOTOFF64
1990
64 bit offset to GOT.
1991
@end deffn
1992
@deffn {} BFD_RELOC_390_GOTPLT12
1993
12-bit offset to symbol-entry within GOT, with PLT handling.
1994
@end deffn
1995
@deffn {} BFD_RELOC_390_GOTPLT16
1996
16-bit offset to symbol-entry within GOT, with PLT handling.
1997
@end deffn
1998
@deffn {} BFD_RELOC_390_GOTPLT32
1999
32-bit offset to symbol-entry within GOT, with PLT handling.
2000
@end deffn
2001
@deffn {} BFD_RELOC_390_GOTPLT64
2002
64-bit offset to symbol-entry within GOT, with PLT handling.
2003
@end deffn
2004
@deffn {} BFD_RELOC_390_GOTPLTENT
2005
32-bit rel. offset to symbol-entry within GOT, with PLT handling.
2006
@end deffn
2007
@deffn {} BFD_RELOC_390_PLTOFF16
2008
16-bit rel. offset from the GOT to a PLT entry.
2009
@end deffn
2010
@deffn {} BFD_RELOC_390_PLTOFF32
2011
32-bit rel. offset from the GOT to a PLT entry.
2012
@end deffn
2013
@deffn {} BFD_RELOC_390_PLTOFF64
2014
64-bit rel. offset from the GOT to a PLT entry.
2015
@end deffn
2016
@deffn {} BFD_RELOC_390_TLS_LOAD
2017
@deffnx {} BFD_RELOC_390_TLS_GDCALL
2018
@deffnx {} BFD_RELOC_390_TLS_LDCALL
2019
@deffnx {} BFD_RELOC_390_TLS_GD32
2020
@deffnx {} BFD_RELOC_390_TLS_GD64
2021
@deffnx {} BFD_RELOC_390_TLS_GOTIE12
2022
@deffnx {} BFD_RELOC_390_TLS_GOTIE32
2023
@deffnx {} BFD_RELOC_390_TLS_GOTIE64
2024
@deffnx {} BFD_RELOC_390_TLS_LDM32
2025
@deffnx {} BFD_RELOC_390_TLS_LDM64
2026
@deffnx {} BFD_RELOC_390_TLS_IE32
2027
@deffnx {} BFD_RELOC_390_TLS_IE64
2028
@deffnx {} BFD_RELOC_390_TLS_IEENT
2029
@deffnx {} BFD_RELOC_390_TLS_LE32
2030
@deffnx {} BFD_RELOC_390_TLS_LE64
2031
@deffnx {} BFD_RELOC_390_TLS_LDO32
2032
@deffnx {} BFD_RELOC_390_TLS_LDO64
2033
@deffnx {} BFD_RELOC_390_TLS_DTPMOD
2034
@deffnx {} BFD_RELOC_390_TLS_DTPOFF
2035
@deffnx {} BFD_RELOC_390_TLS_TPOFF
2036
s390 tls relocations.
2037
@end deffn
2038
@deffn {} BFD_RELOC_390_20
2039
@deffnx {} BFD_RELOC_390_GOT20
2040
@deffnx {} BFD_RELOC_390_GOTPLT20
2041
@deffnx {} BFD_RELOC_390_TLS_GOTIE20
2042
Long displacement extension.
2043
@end deffn
2044
@deffn {} BFD_RELOC_SCORE_DUMMY1
2045
Score relocations
2046
@end deffn
2047
@deffn {} BFD_RELOC_SCORE_GPREL15
2048
Low 16 bit for load/store
2049
@end deffn
2050
@deffn {} BFD_RELOC_SCORE_DUMMY2
2051
@deffnx {} BFD_RELOC_SCORE_JMP
2052
This is a 24-bit reloc with the right 1 bit assumed to be 0
2053
@end deffn
2054
@deffn {} BFD_RELOC_SCORE_BRANCH
2055
This is a 19-bit reloc with the right 1 bit assumed to be 0
2056
@end deffn
2057
@deffn {} BFD_RELOC_SCORE16_JMP
2058
This is a 11-bit reloc with the right 1 bit assumed to be 0
2059
@end deffn
2060
@deffn {} BFD_RELOC_SCORE16_BRANCH
2061
This is a 8-bit reloc with the right 1 bit assumed to be 0
2062
@end deffn
2063
@deffn {} BFD_RELOC_SCORE_GOT15
2064
@deffnx {} BFD_RELOC_SCORE_GOT_LO16
2065
@deffnx {} BFD_RELOC_SCORE_CALL15
2066
@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16
2067
Undocumented Score relocs
2068
@end deffn
2069
@deffn {} BFD_RELOC_IP2K_FR9
2070
Scenix IP2K - 9-bit register number / data address
2071
@end deffn
2072
@deffn {} BFD_RELOC_IP2K_BANK
2073
Scenix IP2K - 4-bit register/data bank number
2074
@end deffn
2075
@deffn {} BFD_RELOC_IP2K_ADDR16CJP
2076
Scenix IP2K - low 13 bits of instruction word address
2077
@end deffn
2078
@deffn {} BFD_RELOC_IP2K_PAGE3
2079
Scenix IP2K - high 3 bits of instruction word address
2080
@end deffn
2081
@deffn {} BFD_RELOC_IP2K_LO8DATA
2082
@deffnx {} BFD_RELOC_IP2K_HI8DATA
2083
@deffnx {} BFD_RELOC_IP2K_EX8DATA
2084
Scenix IP2K - ext/low/high 8 bits of data address
2085
@end deffn
2086
@deffn {} BFD_RELOC_IP2K_LO8INSN
2087
@deffnx {} BFD_RELOC_IP2K_HI8INSN
2088
Scenix IP2K - low/high 8 bits of instruction word address
2089
@end deffn
2090
@deffn {} BFD_RELOC_IP2K_PC_SKIP
2091
Scenix IP2K - even/odd PC modifier to modify snb pcl.0
2092
@end deffn
2093
@deffn {} BFD_RELOC_IP2K_TEXT
2094
Scenix IP2K - 16 bit word address in text section.
2095
@end deffn
2096
@deffn {} BFD_RELOC_IP2K_FR_OFFSET
2097
Scenix IP2K - 7-bit sp or dp offset
2098
@end deffn
2099
@deffn {} BFD_RELOC_VPE4KMATH_DATA
2100
@deffnx {} BFD_RELOC_VPE4KMATH_INSN
2101
Scenix VPE4K coprocessor - data/insn-space addressing
2102
@end deffn
2103
@deffn {} BFD_RELOC_VTABLE_INHERIT
2104
@deffnx {} BFD_RELOC_VTABLE_ENTRY
2105
These two relocations are used by the linker to determine which of
2106
the entries in a C++ virtual function table are actually used.  When
2107
the --gc-sections option is given, the linker will zero out the entries
2108
that are not used, so that the code for those functions need not be
2109
included in the output.
2110
 
2111
VTABLE_INHERIT is a zero-space relocation used to describe to the
2112
linker the inheritance tree of a C++ virtual function table.  The
2113
relocation's symbol should be the parent class' vtable, and the
2114
relocation should be located at the child vtable.
2115
 
2116
VTABLE_ENTRY is a zero-space relocation that describes the use of a
2117
virtual function table entry.  The reloc's symbol should refer to the
2118
table of the class mentioned in the code.  Off of that base, an offset
2119
describes the entry that is being used.  For Rela hosts, this offset
2120
is stored in the reloc's addend.  For Rel hosts, we are forced to put
2121
this offset in the reloc's section offset.
2122
@end deffn
2123
@deffn {} BFD_RELOC_IA64_IMM14
2124
@deffnx {} BFD_RELOC_IA64_IMM22
2125
@deffnx {} BFD_RELOC_IA64_IMM64
2126
@deffnx {} BFD_RELOC_IA64_DIR32MSB
2127
@deffnx {} BFD_RELOC_IA64_DIR32LSB
2128
@deffnx {} BFD_RELOC_IA64_DIR64MSB
2129
@deffnx {} BFD_RELOC_IA64_DIR64LSB
2130
@deffnx {} BFD_RELOC_IA64_GPREL22
2131
@deffnx {} BFD_RELOC_IA64_GPREL64I
2132
@deffnx {} BFD_RELOC_IA64_GPREL32MSB
2133
@deffnx {} BFD_RELOC_IA64_GPREL32LSB
2134
@deffnx {} BFD_RELOC_IA64_GPREL64MSB
2135
@deffnx {} BFD_RELOC_IA64_GPREL64LSB
2136
@deffnx {} BFD_RELOC_IA64_LTOFF22
2137
@deffnx {} BFD_RELOC_IA64_LTOFF64I
2138
@deffnx {} BFD_RELOC_IA64_PLTOFF22
2139
@deffnx {} BFD_RELOC_IA64_PLTOFF64I
2140
@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB
2141
@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB
2142
@deffnx {} BFD_RELOC_IA64_FPTR64I
2143
@deffnx {} BFD_RELOC_IA64_FPTR32MSB
2144
@deffnx {} BFD_RELOC_IA64_FPTR32LSB
2145
@deffnx {} BFD_RELOC_IA64_FPTR64MSB
2146
@deffnx {} BFD_RELOC_IA64_FPTR64LSB
2147
@deffnx {} BFD_RELOC_IA64_PCREL21B
2148
@deffnx {} BFD_RELOC_IA64_PCREL21BI
2149
@deffnx {} BFD_RELOC_IA64_PCREL21M
2150
@deffnx {} BFD_RELOC_IA64_PCREL21F
2151
@deffnx {} BFD_RELOC_IA64_PCREL22
2152
@deffnx {} BFD_RELOC_IA64_PCREL60B
2153
@deffnx {} BFD_RELOC_IA64_PCREL64I
2154
@deffnx {} BFD_RELOC_IA64_PCREL32MSB
2155
@deffnx {} BFD_RELOC_IA64_PCREL32LSB
2156
@deffnx {} BFD_RELOC_IA64_PCREL64MSB
2157
@deffnx {} BFD_RELOC_IA64_PCREL64LSB
2158
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22
2159
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I
2160
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB
2161
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB
2162
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB
2163
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB
2164
@deffnx {} BFD_RELOC_IA64_SEGREL32MSB
2165
@deffnx {} BFD_RELOC_IA64_SEGREL32LSB
2166
@deffnx {} BFD_RELOC_IA64_SEGREL64MSB
2167
@deffnx {} BFD_RELOC_IA64_SEGREL64LSB
2168
@deffnx {} BFD_RELOC_IA64_SECREL32MSB
2169
@deffnx {} BFD_RELOC_IA64_SECREL32LSB
2170
@deffnx {} BFD_RELOC_IA64_SECREL64MSB
2171
@deffnx {} BFD_RELOC_IA64_SECREL64LSB
2172
@deffnx {} BFD_RELOC_IA64_REL32MSB
2173
@deffnx {} BFD_RELOC_IA64_REL32LSB
2174
@deffnx {} BFD_RELOC_IA64_REL64MSB
2175
@deffnx {} BFD_RELOC_IA64_REL64LSB
2176
@deffnx {} BFD_RELOC_IA64_LTV32MSB
2177
@deffnx {} BFD_RELOC_IA64_LTV32LSB
2178
@deffnx {} BFD_RELOC_IA64_LTV64MSB
2179
@deffnx {} BFD_RELOC_IA64_LTV64LSB
2180
@deffnx {} BFD_RELOC_IA64_IPLTMSB
2181
@deffnx {} BFD_RELOC_IA64_IPLTLSB
2182
@deffnx {} BFD_RELOC_IA64_COPY
2183
@deffnx {} BFD_RELOC_IA64_LTOFF22X
2184
@deffnx {} BFD_RELOC_IA64_LDXMOV
2185
@deffnx {} BFD_RELOC_IA64_TPREL14
2186
@deffnx {} BFD_RELOC_IA64_TPREL22
2187
@deffnx {} BFD_RELOC_IA64_TPREL64I
2188
@deffnx {} BFD_RELOC_IA64_TPREL64MSB
2189
@deffnx {} BFD_RELOC_IA64_TPREL64LSB
2190
@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22
2191
@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB
2192
@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB
2193
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22
2194
@deffnx {} BFD_RELOC_IA64_DTPREL14
2195
@deffnx {} BFD_RELOC_IA64_DTPREL22
2196
@deffnx {} BFD_RELOC_IA64_DTPREL64I
2197
@deffnx {} BFD_RELOC_IA64_DTPREL32MSB
2198
@deffnx {} BFD_RELOC_IA64_DTPREL32LSB
2199
@deffnx {} BFD_RELOC_IA64_DTPREL64MSB
2200
@deffnx {} BFD_RELOC_IA64_DTPREL64LSB
2201
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22
2202
Intel IA64 Relocations.
2203
@end deffn
2204
@deffn {} BFD_RELOC_M68HC11_HI8
2205
Motorola 68HC11 reloc.
2206
This is the 8 bit high part of an absolute address.
2207
@end deffn
2208
@deffn {} BFD_RELOC_M68HC11_LO8
2209
Motorola 68HC11 reloc.
2210
This is the 8 bit low part of an absolute address.
2211
@end deffn
2212
@deffn {} BFD_RELOC_M68HC11_3B
2213
Motorola 68HC11 reloc.
2214
This is the 3 bit of a value.
2215
@end deffn
2216
@deffn {} BFD_RELOC_M68HC11_RL_JUMP
2217
Motorola 68HC11 reloc.
2218
This reloc marks the beginning of a jump/call instruction.
2219
It is used for linker relaxation to correctly identify beginning
2220
of instruction and change some branches to use PC-relative
2221
addressing mode.
2222
@end deffn
2223
@deffn {} BFD_RELOC_M68HC11_RL_GROUP
2224
Motorola 68HC11 reloc.
2225
This reloc marks a group of several instructions that gcc generates
2226
and for which the linker relaxation pass can modify and/or remove
2227
some of them.
2228
@end deffn
2229
@deffn {} BFD_RELOC_M68HC11_LO16
2230
Motorola 68HC11 reloc.
2231
This is the 16-bit lower part of an address.  It is used for 'call'
2232
instruction to specify the symbol address without any special
2233
transformation (due to memory bank window).
2234
@end deffn
2235
@deffn {} BFD_RELOC_M68HC11_PAGE
2236
Motorola 68HC11 reloc.
2237
This is a 8-bit reloc that specifies the page number of an address.
2238
It is used by 'call' instruction to specify the page number of
2239
the symbol.
2240
@end deffn
2241
@deffn {} BFD_RELOC_M68HC11_24
2242
Motorola 68HC11 reloc.
2243
This is a 24-bit reloc that represents the address with a 16-bit
2244
value and a 8-bit page number.  The symbol address is transformed
2245
to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
2246
@end deffn
2247
@deffn {} BFD_RELOC_M68HC12_5B
2248
Motorola 68HC12 reloc.
2249
This is the 5 bits of a value.
2250
@end deffn
2251
@deffn {} BFD_RELOC_16C_NUM08
2252
@deffnx {} BFD_RELOC_16C_NUM08_C
2253
@deffnx {} BFD_RELOC_16C_NUM16
2254
@deffnx {} BFD_RELOC_16C_NUM16_C
2255
@deffnx {} BFD_RELOC_16C_NUM32
2256
@deffnx {} BFD_RELOC_16C_NUM32_C
2257
@deffnx {} BFD_RELOC_16C_DISP04
2258
@deffnx {} BFD_RELOC_16C_DISP04_C
2259
@deffnx {} BFD_RELOC_16C_DISP08
2260
@deffnx {} BFD_RELOC_16C_DISP08_C
2261
@deffnx {} BFD_RELOC_16C_DISP16
2262
@deffnx {} BFD_RELOC_16C_DISP16_C
2263
@deffnx {} BFD_RELOC_16C_DISP24
2264
@deffnx {} BFD_RELOC_16C_DISP24_C
2265
@deffnx {} BFD_RELOC_16C_DISP24a
2266
@deffnx {} BFD_RELOC_16C_DISP24a_C
2267
@deffnx {} BFD_RELOC_16C_REG04
2268
@deffnx {} BFD_RELOC_16C_REG04_C
2269
@deffnx {} BFD_RELOC_16C_REG04a
2270
@deffnx {} BFD_RELOC_16C_REG04a_C
2271
@deffnx {} BFD_RELOC_16C_REG14
2272
@deffnx {} BFD_RELOC_16C_REG14_C
2273
@deffnx {} BFD_RELOC_16C_REG16
2274
@deffnx {} BFD_RELOC_16C_REG16_C
2275
@deffnx {} BFD_RELOC_16C_REG20
2276
@deffnx {} BFD_RELOC_16C_REG20_C
2277
@deffnx {} BFD_RELOC_16C_ABS20
2278
@deffnx {} BFD_RELOC_16C_ABS20_C
2279
@deffnx {} BFD_RELOC_16C_ABS24
2280
@deffnx {} BFD_RELOC_16C_ABS24_C
2281
@deffnx {} BFD_RELOC_16C_IMM04
2282
@deffnx {} BFD_RELOC_16C_IMM04_C
2283
@deffnx {} BFD_RELOC_16C_IMM16
2284
@deffnx {} BFD_RELOC_16C_IMM16_C
2285
@deffnx {} BFD_RELOC_16C_IMM20
2286
@deffnx {} BFD_RELOC_16C_IMM20_C
2287
@deffnx {} BFD_RELOC_16C_IMM24
2288
@deffnx {} BFD_RELOC_16C_IMM24_C
2289
@deffnx {} BFD_RELOC_16C_IMM32
2290
@deffnx {} BFD_RELOC_16C_IMM32_C
2291
NS CR16C Relocations.
2292
@end deffn
2293
@deffn {} BFD_RELOC_CR16_NUM8
2294
@deffnx {} BFD_RELOC_CR16_NUM16
2295
@deffnx {} BFD_RELOC_CR16_NUM32
2296
@deffnx {} BFD_RELOC_CR16_NUM32a
2297
@deffnx {} BFD_RELOC_CR16_REGREL0
2298
@deffnx {} BFD_RELOC_CR16_REGREL4
2299
@deffnx {} BFD_RELOC_CR16_REGREL4a
2300
@deffnx {} BFD_RELOC_CR16_REGREL14
2301
@deffnx {} BFD_RELOC_CR16_REGREL14a
2302
@deffnx {} BFD_RELOC_CR16_REGREL16
2303
@deffnx {} BFD_RELOC_CR16_REGREL20
2304
@deffnx {} BFD_RELOC_CR16_REGREL20a
2305
@deffnx {} BFD_RELOC_CR16_ABS20
2306
@deffnx {} BFD_RELOC_CR16_ABS24
2307
@deffnx {} BFD_RELOC_CR16_IMM4
2308
@deffnx {} BFD_RELOC_CR16_IMM8
2309
@deffnx {} BFD_RELOC_CR16_IMM16
2310
@deffnx {} BFD_RELOC_CR16_IMM20
2311
@deffnx {} BFD_RELOC_CR16_IMM24
2312
@deffnx {} BFD_RELOC_CR16_IMM32
2313
@deffnx {} BFD_RELOC_CR16_IMM32a
2314
@deffnx {} BFD_RELOC_CR16_DISP4
2315
@deffnx {} BFD_RELOC_CR16_DISP8
2316
@deffnx {} BFD_RELOC_CR16_DISP16
2317
@deffnx {} BFD_RELOC_CR16_DISP20
2318
@deffnx {} BFD_RELOC_CR16_DISP24
2319
@deffnx {} BFD_RELOC_CR16_DISP24a
2320
@deffnx {} BFD_RELOC_CR16_SWITCH8
2321
@deffnx {} BFD_RELOC_CR16_SWITCH16
2322
@deffnx {} BFD_RELOC_CR16_SWITCH32
2323
NS CR16 Relocations.
2324
@end deffn
2325
@deffn {} BFD_RELOC_CRX_REL4
2326
@deffnx {} BFD_RELOC_CRX_REL8
2327
@deffnx {} BFD_RELOC_CRX_REL8_CMP
2328
@deffnx {} BFD_RELOC_CRX_REL16
2329
@deffnx {} BFD_RELOC_CRX_REL24
2330
@deffnx {} BFD_RELOC_CRX_REL32
2331
@deffnx {} BFD_RELOC_CRX_REGREL12
2332
@deffnx {} BFD_RELOC_CRX_REGREL22
2333
@deffnx {} BFD_RELOC_CRX_REGREL28
2334
@deffnx {} BFD_RELOC_CRX_REGREL32
2335
@deffnx {} BFD_RELOC_CRX_ABS16
2336
@deffnx {} BFD_RELOC_CRX_ABS32
2337
@deffnx {} BFD_RELOC_CRX_NUM8
2338
@deffnx {} BFD_RELOC_CRX_NUM16
2339
@deffnx {} BFD_RELOC_CRX_NUM32
2340
@deffnx {} BFD_RELOC_CRX_IMM16
2341
@deffnx {} BFD_RELOC_CRX_IMM32
2342
@deffnx {} BFD_RELOC_CRX_SWITCH8
2343
@deffnx {} BFD_RELOC_CRX_SWITCH16
2344
@deffnx {} BFD_RELOC_CRX_SWITCH32
2345
NS CRX Relocations.
2346
@end deffn
2347
@deffn {} BFD_RELOC_CRIS_BDISP8
2348
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5
2349
@deffnx {} BFD_RELOC_CRIS_SIGNED_6
2350
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6
2351
@deffnx {} BFD_RELOC_CRIS_SIGNED_8
2352
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8
2353
@deffnx {} BFD_RELOC_CRIS_SIGNED_16
2354
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16
2355
@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET
2356
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4
2357
These relocs are only used within the CRIS assembler.  They are not
2358
(at present) written to any object files.
2359
@end deffn
2360
@deffn {} BFD_RELOC_CRIS_COPY
2361
@deffnx {} BFD_RELOC_CRIS_GLOB_DAT
2362
@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT
2363
@deffnx {} BFD_RELOC_CRIS_RELATIVE
2364
Relocs used in ELF shared libraries for CRIS.
2365
@end deffn
2366
@deffn {} BFD_RELOC_CRIS_32_GOT
2367
32-bit offset to symbol-entry within GOT.
2368
@end deffn
2369
@deffn {} BFD_RELOC_CRIS_16_GOT
2370
16-bit offset to symbol-entry within GOT.
2371
@end deffn
2372
@deffn {} BFD_RELOC_CRIS_32_GOTPLT
2373
32-bit offset to symbol-entry within GOT, with PLT handling.
2374
@end deffn
2375
@deffn {} BFD_RELOC_CRIS_16_GOTPLT
2376
16-bit offset to symbol-entry within GOT, with PLT handling.
2377
@end deffn
2378
@deffn {} BFD_RELOC_CRIS_32_GOTREL
2379
32-bit offset to symbol, relative to GOT.
2380
@end deffn
2381
@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL
2382
32-bit offset to symbol with PLT entry, relative to GOT.
2383
@end deffn
2384
@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL
2385
32-bit offset to symbol with PLT entry, relative to this relocation.
2386
@end deffn
2387
@deffn {} BFD_RELOC_860_COPY
2388
@deffnx {} BFD_RELOC_860_GLOB_DAT
2389
@deffnx {} BFD_RELOC_860_JUMP_SLOT
2390
@deffnx {} BFD_RELOC_860_RELATIVE
2391
@deffnx {} BFD_RELOC_860_PC26
2392
@deffnx {} BFD_RELOC_860_PLT26
2393
@deffnx {} BFD_RELOC_860_PC16
2394
@deffnx {} BFD_RELOC_860_LOW0
2395
@deffnx {} BFD_RELOC_860_SPLIT0
2396
@deffnx {} BFD_RELOC_860_LOW1
2397
@deffnx {} BFD_RELOC_860_SPLIT1
2398
@deffnx {} BFD_RELOC_860_LOW2
2399
@deffnx {} BFD_RELOC_860_SPLIT2
2400
@deffnx {} BFD_RELOC_860_LOW3
2401
@deffnx {} BFD_RELOC_860_LOGOT0
2402
@deffnx {} BFD_RELOC_860_SPGOT0
2403
@deffnx {} BFD_RELOC_860_LOGOT1
2404
@deffnx {} BFD_RELOC_860_SPGOT1
2405
@deffnx {} BFD_RELOC_860_LOGOTOFF0
2406
@deffnx {} BFD_RELOC_860_SPGOTOFF0
2407
@deffnx {} BFD_RELOC_860_LOGOTOFF1
2408
@deffnx {} BFD_RELOC_860_SPGOTOFF1
2409
@deffnx {} BFD_RELOC_860_LOGOTOFF2
2410
@deffnx {} BFD_RELOC_860_LOGOTOFF3
2411
@deffnx {} BFD_RELOC_860_LOPC
2412
@deffnx {} BFD_RELOC_860_HIGHADJ
2413
@deffnx {} BFD_RELOC_860_HAGOT
2414
@deffnx {} BFD_RELOC_860_HAGOTOFF
2415
@deffnx {} BFD_RELOC_860_HAPC
2416
@deffnx {} BFD_RELOC_860_HIGH
2417
@deffnx {} BFD_RELOC_860_HIGOT
2418
@deffnx {} BFD_RELOC_860_HIGOTOFF
2419
Intel i860 Relocations.
2420
@end deffn
2421
@deffn {} BFD_RELOC_OPENRISC_ABS_26
2422
@deffnx {} BFD_RELOC_OPENRISC_REL_26
2423
OpenRISC Relocations.
2424
@end deffn
2425
@deffn {} BFD_RELOC_H8_DIR16A8
2426
@deffnx {} BFD_RELOC_H8_DIR16R8
2427
@deffnx {} BFD_RELOC_H8_DIR24A8
2428
@deffnx {} BFD_RELOC_H8_DIR24R8
2429
@deffnx {} BFD_RELOC_H8_DIR32A16
2430
H8 elf Relocations.
2431
@end deffn
2432
@deffn {} BFD_RELOC_XSTORMY16_REL_12
2433
@deffnx {} BFD_RELOC_XSTORMY16_12
2434
@deffnx {} BFD_RELOC_XSTORMY16_24
2435
@deffnx {} BFD_RELOC_XSTORMY16_FPTR16
2436
Sony Xstormy16 Relocations.
2437
@end deffn
2438
@deffn {} BFD_RELOC_RELC
2439
Self-describing complex relocations.
2440
@end deffn
2441
@deffn {} BFD_RELOC_XC16X_PAG
2442
@deffnx {} BFD_RELOC_XC16X_POF
2443
@deffnx {} BFD_RELOC_XC16X_SEG
2444
@deffnx {} BFD_RELOC_XC16X_SOF
2445
Infineon Relocations.
2446
@end deffn
2447
@deffn {} BFD_RELOC_VAX_GLOB_DAT
2448
@deffnx {} BFD_RELOC_VAX_JMP_SLOT
2449
@deffnx {} BFD_RELOC_VAX_RELATIVE
2450
Relocations used by VAX ELF.
2451
@end deffn
2452
@deffn {} BFD_RELOC_MT_PC16
2453
Morpho MT - 16 bit immediate relocation.
2454
@end deffn
2455
@deffn {} BFD_RELOC_MT_HI16
2456
Morpho MT - Hi 16 bits of an address.
2457
@end deffn
2458
@deffn {} BFD_RELOC_MT_LO16
2459
Morpho MT - Low 16 bits of an address.
2460
@end deffn
2461
@deffn {} BFD_RELOC_MT_GNU_VTINHERIT
2462
Morpho MT - Used to tell the linker which vtable entries are used.
2463
@end deffn
2464
@deffn {} BFD_RELOC_MT_GNU_VTENTRY
2465
Morpho MT - Used to tell the linker which vtable entries are used.
2466
@end deffn
2467
@deffn {} BFD_RELOC_MT_PCINSN8
2468
Morpho MT - 8 bit immediate relocation.
2469
@end deffn
2470
@deffn {} BFD_RELOC_MSP430_10_PCREL
2471
@deffnx {} BFD_RELOC_MSP430_16_PCREL
2472
@deffnx {} BFD_RELOC_MSP430_16
2473
@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE
2474
@deffnx {} BFD_RELOC_MSP430_16_BYTE
2475
@deffnx {} BFD_RELOC_MSP430_2X_PCREL
2476
@deffnx {} BFD_RELOC_MSP430_RL_PCREL
2477
msp430 specific relocation codes
2478
@end deffn
2479
@deffn {} BFD_RELOC_IQ2000_OFFSET_16
2480
@deffnx {} BFD_RELOC_IQ2000_OFFSET_21
2481
@deffnx {} BFD_RELOC_IQ2000_UHI16
2482
IQ2000 Relocations.
2483
@end deffn
2484
@deffn {} BFD_RELOC_XTENSA_RTLD
2485
Special Xtensa relocation used only by PLT entries in ELF shared
2486
objects to indicate that the runtime linker should set the value
2487
to one of its own internal functions or data structures.
2488
@end deffn
2489
@deffn {} BFD_RELOC_XTENSA_GLOB_DAT
2490
@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT
2491
@deffnx {} BFD_RELOC_XTENSA_RELATIVE
2492
Xtensa relocations for ELF shared objects.
2493
@end deffn
2494
@deffn {} BFD_RELOC_XTENSA_PLT
2495
Xtensa relocation used in ELF object files for symbols that may require
2496
PLT entries.  Otherwise, this is just a generic 32-bit relocation.
2497
@end deffn
2498
@deffn {} BFD_RELOC_XTENSA_DIFF8
2499
@deffnx {} BFD_RELOC_XTENSA_DIFF16
2500
@deffnx {} BFD_RELOC_XTENSA_DIFF32
2501
Xtensa relocations to mark the difference of two local symbols.
2502
These are only needed to support linker relaxation and can be ignored
2503
when not relaxing.  The field is set to the value of the difference
2504
assuming no relaxation.  The relocation encodes the position of the
2505
first symbol so the linker can determine whether to adjust the field
2506
value.
2507
@end deffn
2508
@deffn {} BFD_RELOC_XTENSA_SLOT0_OP
2509
@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP
2510
@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP
2511
@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP
2512
@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP
2513
@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP
2514
@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP
2515
@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP
2516
@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP
2517
@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP
2518
@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP
2519
@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP
2520
@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP
2521
@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP
2522
@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP
2523
Generic Xtensa relocations for instruction operands.  Only the slot
2524
number is encoded in the relocation.  The relocation applies to the
2525
last PC-relative immediate operand, or if there are no PC-relative
2526
immediates, to the last immediate operand.
2527
@end deffn
2528
@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT
2529
@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT
2530
@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT
2531
@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT
2532
@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT
2533
@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT
2534
@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT
2535
@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT
2536
@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT
2537
@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT
2538
@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT
2539
@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT
2540
@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT
2541
@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT
2542
@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT
2543
Alternate Xtensa relocations.  Only the slot is encoded in the
2544
relocation.  The meaning of these relocations is opcode-specific.
2545
@end deffn
2546
@deffn {} BFD_RELOC_XTENSA_OP0
2547
@deffnx {} BFD_RELOC_XTENSA_OP1
2548
@deffnx {} BFD_RELOC_XTENSA_OP2
2549
Xtensa relocations for backward compatibility.  These have all been
2550
replaced by BFD_RELOC_XTENSA_SLOT0_OP.
2551
@end deffn
2552
@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND
2553
Xtensa relocation to mark that the assembler expanded the
2554
instructions from an original target.  The expansion size is
2555
encoded in the reloc size.
2556
@end deffn
2557
@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY
2558
Xtensa relocation to mark that the linker should simplify
2559
assembler-expanded instructions.  This is commonly used
2560
internally by the linker after analysis of a
2561
BFD_RELOC_XTENSA_ASM_EXPAND.
2562
@end deffn
2563
@deffn {} BFD_RELOC_Z80_DISP8
2564
8 bit signed offset in (ix+d) or (iy+d).
2565
@end deffn
2566
@deffn {} BFD_RELOC_Z8K_DISP7
2567
DJNZ offset.
2568
@end deffn
2569
@deffn {} BFD_RELOC_Z8K_CALLR
2570
CALR offset.
2571
@end deffn
2572
@deffn {} BFD_RELOC_Z8K_IMM4L
2573
4 bit value.
2574
@end deffn
2575
 
2576
@example
2577
 
2578
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
2579
@end example
2580
@findex bfd_reloc_type_lookup
2581
@subsubsection @code{bfd_reloc_type_lookup}
2582
@strong{Synopsis}
2583
@example
2584
reloc_howto_type *bfd_reloc_type_lookup
2585
   (bfd *abfd, bfd_reloc_code_real_type code);
2586
reloc_howto_type *bfd_reloc_name_lookup
2587
   (bfd *abfd, const char *reloc_name);
2588
@end example
2589
@strong{Description}@*
2590
Return a pointer to a howto structure which, when
2591
invoked, will perform the relocation @var{code} on data from the
2592
architecture noted.
2593
 
2594
@findex bfd_default_reloc_type_lookup
2595
@subsubsection @code{bfd_default_reloc_type_lookup}
2596
@strong{Synopsis}
2597
@example
2598
reloc_howto_type *bfd_default_reloc_type_lookup
2599
   (bfd *abfd, bfd_reloc_code_real_type  code);
2600
@end example
2601
@strong{Description}@*
2602
Provides a default relocation lookup routine for any architecture.
2603
 
2604
@findex bfd_get_reloc_code_name
2605
@subsubsection @code{bfd_get_reloc_code_name}
2606
@strong{Synopsis}
2607
@example
2608
const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
2609
@end example
2610
@strong{Description}@*
2611
Provides a printable name for the supplied relocation code.
2612
Useful mainly for printing error messages.
2613
 
2614
@findex bfd_generic_relax_section
2615
@subsubsection @code{bfd_generic_relax_section}
2616
@strong{Synopsis}
2617
@example
2618
bfd_boolean bfd_generic_relax_section
2619
   (bfd *abfd,
2620
    asection *section,
2621
    struct bfd_link_info *,
2622
    bfd_boolean *);
2623
@end example
2624
@strong{Description}@*
2625
Provides default handling for relaxing for back ends which
2626
don't do relaxing.
2627
 
2628
@findex bfd_generic_gc_sections
2629
@subsubsection @code{bfd_generic_gc_sections}
2630
@strong{Synopsis}
2631
@example
2632
bfd_boolean bfd_generic_gc_sections
2633
   (bfd *, struct bfd_link_info *);
2634
@end example
2635
@strong{Description}@*
2636
Provides default handling for relaxing for back ends which
2637
don't do section gc -- i.e., does nothing.
2638
 
2639
@findex bfd_generic_merge_sections
2640
@subsubsection @code{bfd_generic_merge_sections}
2641
@strong{Synopsis}
2642
@example
2643
bfd_boolean bfd_generic_merge_sections
2644
   (bfd *, struct bfd_link_info *);
2645
@end example
2646
@strong{Description}@*
2647
Provides default handling for SEC_MERGE section merging for back ends
2648
which don't have SEC_MERGE support -- i.e., does nothing.
2649
 
2650
@findex bfd_generic_get_relocated_section_contents
2651
@subsubsection @code{bfd_generic_get_relocated_section_contents}
2652
@strong{Synopsis}
2653
@example
2654
bfd_byte *bfd_generic_get_relocated_section_contents
2655
   (bfd *abfd,
2656
    struct bfd_link_info *link_info,
2657
    struct bfd_link_order *link_order,
2658
    bfd_byte *data,
2659
    bfd_boolean relocatable,
2660
    asymbol **symbols);
2661
@end example
2662
@strong{Description}@*
2663
Provides default handling of relocation effort for back ends
2664
which can't be bothered to do it efficiently.
2665
 

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