OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [config/] [bfin-aux.h] - Blame information for rev 866

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 132 jeremybenn
/* bfin-aux.h ADI Blackfin Header file for gas
2
   Copyright 2005, 2007
3
   Free Software Foundation, Inc.
4
 
5
   This file is part of GAS, the GNU Assembler.
6
 
7
   GAS is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   GAS is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GAS; see the file COPYING.  If not, write to the Free
19
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20
   02110-1301, USA.  */
21
 
22
#include "bfin-defs.h"
23
 
24
#define REG_T Register *
25
 
26
INSTR_T
27
bfin_gen_dsp32mac (int op1, int mm, int mmod, int w1, int p,
28
              int h01, int h11, int h00, int h10,
29
              int op0, REG_T dst, REG_T src0, REG_T src1, int w0);
30
 
31
INSTR_T
32
bfin_gen_dsp32mult (int op1, int mm, int mmod, int w1, int p,
33
               int h01, int h11, int h00, int h10,
34
               int op0, REG_T dst, REG_T src0, REG_T src1, int w0);
35
 
36
INSTR_T
37
bfin_gen_dsp32alu (int HL, int aopcde, int aop, int s, int x,
38
              REG_T dst0, REG_T dst1, REG_T src0, REG_T src1);
39
 
40
INSTR_T
41
bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0, REG_T src1,
42
                int sop, int hls);
43
 
44
INSTR_T
45
bfin_gen_dsp32shiftimm (int sopcde, REG_T dst0, int immag, REG_T src1,
46
                   int sop, int hls);
47
 
48
INSTR_T
49
bfin_gen_ldimmhalf (REG_T reg, int h, int s, int z, Expr_Node *hword,
50
               int reloc);
51
 
52
INSTR_T
53
bfin_gen_ldstidxi (REG_T ptr, REG_T reg, int w, int sz, int z,
54
              Expr_Node *offset);
55
 
56
INSTR_T
57
bfin_gen_ldst (REG_T ptr, REG_T reg, int aop, int sz, int z, int w);
58
 
59
INSTR_T
60
bfin_gen_ldstii (REG_T ptr, REG_T reg, Expr_Node *offset, int w, int op);
61
 
62
INSTR_T
63
bfin_gen_ldstiifp (REG_T reg, Expr_Node *offset, int w);
64
 
65
INSTR_T
66
bfin_gen_ldstpmod (REG_T ptr, REG_T reg, int aop, int w, REG_T idx);
67
 
68
INSTR_T
69
bfin_gen_dspldst (REG_T i, REG_T reg, int aop, int w, int m);
70
 
71
INSTR_T
72
bfin_gen_alu2op (REG_T dst, REG_T src, int opc);
73
 
74
INSTR_T
75
bfin_gen_compi2opd (REG_T dst, int src, int op);
76
 
77
INSTR_T
78
bfin_gen_compi2opp (REG_T dst, int src, int op);
79
 
80
INSTR_T
81
bfin_gen_dagmodik (REG_T i, int op);
82
 
83
INSTR_T
84
bfin_gen_dagmodim (REG_T i, REG_T m, int op, int br);
85
 
86
INSTR_T
87
bfin_gen_ptr2op (REG_T dst, REG_T src, int opc);
88
 
89
INSTR_T
90
bfin_gen_logi2op (int dst, int src, int opc);
91
 
92
INSTR_T
93
bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc);
94
 
95
INSTR_T
96
bfin_gen_ccmv (REG_T src, REG_T dst, int t);
97
 
98
INSTR_T
99
bfin_gen_ccflag (REG_T x, int y, int opc, int i, int g);
100
 
101
INSTR_T
102
bfin_gen_cc2stat (int cbit, int op, int d);
103
 
104
INSTR_T
105
bfin_gen_regmv (REG_T src, REG_T dst);
106
 
107
INSTR_T
108
bfin_gen_cc2dreg (int op, REG_T reg);
109
 
110
INSTR_T
111
bfin_gen_brcc (int t, int b, Expr_Node *offset);
112
 
113
INSTR_T
114
bfin_gen_ujump (Expr_Node *offset);
115
 
116
INSTR_T
117
bfin_gen_cactrl (REG_T reg, int a, int op);
118
 
119
INSTR_T
120
bfin_gen_progctrl (int prgfunc, int poprnd);
121
 
122
INSTR_T
123
bfin_gen_loopsetup (Expr_Node *soffset, REG_T c, int rop,
124
               Expr_Node *eoffset, REG_T reg);
125
 
126
INSTR_T
127
bfin_gen_loop (Expr_Node *expr, REG_T reg, int rop, REG_T preg);
128
 
129
INSTR_T
130
bfin_gen_pushpopmultiple (int dr, int pr, int d, int p, int w);
131
 
132
INSTR_T
133
bfin_gen_pushpopreg (REG_T reg, int w);
134
 
135
INSTR_T
136
bfin_gen_calla (Expr_Node *addr, int s);
137
 
138
INSTR_T
139
bfin_gen_linkage (int r, int framesize);
140
 
141
INSTR_T
142
bfin_gen_pseudodbg (int fn, int reg, int grp);
143
 
144
INSTR_T
145
bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected);
146
 
147
bfd_boolean
148
bfin_resource_conflict (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2);
149
 
150
INSTR_T
151
bfin_gen_multi_instr (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.