OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [config/] [m68k-parse.h] - Blame information for rev 857

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
/* m68k-parse.h -- header file for m68k assembler
2
   Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
3
   2003, 2004, 2005, 2007 Free Software Foundation, Inc.
4
 
5
   This file is part of GAS, the GNU Assembler.
6
 
7
   GAS is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   GAS is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GAS; see the file COPYING.  If not, write to the Free
19
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20
   02110-1301, USA.  */
21
 
22
#ifndef M68K_PARSE_H
23
#define M68K_PARSE_H
24
 
25
/* This header file defines things which are shared between the
26
   operand parser in m68k.y and the m68k assembler proper in
27
   tc-m68k.c.  */
28
 
29
/* The various m68k registers.  */
30
 
31
/* DATA and ADDR have to be contiguous, so that reg-DATA gives
32
   0-7==data reg, 8-15==addr reg for operands that take both types.
33
 
34
   We don't use forms like "ADDR0 = ADDR" here because this file is
35
   likely to be used on an Apollo, and the broken Apollo compiler
36
   gives an `undefined variable' error if we do that, according to
37
   troy@cbme.unsw.edu.au.  */
38
 
39
#define DATA DATA0
40
#define ADDR ADDR0
41
#define SP ADDR7
42
#define BAD BAD0
43
#define BAC BAC0
44
 
45
enum m68k_register
46
{
47
  DATA0 = 1,                    /*   1- 8 == data registers 0-7 */
48
  DATA1,
49
  DATA2,
50
  DATA3,
51
  DATA4,
52
  DATA5,
53
  DATA6,
54
  DATA7,
55
 
56
  ADDR0,
57
  ADDR1,
58
  ADDR2,
59
  ADDR3,
60
  ADDR4,
61
  ADDR5,
62
  ADDR6,
63
  ADDR7,
64
 
65
  FP0,                          /* Eight FP registers */
66
  FP1,
67
  FP2,
68
  FP3,
69
  FP4,
70
  FP5,
71
  FP6,
72
  FP7,
73
 
74
  COP0,                         /* Co-processor #0-#7 */
75
  COP1,
76
  COP2,
77
  COP3,
78
  COP4,
79
  COP5,
80
  COP6,
81
  COP7,
82
 
83
  PC,                           /* Program counter */
84
  ZPC,                          /* Hack for Program space, but 0 addressing */
85
  SR,                           /* Status Reg */
86
  CCR,                          /* Condition code Reg */
87
  ACC,                          /* Accumulator Reg0 (EMAC or ACC on MAC).  */
88
  ACC1,                         /* Accumulator Reg 1 (EMAC).  */
89
  ACC2,                         /* Accumulator Reg 2 (EMAC).  */
90
  ACC3,                         /* Accumulator Reg 3 (EMAC).  */
91
  ACCEXT01,                     /* Accumulator extension 0&1 (EMAC).  */
92
  ACCEXT23,                     /* Accumulator extension 2&3 (EMAC).  */
93
  MACSR,                        /* MAC Status Reg */
94
  MASK,                         /* Modulus Reg */
95
 
96
  /* These have to be grouped together for the movec instruction to work.  */
97
  USP,                          /*  User Stack Pointer */
98
  ISP,                          /*  Interrupt stack pointer */
99
  SFC,
100
  DFC,
101
  CACR,
102
  VBR,
103
  CAAR,
104
  MSP,
105
  ITT0,
106
  ITT1,
107
  DTT0,
108
  DTT1,
109
  MMUSR,
110
  TC,
111
  SRP,
112
  URP,
113
  BUSCR,                        /* 68060 added these.  */
114
  PCR,
115
  ROMBAR,                       /* mcf5200 added these.  */
116
  RAMBAR_ALT,                   /* Some CF chips have RAMBAR using
117
                                   RAMBAR0's number */
118
  RAMBAR0,
119
  RAMBAR1,
120
  MMUBAR,                       /* mcfv4e added these.  */
121
  ROMBAR0,                      /* mcfv4e added these.  */
122
  ROMBAR1,                      /* mcfv4e added these.  */
123
  MPCR, EDRAMBAR, SECMBAR,      /* mcfv4e added these.  */
124
  PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
125
  PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these.  */
126
  PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these.  */
127
  MBAR0, MBAR1,                 /* mcfv4e added these.  */
128
  ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
129
  FLASHBAR, RAMBAR,             /* mcf528x added these.  */
130
  MBAR2,                        /* mcf5249 added this.  */
131
  MBAR,
132
  ASID,                         /* m5475.  */
133
  CAC,                          /* fido added this.  */
134
  MBO,
135
#define last_movec_reg MBO
136
  /* End of movec ordering constraints.  */
137
 
138
  FPI,
139
  FPS,
140
  FPC,
141
 
142
  DRP,                          /* 68851 or 68030 MMU regs */
143
  CRP,
144
  CAL,
145
  VAL,
146
  SCC,
147
  AC,
148
  BAD0,
149
  BAD1,
150
  BAD2,
151
  BAD3,
152
  BAD4,
153
  BAD5,
154
  BAD6,
155
  BAD7,
156
  BAC0,
157
  BAC1,
158
  BAC2,
159
  BAC3,
160
  BAC4,
161
  BAC5,
162
  BAC6,
163
  BAC7,
164
  PSR,                          /* aka MMUSR on 68030 (but not MMUSR on 68040)
165
                                   and ACUSR on 68ec030 */
166
  PCSR,
167
 
168
  IC,                           /* instruction cache token */
169
  DC,                           /* data cache token */
170
  NC,                           /* no cache token */
171
  BC,                           /* both caches token */
172
 
173
  TT0,                          /* 68030 access control unit regs */
174
  TT1,
175
 
176
  ZDATA0,                       /* suppressed data registers.  */
177
  ZDATA1,
178
  ZDATA2,
179
  ZDATA3,
180
  ZDATA4,
181
  ZDATA5,
182
  ZDATA6,
183
  ZDATA7,
184
 
185
  ZADDR0,                       /* suppressed address registers.  */
186
  ZADDR1,
187
  ZADDR2,
188
  ZADDR3,
189
  ZADDR4,
190
  ZADDR5,
191
  ZADDR6,
192
  ZADDR7,
193
 
194
  /* Upper and lower half of data and address registers.  Order *must*
195
     be DATAxL, ADDRxL, DATAxU, ADDRxU.  */
196
  DATA0L,                       /* lower half of data registers */
197
  DATA1L,
198
  DATA2L,
199
  DATA3L,
200
  DATA4L,
201
  DATA5L,
202
  DATA6L,
203
  DATA7L,
204
 
205
  ADDR0L,                       /* lower half of address registers */
206
  ADDR1L,
207
  ADDR2L,
208
  ADDR3L,
209
  ADDR4L,
210
  ADDR5L,
211
  ADDR6L,
212
  ADDR7L,
213
 
214
  DATA0U,                       /* upper half of data registers */
215
  DATA1U,
216
  DATA2U,
217
  DATA3U,
218
  DATA4U,
219
  DATA5U,
220
  DATA6U,
221
  DATA7U,
222
 
223
  ADDR0U,                       /* upper half of address registers */
224
  ADDR1U,
225
  ADDR2U,
226
  ADDR3U,
227
  ADDR4U,
228
  ADDR5U,
229
  ADDR6U,
230
  ADDR7U,
231
};
232
 
233
/* Size information.  */
234
 
235
enum m68k_size
236
{
237
  /* Unspecified.  */
238
  SIZE_UNSPEC,
239
 
240
  /* Byte.  */
241
  SIZE_BYTE,
242
 
243
  /* Word (2 bytes).  */
244
  SIZE_WORD,
245
 
246
  /* Longword (4 bytes).  */
247
  SIZE_LONG
248
};
249
 
250
/* The structure used to hold information about an index register.  */
251
 
252
struct m68k_indexreg
253
{
254
  /* The index register itself.  */
255
  enum m68k_register reg;
256
 
257
  /* The size to use.  */
258
  enum m68k_size size;
259
 
260
  /* The value to scale by.  */
261
  int scale;
262
};
263
 
264
#ifdef OBJ_ELF
265
/* The type of a PIC expression.  */
266
 
267
enum pic_relocation
268
{
269
  pic_none,                     /* not pic */
270
  pic_plt_pcrel,                /* @PLTPC */
271
  pic_got_pcrel,                /* @GOTPC */
272
  pic_plt_off,                  /* @PLT */
273
  pic_got_off                   /* @GOT */
274
};
275
#endif
276
 
277
/* The structure used to hold information about an expression.  */
278
 
279
struct m68k_exp
280
{
281
  /* The size to use.  */
282
  enum m68k_size size;
283
 
284
#ifdef OBJ_ELF
285
  /* The type of pic relocation if any.  */
286
  enum pic_relocation pic_reloc;
287
#endif
288
 
289
  /* The expression itself.  */
290
  expressionS exp;
291
};
292
 
293
/* The operand modes.  */
294
 
295
enum m68k_operand_type
296
{
297
  IMMED = 1,
298
  ABSL,
299
  DREG,
300
  AREG,
301
  FPREG,
302
  CONTROL,
303
  AINDR,
304
  AINC,
305
  ADEC,
306
  DISP,
307
  BASE,
308
  POST,
309
  PRE,
310
  LSH,  /* MAC/EMAC scalefactor '<<'.  */
311
  RSH,  /* MAC/EMAC scalefactor '>>'.  */
312
  REGLST
313
};
314
 
315
/* The structure used to hold a parsed operand.  */
316
 
317
struct m68k_op
318
{
319
  /* The type of operand.  */
320
  enum m68k_operand_type mode;
321
 
322
  /* The main register.  */
323
  enum m68k_register reg;
324
 
325
  /* The register mask for mode REGLST.  */
326
  unsigned long mask;
327
 
328
  /* An error message.  */
329
  const char *error;
330
 
331
  /* The index register.  */
332
  struct m68k_indexreg index;
333
 
334
  /* The displacement.  */
335
  struct m68k_exp disp;
336
 
337
  /* The outer displacement.  */
338
  struct m68k_exp odisp;
339
 
340
  /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
341
  int trailing_ampersand;
342
};
343
 
344
#endif /* ! defined (M68K_PARSE_H) */
345
 
346
/* The parsing function.  */
347
 
348
extern int m68k_ip_op (char *, struct m68k_op *);
349
 
350
/* Whether register prefixes are optional.  */
351
extern int flag_reg_prefix_optional;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.