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[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [config/] [tc-i386.c] - Blame information for rev 156

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/* tc-i386.c -- Assemble code for the Intel 80386
2
   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3
   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4
   Free Software Foundation, Inc.
5
 
6
   This file is part of GAS, the GNU Assembler.
7
 
8
   GAS is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3, or (at your option)
11
   any later version.
12
 
13
   GAS is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with GAS; see the file COPYING.  If not, write to the Free
20
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21
   02110-1301, USA.  */
22
 
23
/* Intel 80386 machine specific gas.
24
   Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25
   x86_64 support by Jan Hubicka (jh@suse.cz)
26
   VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27
   Bugs & suggestions are completely welcome.  This is free software.
28
   Please help us make it better.  */
29
 
30
#include "as.h"
31
#include "safe-ctype.h"
32
#include "subsegs.h"
33
#include "dwarf2dbg.h"
34
#include "dw2gencfi.h"
35
#include "elf/x86-64.h"
36
#include "opcodes/i386-init.h"
37
 
38
#ifndef REGISTER_WARNINGS
39
#define REGISTER_WARNINGS 1
40
#endif
41
 
42
#ifndef INFER_ADDR_PREFIX
43
#define INFER_ADDR_PREFIX 1
44
#endif
45
 
46
#ifndef DEFAULT_ARCH
47
#define DEFAULT_ARCH "i386"
48
#endif
49
 
50
#ifndef INLINE
51
#if __GNUC__ >= 2
52
#define INLINE __inline__
53
#else
54
#define INLINE
55
#endif
56
#endif
57
 
58
/* Prefixes will be emitted in the order defined below.
59
   WAIT_PREFIX must be the first prefix since FWAIT is really is an
60
   instruction, and so must come before any prefixes.
61
   The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62
   LOCKREP_PREFIX.  */
63
#define WAIT_PREFIX     0
64
#define SEG_PREFIX      1
65
#define ADDR_PREFIX     2
66
#define DATA_PREFIX     3
67
#define LOCKREP_PREFIX  4
68
#define REX_PREFIX      5       /* must come last.  */
69
#define MAX_PREFIXES    6       /* max prefixes per opcode */
70
 
71
/* we define the syntax here (modulo base,index,scale syntax) */
72
#define REGISTER_PREFIX '%'
73
#define IMMEDIATE_PREFIX '$'
74
#define ABSOLUTE_PREFIX '*'
75
 
76
/* these are the instruction mnemonic suffixes in AT&T syntax or
77
   memory operand size in Intel syntax.  */
78
#define WORD_MNEM_SUFFIX  'w'
79
#define BYTE_MNEM_SUFFIX  'b'
80
#define SHORT_MNEM_SUFFIX 's'
81
#define LONG_MNEM_SUFFIX  'l'
82
#define QWORD_MNEM_SUFFIX  'q'
83
#define XMMWORD_MNEM_SUFFIX  'x'
84
#define YMMWORD_MNEM_SUFFIX 'y'
85
/* Intel Syntax.  Use a non-ascii letter since since it never appears
86
   in instructions.  */
87
#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
 
89
#define END_OF_INSN '\0'
90
 
91
/*
92
  'templates' is for grouping together 'template' structures for opcodes
93
  of the same name.  This is only used for storing the insns in the grand
94
  ole hash table of insns.
95
  The templates themselves start at START and range up to (but not including)
96
  END.
97
  */
98
typedef struct
99
{
100
  const template *start;
101
  const template *end;
102
}
103
templates;
104
 
105
/* 386 operand encoding bytes:  see 386 book for details of this.  */
106
typedef struct
107
{
108
  unsigned int regmem;  /* codes register or memory operand */
109
  unsigned int reg;     /* codes register operand (or extended opcode) */
110
  unsigned int mode;    /* how to interpret regmem & reg */
111
}
112
modrm_byte;
113
 
114
/* x86-64 extension prefix.  */
115
typedef int rex_byte;
116
 
117
/* The SSE5 instructions have a two bit instruction modifier (OC) that
118
   is stored in two separate bytes in the instruction.  Pick apart OC
119
   into the 2 separate bits for instruction.  */
120
#define DREX_OC0(x)     (((x) & 1) != 0)
121
#define DREX_OC1(x)     (((x) & 2) != 0)
122
 
123
#define DREX_OC0_MASK   (1 << 3)        /* set OC0 in byte 4 */
124
#define DREX_OC1_MASK   (1 << 2)        /* set OC1 in byte 3 */
125
 
126
/* OC mappings */
127
#define DREX_XMEM_X1_X2_X2 0    /* 4 op insn, dest = src3, src1 = reg/mem */
128
#define DREX_X1_XMEM_X2_X2 1    /* 4 op insn, dest = src3, src2 = reg/mem */
129
#define DREX_X1_XMEM_X2_X1 2    /* 4 op insn, dest = src1, src2 = reg/mem */
130
#define DREX_X1_X2_XMEM_X1 3    /* 4 op insn, dest = src1, src3 = reg/mem */
131
 
132
#define DREX_XMEM_X1_X2    0    /* 3 op insn, src1 = reg/mem */
133
#define DREX_X1_XMEM_X2    1    /* 3 op insn, src1 = reg/mem */
134
 
135
/* Information needed to create the DREX byte in SSE5 instructions.  */
136
typedef struct
137
{
138
  unsigned int reg;             /* register */
139
  unsigned int rex;             /* REX flags */
140
  unsigned int modrm_reg;       /* which arg goes in the modrm.reg field */
141
  unsigned int modrm_regmem;    /* which arg goes in the modrm.regmem field */
142
} drex_byte;
143
 
144
/* 386 opcode byte to code indirect addressing.  */
145
typedef struct
146
{
147
  unsigned base;
148
  unsigned index;
149
  unsigned scale;
150
}
151
sib_byte;
152
 
153
enum processor_type
154
{
155
  PROCESSOR_UNKNOWN,
156
  PROCESSOR_I386,
157
  PROCESSOR_I486,
158
  PROCESSOR_PENTIUM,
159
  PROCESSOR_PENTIUMPRO,
160
  PROCESSOR_PENTIUM4,
161
  PROCESSOR_NOCONA,
162
  PROCESSOR_CORE,
163
  PROCESSOR_CORE2,
164
  PROCESSOR_K6,
165
  PROCESSOR_ATHLON,
166
  PROCESSOR_K8,
167
  PROCESSOR_GENERIC32,
168
  PROCESSOR_GENERIC64,
169
  PROCESSOR_AMDFAM10
170
};
171
 
172
/* x86 arch names, types and features */
173
typedef struct
174
{
175
  const char *name;             /* arch name */
176
  enum processor_type type;     /* arch type */
177
  i386_cpu_flags flags;         /* cpu feature flags */
178
}
179
arch_entry;
180
 
181
static void set_code_flag (int);
182
static void set_16bit_gcc_code_flag (int);
183
static void set_intel_syntax (int);
184
static void set_intel_mnemonic (int);
185
static void set_allow_index_reg (int);
186
static void set_cpu_arch (int);
187
#ifdef TE_PE
188
static void pe_directive_secrel (int);
189
#endif
190
static void signed_cons (int);
191
static char *output_invalid (int c);
192
static int i386_att_operand (char *);
193
static int i386_intel_operand (char *, int);
194
static const reg_entry *parse_register (char *, char **);
195
static char *parse_insn (char *, char *);
196
static char *parse_operands (char *, const char *);
197
static void swap_operands (void);
198
static void swap_2_operands (int, int);
199
static void optimize_imm (void);
200
static void optimize_disp (void);
201
static int match_template (void);
202
static int check_string (void);
203
static int process_suffix (void);
204
static int check_byte_reg (void);
205
static int check_long_reg (void);
206
static int check_qword_reg (void);
207
static int check_word_reg (void);
208
static int finalize_imm (void);
209
static void process_drex (void);
210
static int process_operands (void);
211
static const seg_entry *build_modrm_byte (void);
212
static void output_insn (void);
213
static void output_imm (fragS *, offsetT);
214
static void output_disp (fragS *, offsetT);
215
#ifndef I386COFF
216
static void s_bss (int);
217
#endif
218
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
219
static void handle_large_common (int small ATTRIBUTE_UNUSED);
220
#endif
221
 
222
static const char *default_arch = DEFAULT_ARCH;
223
 
224
/* VEX prefix.  */
225
typedef struct
226
{
227
  /* VEX prefix is either 2 byte or 3 byte.  */
228
  unsigned char bytes[3];
229
  unsigned int length;
230
  /* Destination or source register specifier.  */
231
  const reg_entry *register_specifier;
232
} vex_prefix;
233
 
234
/* 'md_assemble ()' gathers together information and puts it into a
235
   i386_insn.  */
236
 
237
union i386_op
238
  {
239
    expressionS *disps;
240
    expressionS *imms;
241
    const reg_entry *regs;
242
  };
243
 
244
struct _i386_insn
245
  {
246
    /* TM holds the template for the insn were currently assembling.  */
247
    template tm;
248
 
249
    /* SUFFIX holds the instruction size suffix for byte, word, dword
250
       or qword, if given.  */
251
    char suffix;
252
 
253
    /* OPERANDS gives the number of given operands.  */
254
    unsigned int operands;
255
 
256
    /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
257
       of given register, displacement, memory operands and immediate
258
       operands.  */
259
    unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
260
 
261
    /* TYPES [i] is the type (see above #defines) which tells us how to
262
       use OP[i] for the corresponding operand.  */
263
    i386_operand_type types[MAX_OPERANDS];
264
 
265
    /* Displacement expression, immediate expression, or register for each
266
       operand.  */
267
    union i386_op op[MAX_OPERANDS];
268
 
269
    /* Flags for operands.  */
270
    unsigned int flags[MAX_OPERANDS];
271
#define Operand_PCrel 1
272
 
273
    /* Relocation type for operand */
274
    enum bfd_reloc_code_real reloc[MAX_OPERANDS];
275
 
276
    /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
277
       the base index byte below.  */
278
    const reg_entry *base_reg;
279
    const reg_entry *index_reg;
280
    unsigned int log2_scale_factor;
281
 
282
    /* SEG gives the seg_entries of this insn.  They are zero unless
283
       explicit segment overrides are given.  */
284
    const seg_entry *seg[2];
285
 
286
    /* PREFIX holds all the given prefix opcodes (usually null).
287
       PREFIXES is the number of prefix opcodes.  */
288
    unsigned int prefixes;
289
    unsigned char prefix[MAX_PREFIXES];
290
 
291
    /* RM and SIB are the modrm byte and the sib byte where the
292
       addressing modes of this insn are encoded.  DREX is the byte
293
       added by the SSE5 instructions.  */
294
 
295
    modrm_byte rm;
296
    rex_byte rex;
297
    sib_byte sib;
298
    drex_byte drex;
299
    vex_prefix vex;
300
  };
301
 
302
typedef struct _i386_insn i386_insn;
303
 
304
/* List of chars besides those in app.c:symbol_chars that can start an
305
   operand.  Used to prevent the scrubber eating vital white-space.  */
306
const char extra_symbol_chars[] = "*%-(["
307
#ifdef LEX_AT
308
        "@"
309
#endif
310
#ifdef LEX_QM
311
        "?"
312
#endif
313
        ;
314
 
315
#if (defined (TE_I386AIX)                               \
316
     || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
317
         && !defined (TE_GNU)                           \
318
         && !defined (TE_LINUX)                         \
319
         && !defined (TE_NETWARE)                       \
320
         && !defined (TE_FreeBSD)                       \
321
         && !defined (TE_NetBSD)))
322
/* This array holds the chars that always start a comment.  If the
323
   pre-processor is disabled, these aren't very useful.  The option
324
   --divide will remove '/' from this list.  */
325
const char *i386_comment_chars = "#/";
326
#define SVR4_COMMENT_CHARS 1
327
#define PREFIX_SEPARATOR '\\'
328
 
329
#else
330
const char *i386_comment_chars = "#";
331
#define PREFIX_SEPARATOR '/'
332
#endif
333
 
334
/* This array holds the chars that only start a comment at the beginning of
335
   a line.  If the line seems to have the form '# 123 filename'
336
   .line and .file directives will appear in the pre-processed output.
337
   Note that input_file.c hand checks for '#' at the beginning of the
338
   first line of the input file.  This is because the compiler outputs
339
   #NO_APP at the beginning of its output.
340
   Also note that comments started like this one will always work if
341
   '/' isn't otherwise defined.  */
342
const char line_comment_chars[] = "#/";
343
 
344
const char line_separator_chars[] = ";";
345
 
346
/* Chars that can be used to separate mant from exp in floating point
347
   nums.  */
348
const char EXP_CHARS[] = "eE";
349
 
350
/* Chars that mean this number is a floating point constant
351
   As in 0f12.456
352
   or    0d1.2345e12.  */
353
const char FLT_CHARS[] = "fFdDxX";
354
 
355
/* Tables for lexical analysis.  */
356
static char mnemonic_chars[256];
357
static char register_chars[256];
358
static char operand_chars[256];
359
static char identifier_chars[256];
360
static char digit_chars[256];
361
 
362
/* Lexical macros.  */
363
#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
364
#define is_operand_char(x) (operand_chars[(unsigned char) x])
365
#define is_register_char(x) (register_chars[(unsigned char) x])
366
#define is_space_char(x) ((x) == ' ')
367
#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
368
#define is_digit_char(x) (digit_chars[(unsigned char) x])
369
 
370
/* All non-digit non-letter characters that may occur in an operand.  */
371
static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
372
 
373
/* md_assemble() always leaves the strings it's passed unaltered.  To
374
   effect this we maintain a stack of saved characters that we've smashed
375
   with '\0's (indicating end of strings for various sub-fields of the
376
   assembler instruction).  */
377
static char save_stack[32];
378
static char *save_stack_p;
379
#define END_STRING_AND_SAVE(s) \
380
        do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
381
#define RESTORE_END_STRING(s) \
382
        do { *(s) = *--save_stack_p; } while (0)
383
 
384
/* The instruction we're assembling.  */
385
static i386_insn i;
386
 
387
/* Possible templates for current insn.  */
388
static const templates *current_templates;
389
 
390
/* Per instruction expressionS buffers: max displacements & immediates.  */
391
static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
392
static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
393
 
394
/* Current operand we are working on.  */
395
static int this_operand;
396
 
397
/* We support four different modes.  FLAG_CODE variable is used to distinguish
398
   these.  */
399
 
400
enum flag_code {
401
        CODE_32BIT,
402
        CODE_16BIT,
403
        CODE_64BIT };
404
 
405
static enum flag_code flag_code;
406
static unsigned int object_64bit;
407
static int use_rela_relocations = 0;
408
 
409
/* The names used to print error messages.  */
410
static const char *flag_code_names[] =
411
  {
412
    "32",
413
    "16",
414
    "64"
415
  };
416
 
417
/* 1 for intel syntax,
418
 
419
static int intel_syntax = 0;
420
 
421
/* 1 for intel mnemonic,
422
 
423
static int intel_mnemonic = !SYSV386_COMPAT;
424
 
425
/* 1 if support old (<= 2.8.1) versions of gcc.  */
426
static int old_gcc = OLDGCC_COMPAT;
427
 
428
/* 1 if pseudo registers are permitted.  */
429
static int allow_pseudo_reg = 0;
430
 
431
/* 1 if register prefix % not required.  */
432
static int allow_naked_reg = 0;
433
 
434
/* 1 if pseudo index register, eiz/riz, is allowed .  */
435
static int allow_index_reg = 0;
436
 
437
static enum
438
  {
439
    sse_check_none = 0,
440
    sse_check_warning,
441
    sse_check_error
442
  }
443
sse_check;
444
 
445
/* Register prefix used for error message.  */
446
static const char *register_prefix = "%";
447
 
448
/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
449
   leave, push, and pop instructions so that gcc has the same stack
450
   frame as in 32 bit mode.  */
451
static char stackop_size = '\0';
452
 
453
/* Non-zero to optimize code alignment.  */
454
int optimize_align_code = 1;
455
 
456
/* Non-zero to quieten some warnings.  */
457
static int quiet_warnings = 0;
458
 
459
/* CPU name.  */
460
static const char *cpu_arch_name = NULL;
461
static char *cpu_sub_arch_name = NULL;
462
 
463
/* CPU feature flags.  */
464
static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
465
 
466
/* If we have selected a cpu we are generating instructions for.  */
467
static int cpu_arch_tune_set = 0;
468
 
469
/* Cpu we are generating instructions for.  */
470
static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
471
 
472
/* CPU feature flags of cpu we are generating instructions for.  */
473
static i386_cpu_flags cpu_arch_tune_flags;
474
 
475
/* CPU instruction set architecture used.  */
476
static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
477
 
478
/* CPU feature flags of instruction set architecture used.  */
479
static i386_cpu_flags cpu_arch_isa_flags;
480
 
481
/* If set, conditional jumps are not automatically promoted to handle
482
   larger than a byte offset.  */
483
static unsigned int no_cond_jump_promotion = 0;
484
 
485
/* Encode SSE instructions with VEX prefix.  */
486
static unsigned int sse2avx;
487
 
488
/* Pre-defined "_GLOBAL_OFFSET_TABLE_".  */
489
static symbolS *GOT_symbol;
490
 
491
/* The dwarf2 return column, adjusted for 32 or 64 bit.  */
492
unsigned int x86_dwarf2_return_column;
493
 
494
/* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
495
int x86_cie_data_alignment;
496
 
497
/* Interface to relax_segment.
498
   There are 3 major relax states for 386 jump insns because the
499
   different types of jumps add different sizes to frags when we're
500
   figuring out what sort of jump to choose to reach a given label.  */
501
 
502
/* Types.  */
503
#define UNCOND_JUMP 0
504
#define COND_JUMP 1
505
#define COND_JUMP86 2
506
 
507
/* Sizes.  */
508
#define CODE16  1
509
#define SMALL   0
510
#define SMALL16 (SMALL | CODE16)
511
#define BIG     2
512
#define BIG16   (BIG | CODE16)
513
 
514
#ifndef INLINE
515
#ifdef __GNUC__
516
#define INLINE __inline__
517
#else
518
#define INLINE
519
#endif
520
#endif
521
 
522
#define ENCODE_RELAX_STATE(type, size) \
523
  ((relax_substateT) (((type) << 2) | (size)))
524
#define TYPE_FROM_RELAX_STATE(s) \
525
  ((s) >> 2)
526
#define DISP_SIZE_FROM_RELAX_STATE(s) \
527
    ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
528
 
529
/* This table is used by relax_frag to promote short jumps to long
530
   ones where necessary.  SMALL (short) jumps may be promoted to BIG
531
   (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long).  We
532
   don't allow a short jump in a 32 bit code segment to be promoted to
533
   a 16 bit offset jump because it's slower (requires data size
534
   prefix), and doesn't work, unless the destination is in the bottom
535
   64k of the code segment (The top 16 bits of eip are zeroed).  */
536
 
537
const relax_typeS md_relax_table[] =
538
{
539
  /* The fields are:
540
     1) most positive reach of this state,
541
     2) most negative reach of this state,
542
     3) how many bytes this mode will have in the variable part of the frag
543
     4) which index into the table to try if we can't fit into this one.  */
544
 
545
  /* UNCOND_JUMP states.  */
546
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
547
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
548
  /* dword jmp adds 4 bytes to frag:
549
 
550
  {0, 0, 4, 0},
551
  /* word jmp adds 2 byte2 to frag:
552
 
553
  {0, 0, 2, 0},
554
 
555
  /* COND_JUMP states.  */
556
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
557
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
558
  /* dword conditionals adds 5 bytes to frag:
559
     1 extra opcode byte, 4 displacement bytes.  */
560
  {0, 0, 5, 0},
561
  /* word conditionals add 3 bytes to frag:
562
     1 extra opcode byte, 2 displacement bytes.  */
563
  {0, 0, 3, 0},
564
 
565
  /* COND_JUMP86 states.  */
566
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
567
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
568
  /* dword conditionals adds 5 bytes to frag:
569
     1 extra opcode byte, 4 displacement bytes.  */
570
  {0, 0, 5, 0},
571
  /* word conditionals add 4 bytes to frag:
572
     1 displacement byte and a 3 byte long branch insn.  */
573
  {0, 0, 4, 0}
574
};
575
 
576
static const arch_entry cpu_arch[] =
577
{
578
  { "generic32", PROCESSOR_GENERIC32,
579
    CPU_GENERIC32_FLAGS },
580
  { "generic64", PROCESSOR_GENERIC64,
581
    CPU_GENERIC64_FLAGS },
582
  { "i8086", PROCESSOR_UNKNOWN,
583
    CPU_NONE_FLAGS },
584
  { "i186", PROCESSOR_UNKNOWN,
585
    CPU_I186_FLAGS },
586
  { "i286", PROCESSOR_UNKNOWN,
587
    CPU_I286_FLAGS },
588
  { "i386", PROCESSOR_I386,
589
    CPU_I386_FLAGS },
590
  { "i486", PROCESSOR_I486,
591
    CPU_I486_FLAGS },
592
  { "i586", PROCESSOR_PENTIUM,
593
    CPU_I586_FLAGS },
594
  { "i686", PROCESSOR_PENTIUMPRO,
595
    CPU_I686_FLAGS },
596
  { "pentium", PROCESSOR_PENTIUM,
597
    CPU_I586_FLAGS },
598
  { "pentiumpro", PROCESSOR_PENTIUMPRO,
599
    CPU_I686_FLAGS },
600
  { "pentiumii", PROCESSOR_PENTIUMPRO,
601
    CPU_P2_FLAGS },
602
  { "pentiumiii",PROCESSOR_PENTIUMPRO,
603
    CPU_P3_FLAGS },
604
  { "pentium4", PROCESSOR_PENTIUM4,
605
    CPU_P4_FLAGS },
606
  { "prescott", PROCESSOR_NOCONA,
607
    CPU_CORE_FLAGS },
608
  { "nocona", PROCESSOR_NOCONA,
609
    CPU_NOCONA_FLAGS },
610
  { "yonah", PROCESSOR_CORE,
611
    CPU_CORE_FLAGS },
612
  { "core", PROCESSOR_CORE,
613
    CPU_CORE_FLAGS },
614
  { "merom", PROCESSOR_CORE2,
615
    CPU_CORE2_FLAGS },
616
  { "core2", PROCESSOR_CORE2,
617
    CPU_CORE2_FLAGS },
618
  { "k6", PROCESSOR_K6,
619
    CPU_K6_FLAGS },
620
  { "k6_2", PROCESSOR_K6,
621
    CPU_K6_2_FLAGS },
622
  { "athlon", PROCESSOR_ATHLON,
623
    CPU_ATHLON_FLAGS },
624
  { "sledgehammer", PROCESSOR_K8,
625
    CPU_K8_FLAGS },
626
  { "opteron", PROCESSOR_K8,
627
    CPU_K8_FLAGS },
628
  { "k8", PROCESSOR_K8,
629
    CPU_K8_FLAGS },
630
  { "amdfam10", PROCESSOR_AMDFAM10,
631
    CPU_AMDFAM10_FLAGS },
632
  { ".mmx", PROCESSOR_UNKNOWN,
633
    CPU_MMX_FLAGS },
634
  { ".sse", PROCESSOR_UNKNOWN,
635
    CPU_SSE_FLAGS },
636
  { ".sse2", PROCESSOR_UNKNOWN,
637
    CPU_SSE2_FLAGS },
638
  { ".sse3", PROCESSOR_UNKNOWN,
639
    CPU_SSE3_FLAGS },
640
  { ".ssse3", PROCESSOR_UNKNOWN,
641
    CPU_SSSE3_FLAGS },
642
  { ".sse4.1", PROCESSOR_UNKNOWN,
643
    CPU_SSE4_1_FLAGS },
644
  { ".sse4.2", PROCESSOR_UNKNOWN,
645
    CPU_SSE4_2_FLAGS },
646
  { ".sse4", PROCESSOR_UNKNOWN,
647
    CPU_SSE4_2_FLAGS },
648
  { ".avx", PROCESSOR_UNKNOWN,
649
    CPU_AVX_FLAGS },
650
  { ".vmx", PROCESSOR_UNKNOWN,
651
    CPU_VMX_FLAGS },
652
  { ".smx", PROCESSOR_UNKNOWN,
653
    CPU_SMX_FLAGS },
654
  { ".xsave", PROCESSOR_UNKNOWN,
655
    CPU_XSAVE_FLAGS },
656
  { ".aes", PROCESSOR_UNKNOWN,
657
    CPU_AES_FLAGS },
658
  { ".pclmul", PROCESSOR_UNKNOWN,
659
    CPU_PCLMUL_FLAGS },
660
  { ".clmul", PROCESSOR_UNKNOWN,
661
    CPU_PCLMUL_FLAGS },
662
  { ".fma", PROCESSOR_UNKNOWN,
663
    CPU_FMA_FLAGS },
664
  { ".movbe", PROCESSOR_UNKNOWN,
665
    CPU_MOVBE_FLAGS },
666
  { ".ept", PROCESSOR_UNKNOWN,
667
    CPU_EPT_FLAGS },
668
  { ".3dnow", PROCESSOR_UNKNOWN,
669
    CPU_3DNOW_FLAGS },
670
  { ".3dnowa", PROCESSOR_UNKNOWN,
671
    CPU_3DNOWA_FLAGS },
672
  { ".padlock", PROCESSOR_UNKNOWN,
673
    CPU_PADLOCK_FLAGS },
674
  { ".pacifica", PROCESSOR_UNKNOWN,
675
    CPU_SVME_FLAGS },
676
  { ".svme", PROCESSOR_UNKNOWN,
677
    CPU_SVME_FLAGS },
678
  { ".sse4a", PROCESSOR_UNKNOWN,
679
    CPU_SSE4A_FLAGS },
680
  { ".abm", PROCESSOR_UNKNOWN,
681
    CPU_ABM_FLAGS },
682
  { ".sse5", PROCESSOR_UNKNOWN,
683
    CPU_SSE5_FLAGS },
684
};
685
 
686
const pseudo_typeS md_pseudo_table[] =
687
{
688
#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
689
  {"align", s_align_bytes, 0},
690
#else
691
  {"align", s_align_ptwo, 0},
692
#endif
693
  {"arch", set_cpu_arch, 0},
694
#ifndef I386COFF
695
  {"bss", s_bss, 0},
696
#endif
697
  {"ffloat", float_cons, 'f'},
698
  {"dfloat", float_cons, 'd'},
699
  {"tfloat", float_cons, 'x'},
700
  {"value", cons, 2},
701
  {"slong", signed_cons, 4},
702
  {"noopt", s_ignore, 0},
703
  {"optim", s_ignore, 0},
704
  {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
705
  {"code16", set_code_flag, CODE_16BIT},
706
  {"code32", set_code_flag, CODE_32BIT},
707
  {"code64", set_code_flag, CODE_64BIT},
708
  {"intel_syntax", set_intel_syntax, 1},
709
  {"att_syntax", set_intel_syntax, 0},
710
  {"intel_mnemonic", set_intel_mnemonic, 1},
711
  {"att_mnemonic", set_intel_mnemonic, 0},
712
  {"allow_index_reg", set_allow_index_reg, 1},
713
  {"disallow_index_reg", set_allow_index_reg, 0},
714
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
715
  {"largecomm", handle_large_common, 0},
716
#else
717
  {"file", (void (*) (int)) dwarf2_directive_file, 0},
718
  {"loc", dwarf2_directive_loc, 0},
719
  {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
720
#endif
721
#ifdef TE_PE
722
  {"secrel32", pe_directive_secrel, 0},
723
#endif
724
  {0, 0, 0}
725
};
726
 
727
/* For interface with expression ().  */
728
extern char *input_line_pointer;
729
 
730
/* Hash table for instruction mnemonic lookup.  */
731
static struct hash_control *op_hash;
732
 
733
/* Hash table for register lookup.  */
734
static struct hash_control *reg_hash;
735
 
736
void
737
i386_align_code (fragS *fragP, int count)
738
{
739
  /* Various efficient no-op patterns for aligning code labels.
740
     Note: Don't try to assemble the instructions in the comments.
741
     0L and 0w are not legal.  */
742
  static const char f32_1[] =
743
    {0x90};                                     /* nop                  */
744
  static const char f32_2[] =
745
    {0x66,0x90};                                /* xchg %ax,%ax */
746
  static const char f32_3[] =
747
    {0x8d,0x76,0x00};                           /* leal 0(%esi),%esi    */
748
  static const char f32_4[] =
749
    {0x8d,0x74,0x26,0x00};                      /* leal 0(%esi,1),%esi  */
750
  static const char f32_5[] =
751
    {0x90,                                      /* nop                  */
752
     0x8d,0x74,0x26,0x00};                      /* leal 0(%esi,1),%esi  */
753
  static const char f32_6[] =
754
    {0x8d,0xb6,0x00,0x00,0x00,0x00};            /* leal 0L(%esi),%esi   */
755
  static const char f32_7[] =
756
    {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00};       /* leal 0L(%esi,1),%esi */
757
  static const char f32_8[] =
758
    {0x90,                                      /* nop                  */
759
     0x8d,0xb4,0x26,0x00,0x00,0x00,0x00};       /* leal 0L(%esi,1),%esi */
760
  static const char f32_9[] =
761
    {0x89,0xf6,                                 /* movl %esi,%esi       */
762
     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
763
  static const char f32_10[] =
764
    {0x8d,0x76,0x00,                            /* leal 0(%esi),%esi    */
765
     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
766
  static const char f32_11[] =
767
    {0x8d,0x74,0x26,0x00,                       /* leal 0(%esi,1),%esi  */
768
     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
769
  static const char f32_12[] =
770
    {0x8d,0xb6,0x00,0x00,0x00,0x00,             /* leal 0L(%esi),%esi   */
771
     0x8d,0xbf,0x00,0x00,0x00,0x00};            /* leal 0L(%edi),%edi   */
772
  static const char f32_13[] =
773
    {0x8d,0xb6,0x00,0x00,0x00,0x00,             /* leal 0L(%esi),%esi   */
774
     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
775
  static const char f32_14[] =
776
    {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00,        /* leal 0L(%esi,1),%esi */
777
     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
778
  static const char f16_3[] =
779
    {0x8d,0x74,0x00};                           /* lea 0(%esi),%esi     */
780
  static const char f16_4[] =
781
    {0x8d,0xb4,0x00,0x00};                      /* lea 0w(%si),%si      */
782
  static const char f16_5[] =
783
    {0x90,                                      /* nop                  */
784
     0x8d,0xb4,0x00,0x00};                      /* lea 0w(%si),%si      */
785
  static const char f16_6[] =
786
    {0x89,0xf6,                                 /* mov %si,%si          */
787
     0x8d,0xbd,0x00,0x00};                      /* lea 0w(%di),%di      */
788
  static const char f16_7[] =
789
    {0x8d,0x74,0x00,                            /* lea 0(%si),%si       */
790
     0x8d,0xbd,0x00,0x00};                      /* lea 0w(%di),%di      */
791
  static const char f16_8[] =
792
    {0x8d,0xb4,0x00,0x00,                       /* lea 0w(%si),%si      */
793
     0x8d,0xbd,0x00,0x00};                      /* lea 0w(%di),%di      */
794
  static const char jump_31[] =
795
    {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90,        /* jmp .+31; lotsa nops */
796
     0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
797
     0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
798
     0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
799
  static const char *const f32_patt[] = {
800
    f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
801
    f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
802
  };
803
  static const char *const f16_patt[] = {
804
    f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
805
  };
806
  /* nopl (%[re]ax) */
807
  static const char alt_3[] =
808
    {0x0f,0x1f,0x00};
809
  /* nopl 0(%[re]ax) */
810
  static const char alt_4[] =
811
    {0x0f,0x1f,0x40,0x00};
812
  /* nopl 0(%[re]ax,%[re]ax,1) */
813
  static const char alt_5[] =
814
    {0x0f,0x1f,0x44,0x00,0x00};
815
  /* nopw 0(%[re]ax,%[re]ax,1) */
816
  static const char alt_6[] =
817
    {0x66,0x0f,0x1f,0x44,0x00,0x00};
818
  /* nopl 0L(%[re]ax) */
819
  static const char alt_7[] =
820
    {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
821
  /* nopl 0L(%[re]ax,%[re]ax,1) */
822
  static const char alt_8[] =
823
    {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
824
  /* nopw 0L(%[re]ax,%[re]ax,1) */
825
  static const char alt_9[] =
826
    {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
827
  /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
828
  static const char alt_10[] =
829
    {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
830
  /* data16
831
     nopw %cs:0L(%[re]ax,%[re]ax,1) */
832
  static const char alt_long_11[] =
833
    {0x66,
834
     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
835
  /* data16
836
     data16
837
     nopw %cs:0L(%[re]ax,%[re]ax,1) */
838
  static const char alt_long_12[] =
839
    {0x66,
840
     0x66,
841
     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
842
  /* data16
843
     data16
844
     data16
845
     nopw %cs:0L(%[re]ax,%[re]ax,1) */
846
  static const char alt_long_13[] =
847
    {0x66,
848
     0x66,
849
     0x66,
850
     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
851
  /* data16
852
     data16
853
     data16
854
     data16
855
     nopw %cs:0L(%[re]ax,%[re]ax,1) */
856
  static const char alt_long_14[] =
857
    {0x66,
858
     0x66,
859
     0x66,
860
     0x66,
861
     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862
  /* data16
863
     data16
864
     data16
865
     data16
866
     data16
867
     nopw %cs:0L(%[re]ax,%[re]ax,1) */
868
  static const char alt_long_15[] =
869
    {0x66,
870
     0x66,
871
     0x66,
872
     0x66,
873
     0x66,
874
     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875
  /* nopl 0(%[re]ax,%[re]ax,1)
876
     nopw 0(%[re]ax,%[re]ax,1) */
877
  static const char alt_short_11[] =
878
    {0x0f,0x1f,0x44,0x00,0x00,
879
     0x66,0x0f,0x1f,0x44,0x00,0x00};
880
  /* nopw 0(%[re]ax,%[re]ax,1)
881
     nopw 0(%[re]ax,%[re]ax,1) */
882
  static const char alt_short_12[] =
883
    {0x66,0x0f,0x1f,0x44,0x00,0x00,
884
     0x66,0x0f,0x1f,0x44,0x00,0x00};
885
  /* nopw 0(%[re]ax,%[re]ax,1)
886
     nopl 0L(%[re]ax) */
887
  static const char alt_short_13[] =
888
    {0x66,0x0f,0x1f,0x44,0x00,0x00,
889
     0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
890
  /* nopl 0L(%[re]ax)
891
     nopl 0L(%[re]ax) */
892
  static const char alt_short_14[] =
893
    {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
894
     0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
895
  /* nopl 0L(%[re]ax)
896
     nopl 0L(%[re]ax,%[re]ax,1) */
897
  static const char alt_short_15[] =
898
    {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
899
     0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900
  static const char *const alt_short_patt[] = {
901
    f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
902
    alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
903
    alt_short_14, alt_short_15
904
  };
905
  static const char *const alt_long_patt[] = {
906
    f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
907
    alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
908
    alt_long_14, alt_long_15
909
  };
910
 
911
  /* Only align for at least a positive non-zero boundary. */
912
  if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
913
    return;
914
 
915
  /* We need to decide which NOP sequence to use for 32bit and
916
     64bit. When -mtune= is used:
917
 
918
     1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
919
     PROCESSOR_GENERIC32, f32_patt will be used.
920
     2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
921
     PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
922
     alt_long_patt will be used.
923
     3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
924
     PROCESSOR_AMDFAM10, alt_short_patt will be used.
925
 
926
     When -mtune= isn't used, alt_long_patt will be used if
927
     cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
928
     be used.
929
 
930
     When -march= or .arch is used, we can't use anything beyond
931
     cpu_arch_isa_flags.   */
932
 
933
  if (flag_code == CODE_16BIT)
934
    {
935
      if (count > 8)
936
        {
937
          memcpy (fragP->fr_literal + fragP->fr_fix,
938
                  jump_31, count);
939
          /* Adjust jump offset.  */
940
          fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
941
        }
942
      else
943
        memcpy (fragP->fr_literal + fragP->fr_fix,
944
                f16_patt[count - 1], count);
945
    }
946
  else
947
    {
948
      const char *const *patt = NULL;
949
 
950
      if (cpu_arch_isa == PROCESSOR_UNKNOWN)
951
        {
952
          /* PROCESSOR_UNKNOWN means that all ISAs may be used.  */
953
          switch (cpu_arch_tune)
954
            {
955
            case PROCESSOR_UNKNOWN:
956
              /* We use cpu_arch_isa_flags to check if we SHOULD
957
                 optimize for Cpu686.  */
958
              if (cpu_arch_isa_flags.bitfield.cpui686)
959
                patt = alt_long_patt;
960
              else
961
                patt = f32_patt;
962
              break;
963
            case PROCESSOR_PENTIUMPRO:
964
            case PROCESSOR_PENTIUM4:
965
            case PROCESSOR_NOCONA:
966
            case PROCESSOR_CORE:
967
            case PROCESSOR_CORE2:
968
            case PROCESSOR_GENERIC64:
969
              patt = alt_long_patt;
970
              break;
971
            case PROCESSOR_K6:
972
            case PROCESSOR_ATHLON:
973
            case PROCESSOR_K8:
974
            case PROCESSOR_AMDFAM10:
975
              patt = alt_short_patt;
976
              break;
977
            case PROCESSOR_I386:
978
            case PROCESSOR_I486:
979
            case PROCESSOR_PENTIUM:
980
            case PROCESSOR_GENERIC32:
981
              patt = f32_patt;
982
              break;
983
            }
984
        }
985
      else
986
        {
987
          switch (cpu_arch_tune)
988
            {
989
            case PROCESSOR_UNKNOWN:
990
              /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
991
                 PROCESSOR_UNKNOWN.  */
992
              abort ();
993
              break;
994
 
995
            case PROCESSOR_I386:
996
            case PROCESSOR_I486:
997
            case PROCESSOR_PENTIUM:
998
            case PROCESSOR_K6:
999
            case PROCESSOR_ATHLON:
1000
            case PROCESSOR_K8:
1001
            case PROCESSOR_AMDFAM10:
1002
            case PROCESSOR_GENERIC32:
1003
              /* We use cpu_arch_isa_flags to check if we CAN optimize
1004
                 for Cpu686.  */
1005
              if (cpu_arch_isa_flags.bitfield.cpui686)
1006
                patt = alt_short_patt;
1007
              else
1008
                patt = f32_patt;
1009
              break;
1010
            case PROCESSOR_PENTIUMPRO:
1011
            case PROCESSOR_PENTIUM4:
1012
            case PROCESSOR_NOCONA:
1013
            case PROCESSOR_CORE:
1014
            case PROCESSOR_CORE2:
1015
              if (cpu_arch_isa_flags.bitfield.cpui686)
1016
                patt = alt_long_patt;
1017
              else
1018
                patt = f32_patt;
1019
              break;
1020
            case PROCESSOR_GENERIC64:
1021
              patt = alt_long_patt;
1022
              break;
1023
            }
1024
        }
1025
 
1026
      if (patt == f32_patt)
1027
        {
1028
          /* If the padding is less than 15 bytes, we use the normal
1029
             ones.  Otherwise, we use a jump instruction and adjust
1030
             its offset.  */
1031
          if (count < 15)
1032
            memcpy (fragP->fr_literal + fragP->fr_fix,
1033
                    patt[count - 1], count);
1034
          else
1035
            {
1036
              memcpy (fragP->fr_literal + fragP->fr_fix,
1037
                      jump_31, count);
1038
              /* Adjust jump offset.  */
1039
              fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1040
            }
1041
        }
1042
      else
1043
        {
1044
          /* Maximum length of an instruction is 15 byte.  If the
1045
             padding is greater than 15 bytes and we don't use jump,
1046
             we have to break it into smaller pieces.  */
1047
          int padding = count;
1048
          while (padding > 15)
1049
            {
1050
              padding -= 15;
1051
              memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1052
                      patt [14], 15);
1053
            }
1054
 
1055
          if (padding)
1056
            memcpy (fragP->fr_literal + fragP->fr_fix,
1057
                    patt [padding - 1], padding);
1058
        }
1059
    }
1060
  fragP->fr_var = count;
1061
}
1062
 
1063
static INLINE int
1064
operand_type_all_zero (const union i386_operand_type *x)
1065
{
1066
  switch (ARRAY_SIZE(x->array))
1067
    {
1068
    case 3:
1069
      if (x->array[2])
1070
        return 0;
1071
    case 2:
1072
      if (x->array[1])
1073
        return 0;
1074
    case 1:
1075
      return !x->array[0];
1076
    default:
1077
      abort ();
1078
    }
1079
}
1080
 
1081
static INLINE void
1082
operand_type_set (union i386_operand_type *x, unsigned int v)
1083
{
1084
  switch (ARRAY_SIZE(x->array))
1085
    {
1086
    case 3:
1087
      x->array[2] = v;
1088
    case 2:
1089
      x->array[1] = v;
1090
    case 1:
1091
      x->array[0] = v;
1092
      break;
1093
    default:
1094
      abort ();
1095
    }
1096
}
1097
 
1098
static INLINE int
1099
operand_type_equal (const union i386_operand_type *x,
1100
                    const union i386_operand_type *y)
1101
{
1102
  switch (ARRAY_SIZE(x->array))
1103
    {
1104
    case 3:
1105
      if (x->array[2] != y->array[2])
1106
        return 0;
1107
    case 2:
1108
      if (x->array[1] != y->array[1])
1109
        return 0;
1110
    case 1:
1111
      return x->array[0] == y->array[0];
1112
      break;
1113
    default:
1114
      abort ();
1115
    }
1116
}
1117
 
1118
static INLINE int
1119
cpu_flags_all_zero (const union i386_cpu_flags *x)
1120
{
1121
  switch (ARRAY_SIZE(x->array))
1122
    {
1123
    case 3:
1124
      if (x->array[2])
1125
        return 0;
1126
    case 2:
1127
      if (x->array[1])
1128
        return 0;
1129
    case 1:
1130
      return !x->array[0];
1131
    default:
1132
      abort ();
1133
    }
1134
}
1135
 
1136
static INLINE void
1137
cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1138
{
1139
  switch (ARRAY_SIZE(x->array))
1140
    {
1141
    case 3:
1142
      x->array[2] = v;
1143
    case 2:
1144
      x->array[1] = v;
1145
    case 1:
1146
      x->array[0] = v;
1147
      break;
1148
    default:
1149
      abort ();
1150
    }
1151
}
1152
 
1153
static INLINE int
1154
cpu_flags_equal (const union i386_cpu_flags *x,
1155
                 const union i386_cpu_flags *y)
1156
{
1157
  switch (ARRAY_SIZE(x->array))
1158
    {
1159
    case 3:
1160
      if (x->array[2] != y->array[2])
1161
        return 0;
1162
    case 2:
1163
      if (x->array[1] != y->array[1])
1164
        return 0;
1165
    case 1:
1166
      return x->array[0] == y->array[0];
1167
      break;
1168
    default:
1169
      abort ();
1170
    }
1171
}
1172
 
1173
static INLINE int
1174
cpu_flags_check_cpu64 (i386_cpu_flags f)
1175
{
1176
  return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1177
           || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1178
}
1179
 
1180
static INLINE i386_cpu_flags
1181
cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1182
{
1183
  switch (ARRAY_SIZE (x.array))
1184
    {
1185
    case 3:
1186
      x.array [2] &= y.array [2];
1187
    case 2:
1188
      x.array [1] &= y.array [1];
1189
    case 1:
1190
      x.array [0] &= y.array [0];
1191
      break;
1192
    default:
1193
      abort ();
1194
    }
1195
  return x;
1196
}
1197
 
1198
static INLINE i386_cpu_flags
1199
cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1200
{
1201
  switch (ARRAY_SIZE (x.array))
1202
    {
1203
    case 3:
1204
      x.array [2] |= y.array [2];
1205
    case 2:
1206
      x.array [1] |= y.array [1];
1207
    case 1:
1208
      x.array [0] |= y.array [0];
1209
      break;
1210
    default:
1211
      abort ();
1212
    }
1213
  return x;
1214
}
1215
 
1216
#define CPU_FLAGS_ARCH_MATCH            0x1
1217
#define CPU_FLAGS_64BIT_MATCH           0x2
1218
 
1219
#define CPU_FLAGS_32BIT_MATCH           CPU_FLAGS_ARCH_MATCH 
1220
#define CPU_FLAGS_PERFECT_MATCH \
1221
  (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1222
 
1223
/* Return CPU flags match bits. */
1224
 
1225
static int
1226
cpu_flags_match (const template *t)
1227
{
1228
  i386_cpu_flags x = t->cpu_flags;
1229
  int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1230
 
1231
  x.bitfield.cpu64 = 0;
1232
  x.bitfield.cpuno64 = 0;
1233
 
1234
  if (cpu_flags_all_zero (&x))
1235
    {
1236
      /* This instruction is available on all archs.  */
1237
      match |= CPU_FLAGS_32BIT_MATCH;
1238
    }
1239
  else
1240
    {
1241
      /* This instruction is available only on some archs.  */
1242
      i386_cpu_flags cpu = cpu_arch_flags;
1243
 
1244
      cpu.bitfield.cpu64 = 0;
1245
      cpu.bitfield.cpuno64 = 0;
1246
      cpu = cpu_flags_and (x, cpu);
1247
      if (!cpu_flags_all_zero (&cpu))
1248
        {
1249
          /* Check SSE2AVX  */
1250
          if (!t->opcode_modifier.sse2avx || sse2avx)
1251
            match |= CPU_FLAGS_32BIT_MATCH;
1252
        }
1253
    }
1254
  return match;
1255
}
1256
 
1257
static INLINE i386_operand_type
1258
operand_type_and (i386_operand_type x, i386_operand_type y)
1259
{
1260
  switch (ARRAY_SIZE (x.array))
1261
    {
1262
    case 3:
1263
      x.array [2] &= y.array [2];
1264
    case 2:
1265
      x.array [1] &= y.array [1];
1266
    case 1:
1267
      x.array [0] &= y.array [0];
1268
      break;
1269
    default:
1270
      abort ();
1271
    }
1272
  return x;
1273
}
1274
 
1275
static INLINE i386_operand_type
1276
operand_type_or (i386_operand_type x, i386_operand_type y)
1277
{
1278
  switch (ARRAY_SIZE (x.array))
1279
    {
1280
    case 3:
1281
      x.array [2] |= y.array [2];
1282
    case 2:
1283
      x.array [1] |= y.array [1];
1284
    case 1:
1285
      x.array [0] |= y.array [0];
1286
      break;
1287
    default:
1288
      abort ();
1289
    }
1290
  return x;
1291
}
1292
 
1293
static INLINE i386_operand_type
1294
operand_type_xor (i386_operand_type x, i386_operand_type y)
1295
{
1296
  switch (ARRAY_SIZE (x.array))
1297
    {
1298
    case 3:
1299
      x.array [2] ^= y.array [2];
1300
    case 2:
1301
      x.array [1] ^= y.array [1];
1302
    case 1:
1303
      x.array [0] ^= y.array [0];
1304
      break;
1305
    default:
1306
      abort ();
1307
    }
1308
  return x;
1309
}
1310
 
1311
static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1312
static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1313
static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1314
static const i386_operand_type inoutportreg
1315
  = OPERAND_TYPE_INOUTPORTREG;
1316
static const i386_operand_type reg16_inoutportreg
1317
  = OPERAND_TYPE_REG16_INOUTPORTREG;
1318
static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1319
static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1320
static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1321
static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1322
static const i386_operand_type anydisp
1323
  = OPERAND_TYPE_ANYDISP;
1324
static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1325
static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1326
static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1327
static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1328
static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1329
static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1330
static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1331
static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1332
static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1333
static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1334
static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1335
static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4;
1336
 
1337
enum operand_type
1338
{
1339
  reg,
1340
  imm,
1341
  disp,
1342
  anymem
1343
};
1344
 
1345
static INLINE int
1346
operand_type_check (i386_operand_type t, enum operand_type c)
1347
{
1348
  switch (c)
1349
    {
1350
    case reg:
1351
      return (t.bitfield.reg8
1352
              || t.bitfield.reg16
1353
              || t.bitfield.reg32
1354
              || t.bitfield.reg64);
1355
 
1356
    case imm:
1357
      return (t.bitfield.imm8
1358
              || t.bitfield.imm8s
1359
              || t.bitfield.imm16
1360
              || t.bitfield.imm32
1361
              || t.bitfield.imm32s
1362
              || t.bitfield.imm64);
1363
 
1364
    case disp:
1365
      return (t.bitfield.disp8
1366
              || t.bitfield.disp16
1367
              || t.bitfield.disp32
1368
              || t.bitfield.disp32s
1369
              || t.bitfield.disp64);
1370
 
1371
    case anymem:
1372
      return (t.bitfield.disp8
1373
              || t.bitfield.disp16
1374
              || t.bitfield.disp32
1375
              || t.bitfield.disp32s
1376
              || t.bitfield.disp64
1377
              || t.bitfield.baseindex);
1378
 
1379
    default:
1380
      abort ();
1381
    }
1382
}
1383
 
1384
/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1385
   operand J for instruction template T.  */
1386
 
1387
static INLINE int
1388
match_reg_size (const template *t, unsigned int j)
1389
{
1390
  return !((i.types[j].bitfield.byte
1391
            && !t->operand_types[j].bitfield.byte)
1392
           || (i.types[j].bitfield.word
1393
               && !t->operand_types[j].bitfield.word)
1394
           || (i.types[j].bitfield.dword
1395
               && !t->operand_types[j].bitfield.dword)
1396
           || (i.types[j].bitfield.qword
1397
               && !t->operand_types[j].bitfield.qword));
1398
}
1399
 
1400
/* Return 1 if there is no conflict in any size on operand J for
1401
   instruction template T.  */
1402
 
1403
static INLINE int
1404
match_mem_size (const template *t, unsigned int j)
1405
{
1406
  return (match_reg_size (t, j)
1407
          && !((i.types[j].bitfield.unspecified
1408
                && !t->operand_types[j].bitfield.unspecified)
1409
               || (i.types[j].bitfield.fword
1410
                   && !t->operand_types[j].bitfield.fword)
1411
               || (i.types[j].bitfield.tbyte
1412
                   && !t->operand_types[j].bitfield.tbyte)
1413
               || (i.types[j].bitfield.xmmword
1414
                   && !t->operand_types[j].bitfield.xmmword)
1415
               || (i.types[j].bitfield.ymmword
1416
                   && !t->operand_types[j].bitfield.ymmword)));
1417
}
1418
 
1419
/* Return 1 if there is no size conflict on any operands for
1420
   instruction template T.  */
1421
 
1422
static INLINE int
1423
operand_size_match (const template *t)
1424
{
1425
  unsigned int j;
1426
  int match = 1;
1427
 
1428
  /* Don't check jump instructions.  */
1429
  if (t->opcode_modifier.jump
1430
      || t->opcode_modifier.jumpbyte
1431
      || t->opcode_modifier.jumpdword
1432
      || t->opcode_modifier.jumpintersegment)
1433
    return match;
1434
 
1435
  /* Check memory and accumulator operand size.  */
1436
  for (j = 0; j < i.operands; j++)
1437
    {
1438
      if (t->operand_types[j].bitfield.anysize)
1439
        continue;
1440
 
1441
      if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1442
        {
1443
          match = 0;
1444
          break;
1445
        }
1446
 
1447
      if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1448
        {
1449
          match = 0;
1450
          break;
1451
        }
1452
    }
1453
 
1454
  if (match
1455
      || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1456
    return match;
1457
 
1458
  /* Check reverse.  */
1459
  assert (i.operands == 2);
1460
 
1461
  match = 1;
1462
  for (j = 0; j < 2; j++)
1463
    {
1464
      if (t->operand_types[j].bitfield.acc
1465
          && !match_reg_size (t, j ? 0 : 1))
1466
        {
1467
          match = 0;
1468
          break;
1469
        }
1470
 
1471
      if (i.types[j].bitfield.mem
1472
          && !match_mem_size (t, j ? 0 : 1))
1473
        {
1474
          match = 0;
1475
          break;
1476
        }
1477
    }
1478
 
1479
  return match;
1480
}
1481
 
1482
static INLINE int
1483
operand_type_match (i386_operand_type overlap,
1484
                    i386_operand_type given)
1485
{
1486
  i386_operand_type temp = overlap;
1487
 
1488
  temp.bitfield.jumpabsolute = 0;
1489
  temp.bitfield.unspecified = 0;
1490
  temp.bitfield.byte = 0;
1491
  temp.bitfield.word = 0;
1492
  temp.bitfield.dword = 0;
1493
  temp.bitfield.fword = 0;
1494
  temp.bitfield.qword = 0;
1495
  temp.bitfield.tbyte = 0;
1496
  temp.bitfield.xmmword = 0;
1497
  temp.bitfield.ymmword = 0;
1498
  if (operand_type_all_zero (&temp))
1499
    return 0;
1500
 
1501
  return (given.bitfield.baseindex == overlap.bitfield.baseindex
1502
          && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1503
}
1504
 
1505
/* If given types g0 and g1 are registers they must be of the same type
1506
   unless the expected operand type register overlap is null.
1507
   Note that Acc in a template matches every size of reg.  */
1508
 
1509
static INLINE int
1510
operand_type_register_match (i386_operand_type m0,
1511
                             i386_operand_type g0,
1512
                             i386_operand_type t0,
1513
                             i386_operand_type m1,
1514
                             i386_operand_type g1,
1515
                             i386_operand_type t1)
1516
{
1517
  if (!operand_type_check (g0, reg))
1518
    return 1;
1519
 
1520
  if (!operand_type_check (g1, reg))
1521
    return 1;
1522
 
1523
  if (g0.bitfield.reg8 == g1.bitfield.reg8
1524
      && g0.bitfield.reg16 == g1.bitfield.reg16
1525
      && g0.bitfield.reg32 == g1.bitfield.reg32
1526
      && g0.bitfield.reg64 == g1.bitfield.reg64)
1527
    return 1;
1528
 
1529
  if (m0.bitfield.acc)
1530
    {
1531
      t0.bitfield.reg8 = 1;
1532
      t0.bitfield.reg16 = 1;
1533
      t0.bitfield.reg32 = 1;
1534
      t0.bitfield.reg64 = 1;
1535
    }
1536
 
1537
  if (m1.bitfield.acc)
1538
    {
1539
      t1.bitfield.reg8 = 1;
1540
      t1.bitfield.reg16 = 1;
1541
      t1.bitfield.reg32 = 1;
1542
      t1.bitfield.reg64 = 1;
1543
    }
1544
 
1545
  return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1546
          && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1547
          && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1548
          && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1549
}
1550
 
1551
static INLINE unsigned int
1552
mode_from_disp_size (i386_operand_type t)
1553
{
1554
  if (t.bitfield.disp8)
1555
    return 1;
1556
  else if (t.bitfield.disp16
1557
           || t.bitfield.disp32
1558
           || t.bitfield.disp32s)
1559
    return 2;
1560
  else
1561
    return 0;
1562
}
1563
 
1564
static INLINE int
1565
fits_in_signed_byte (offsetT num)
1566
{
1567
  return (num >= -128) && (num <= 127);
1568
}
1569
 
1570
static INLINE int
1571
fits_in_unsigned_byte (offsetT num)
1572
{
1573
  return (num & 0xff) == num;
1574
}
1575
 
1576
static INLINE int
1577
fits_in_unsigned_word (offsetT num)
1578
{
1579
  return (num & 0xffff) == num;
1580
}
1581
 
1582
static INLINE int
1583
fits_in_signed_word (offsetT num)
1584
{
1585
  return (-32768 <= num) && (num <= 32767);
1586
}
1587
 
1588
static INLINE int
1589
fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1590
{
1591
#ifndef BFD64
1592
  return 1;
1593
#else
1594
  return (!(((offsetT) -1 << 31) & num)
1595
          || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1596
#endif
1597
}                               /* fits_in_signed_long() */
1598
 
1599
static INLINE int
1600
fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1601
{
1602
#ifndef BFD64
1603
  return 1;
1604
#else
1605
  return (num & (((offsetT) 2 << 31) - 1)) == num;
1606
#endif
1607
}                               /* fits_in_unsigned_long() */
1608
 
1609
static INLINE int
1610
fits_in_imm4 (offsetT num)
1611
{
1612
  return (num & 0xf) == num;
1613
}
1614
 
1615
static i386_operand_type
1616
smallest_imm_type (offsetT num)
1617
{
1618
  i386_operand_type t;
1619
 
1620
  operand_type_set (&t, 0);
1621
  t.bitfield.imm64 = 1;
1622
 
1623
  if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1624
    {
1625
      /* This code is disabled on the 486 because all the Imm1 forms
1626
         in the opcode table are slower on the i486.  They're the
1627
         versions with the implicitly specified single-position
1628
         displacement, which has another syntax if you really want to
1629
         use that form.  */
1630
      t.bitfield.imm1 = 1;
1631
      t.bitfield.imm8 = 1;
1632
      t.bitfield.imm8s = 1;
1633
      t.bitfield.imm16 = 1;
1634
      t.bitfield.imm32 = 1;
1635
      t.bitfield.imm32s = 1;
1636
    }
1637
  else if (fits_in_signed_byte (num))
1638
    {
1639
      t.bitfield.imm8 = 1;
1640
      t.bitfield.imm8s = 1;
1641
      t.bitfield.imm16 = 1;
1642
      t.bitfield.imm32 = 1;
1643
      t.bitfield.imm32s = 1;
1644
    }
1645
  else if (fits_in_unsigned_byte (num))
1646
    {
1647
      t.bitfield.imm8 = 1;
1648
      t.bitfield.imm16 = 1;
1649
      t.bitfield.imm32 = 1;
1650
      t.bitfield.imm32s = 1;
1651
    }
1652
  else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1653
    {
1654
      t.bitfield.imm16 = 1;
1655
      t.bitfield.imm32 = 1;
1656
      t.bitfield.imm32s = 1;
1657
    }
1658
  else if (fits_in_signed_long (num))
1659
    {
1660
      t.bitfield.imm32 = 1;
1661
      t.bitfield.imm32s = 1;
1662
    }
1663
  else if (fits_in_unsigned_long (num))
1664
    t.bitfield.imm32 = 1;
1665
 
1666
  return t;
1667
}
1668
 
1669
static offsetT
1670
offset_in_range (offsetT val, int size)
1671
{
1672
  addressT mask;
1673
 
1674
  switch (size)
1675
    {
1676
    case 1: mask = ((addressT) 1 <<  8) - 1; break;
1677
    case 2: mask = ((addressT) 1 << 16) - 1; break;
1678
    case 4: mask = ((addressT) 2 << 31) - 1; break;
1679
#ifdef BFD64
1680
    case 8: mask = ((addressT) 2 << 63) - 1; break;
1681
#endif
1682
    default: abort ();
1683
    }
1684
 
1685
  /* If BFD64, sign extend val.  */
1686
  if (!use_rela_relocations)
1687
    if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1688
      val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1689
 
1690
  if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1691
    {
1692
      char buf1[40], buf2[40];
1693
 
1694
      sprint_value (buf1, val);
1695
      sprint_value (buf2, val & mask);
1696
      as_warn (_("%s shortened to %s"), buf1, buf2);
1697
    }
1698
  return val & mask;
1699
}
1700
 
1701
/* Returns 0 if attempting to add a prefix where one from the same
1702
   class already exists, 1 if non rep/repne added, 2 if rep/repne
1703
   added.  */
1704
static int
1705
add_prefix (unsigned int prefix)
1706
{
1707
  int ret = 1;
1708
  unsigned int q;
1709
 
1710
  if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1711
      && flag_code == CODE_64BIT)
1712
    {
1713
      if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1714
          || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1715
              && (prefix & (REX_R | REX_X | REX_B))))
1716
        ret = 0;
1717
      q = REX_PREFIX;
1718
    }
1719
  else
1720
    {
1721
      switch (prefix)
1722
        {
1723
        default:
1724
          abort ();
1725
 
1726
        case CS_PREFIX_OPCODE:
1727
        case DS_PREFIX_OPCODE:
1728
        case ES_PREFIX_OPCODE:
1729
        case FS_PREFIX_OPCODE:
1730
        case GS_PREFIX_OPCODE:
1731
        case SS_PREFIX_OPCODE:
1732
          q = SEG_PREFIX;
1733
          break;
1734
 
1735
        case REPNE_PREFIX_OPCODE:
1736
        case REPE_PREFIX_OPCODE:
1737
          ret = 2;
1738
          /* fall thru */
1739
        case LOCK_PREFIX_OPCODE:
1740
          q = LOCKREP_PREFIX;
1741
          break;
1742
 
1743
        case FWAIT_OPCODE:
1744
          q = WAIT_PREFIX;
1745
          break;
1746
 
1747
        case ADDR_PREFIX_OPCODE:
1748
          q = ADDR_PREFIX;
1749
          break;
1750
 
1751
        case DATA_PREFIX_OPCODE:
1752
          q = DATA_PREFIX;
1753
          break;
1754
        }
1755
      if (i.prefix[q] != 0)
1756
        ret = 0;
1757
    }
1758
 
1759
  if (ret)
1760
    {
1761
      if (!i.prefix[q])
1762
        ++i.prefixes;
1763
      i.prefix[q] |= prefix;
1764
    }
1765
  else
1766
    as_bad (_("same type of prefix used twice"));
1767
 
1768
  return ret;
1769
}
1770
 
1771
static void
1772
set_code_flag (int value)
1773
{
1774
  flag_code = value;
1775
  if (flag_code == CODE_64BIT)
1776
    {
1777
      cpu_arch_flags.bitfield.cpu64 = 1;
1778
      cpu_arch_flags.bitfield.cpuno64 = 0;
1779
    }
1780
  else
1781
    {
1782
      cpu_arch_flags.bitfield.cpu64 = 0;
1783
      cpu_arch_flags.bitfield.cpuno64 = 1;
1784
    }
1785
  if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1786
    {
1787
      as_bad (_("64bit mode not supported on this CPU."));
1788
    }
1789
  if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1790
    {
1791
      as_bad (_("32bit mode not supported on this CPU."));
1792
    }
1793
  stackop_size = '\0';
1794
}
1795
 
1796
static void
1797
set_16bit_gcc_code_flag (int new_code_flag)
1798
{
1799
  flag_code = new_code_flag;
1800
  if (flag_code != CODE_16BIT)
1801
    abort ();
1802
  cpu_arch_flags.bitfield.cpu64 = 0;
1803
  cpu_arch_flags.bitfield.cpuno64 = 1;
1804
  stackop_size = LONG_MNEM_SUFFIX;
1805
}
1806
 
1807
static void
1808
set_intel_syntax (int syntax_flag)
1809
{
1810
  /* Find out if register prefixing is specified.  */
1811
  int ask_naked_reg = 0;
1812
 
1813
  SKIP_WHITESPACE ();
1814
  if (!is_end_of_line[(unsigned char) *input_line_pointer])
1815
    {
1816
      char *string = input_line_pointer;
1817
      int e = get_symbol_end ();
1818
 
1819
      if (strcmp (string, "prefix") == 0)
1820
        ask_naked_reg = 1;
1821
      else if (strcmp (string, "noprefix") == 0)
1822
        ask_naked_reg = -1;
1823
      else
1824
        as_bad (_("bad argument to syntax directive."));
1825
      *input_line_pointer = e;
1826
    }
1827
  demand_empty_rest_of_line ();
1828
 
1829
  intel_syntax = syntax_flag;
1830
 
1831
  if (ask_naked_reg == 0)
1832
    allow_naked_reg = (intel_syntax
1833
                       && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1834
  else
1835
    allow_naked_reg = (ask_naked_reg < 0);
1836
 
1837
  identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1838
  identifier_chars['$'] = intel_syntax ? '$' : 0;
1839
  register_prefix = allow_naked_reg ? "" : "%";
1840
}
1841
 
1842
static void
1843
set_intel_mnemonic (int mnemonic_flag)
1844
{
1845
  intel_mnemonic = mnemonic_flag;
1846
}
1847
 
1848
static void
1849
set_allow_index_reg (int flag)
1850
{
1851
  allow_index_reg = flag;
1852
}
1853
 
1854
static void
1855
set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1856
{
1857
  SKIP_WHITESPACE ();
1858
 
1859
  if (!is_end_of_line[(unsigned char) *input_line_pointer])
1860
    {
1861
      char *string = input_line_pointer;
1862
      int e = get_symbol_end ();
1863
      unsigned int i;
1864
      i386_cpu_flags flags;
1865
 
1866
      for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1867
        {
1868
          if (strcmp (string, cpu_arch[i].name) == 0)
1869
            {
1870
              if (*string != '.')
1871
                {
1872
                  cpu_arch_name = cpu_arch[i].name;
1873
                  cpu_sub_arch_name = NULL;
1874
                  cpu_arch_flags = cpu_arch[i].flags;
1875
                  if (flag_code == CODE_64BIT)
1876
                    {
1877
                      cpu_arch_flags.bitfield.cpu64 = 1;
1878
                      cpu_arch_flags.bitfield.cpuno64 = 0;
1879
                    }
1880
                  else
1881
                    {
1882
                      cpu_arch_flags.bitfield.cpu64 = 0;
1883
                      cpu_arch_flags.bitfield.cpuno64 = 1;
1884
                    }
1885
                  cpu_arch_isa = cpu_arch[i].type;
1886
                  cpu_arch_isa_flags = cpu_arch[i].flags;
1887
                  if (!cpu_arch_tune_set)
1888
                    {
1889
                      cpu_arch_tune = cpu_arch_isa;
1890
                      cpu_arch_tune_flags = cpu_arch_isa_flags;
1891
                    }
1892
                  break;
1893
                }
1894
 
1895
              flags = cpu_flags_or (cpu_arch_flags,
1896
                                    cpu_arch[i].flags);
1897
              if (!cpu_flags_equal (&flags, &cpu_arch_flags))
1898
                {
1899
                  if (cpu_sub_arch_name)
1900
                    {
1901
                      char *name = cpu_sub_arch_name;
1902
                      cpu_sub_arch_name = concat (name,
1903
                                                  cpu_arch[i].name,
1904
                                                  (const char *) NULL);
1905
                      free (name);
1906
                    }
1907
                  else
1908
                    cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
1909
                  cpu_arch_flags = flags;
1910
                }
1911
              *input_line_pointer = e;
1912
              demand_empty_rest_of_line ();
1913
              return;
1914
            }
1915
        }
1916
      if (i >= ARRAY_SIZE (cpu_arch))
1917
        as_bad (_("no such architecture: `%s'"), string);
1918
 
1919
      *input_line_pointer = e;
1920
    }
1921
  else
1922
    as_bad (_("missing cpu architecture"));
1923
 
1924
  no_cond_jump_promotion = 0;
1925
  if (*input_line_pointer == ','
1926
      && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1927
    {
1928
      char *string = ++input_line_pointer;
1929
      int e = get_symbol_end ();
1930
 
1931
      if (strcmp (string, "nojumps") == 0)
1932
        no_cond_jump_promotion = 1;
1933
      else if (strcmp (string, "jumps") == 0)
1934
        ;
1935
      else
1936
        as_bad (_("no such architecture modifier: `%s'"), string);
1937
 
1938
      *input_line_pointer = e;
1939
    }
1940
 
1941
  demand_empty_rest_of_line ();
1942
}
1943
 
1944
unsigned long
1945
i386_mach ()
1946
{
1947
  if (!strcmp (default_arch, "x86_64"))
1948
    return bfd_mach_x86_64;
1949
  else if (!strcmp (default_arch, "i386"))
1950
    return bfd_mach_i386_i386;
1951
  else
1952
    as_fatal (_("Unknown architecture"));
1953
}
1954
 
1955
void
1956
md_begin ()
1957
{
1958
  const char *hash_err;
1959
 
1960
  /* Initialize op_hash hash table.  */
1961
  op_hash = hash_new ();
1962
 
1963
  {
1964
    const template *optab;
1965
    templates *core_optab;
1966
 
1967
    /* Setup for loop.  */
1968
    optab = i386_optab;
1969
    core_optab = (templates *) xmalloc (sizeof (templates));
1970
    core_optab->start = optab;
1971
 
1972
    while (1)
1973
      {
1974
        ++optab;
1975
        if (optab->name == NULL
1976
            || strcmp (optab->name, (optab - 1)->name) != 0)
1977
          {
1978
            /* different name --> ship out current template list;
1979
               add to hash table; & begin anew.  */
1980
            core_optab->end = optab;
1981
            hash_err = hash_insert (op_hash,
1982
                                    (optab - 1)->name,
1983
                                    (PTR) core_optab);
1984
            if (hash_err)
1985
              {
1986
                as_fatal (_("Internal Error:  Can't hash %s: %s"),
1987
                          (optab - 1)->name,
1988
                          hash_err);
1989
              }
1990
            if (optab->name == NULL)
1991
              break;
1992
            core_optab = (templates *) xmalloc (sizeof (templates));
1993
            core_optab->start = optab;
1994
          }
1995
      }
1996
  }
1997
 
1998
  /* Initialize reg_hash hash table.  */
1999
  reg_hash = hash_new ();
2000
  {
2001
    const reg_entry *regtab;
2002
    unsigned int regtab_size = i386_regtab_size;
2003
 
2004
    for (regtab = i386_regtab; regtab_size--; regtab++)
2005
      {
2006
        hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
2007
        if (hash_err)
2008
          as_fatal (_("Internal Error:  Can't hash %s: %s"),
2009
                    regtab->reg_name,
2010
                    hash_err);
2011
      }
2012
  }
2013
 
2014
  /* Fill in lexical tables:  mnemonic_chars, operand_chars.  */
2015
  {
2016
    int c;
2017
    char *p;
2018
 
2019
    for (c = 0; c < 256; c++)
2020
      {
2021
        if (ISDIGIT (c))
2022
          {
2023
            digit_chars[c] = c;
2024
            mnemonic_chars[c] = c;
2025
            register_chars[c] = c;
2026
            operand_chars[c] = c;
2027
          }
2028
        else if (ISLOWER (c))
2029
          {
2030
            mnemonic_chars[c] = c;
2031
            register_chars[c] = c;
2032
            operand_chars[c] = c;
2033
          }
2034
        else if (ISUPPER (c))
2035
          {
2036
            mnemonic_chars[c] = TOLOWER (c);
2037
            register_chars[c] = mnemonic_chars[c];
2038
            operand_chars[c] = c;
2039
          }
2040
 
2041
        if (ISALPHA (c) || ISDIGIT (c))
2042
          identifier_chars[c] = c;
2043
        else if (c >= 128)
2044
          {
2045
            identifier_chars[c] = c;
2046
            operand_chars[c] = c;
2047
          }
2048
      }
2049
 
2050
#ifdef LEX_AT
2051
    identifier_chars['@'] = '@';
2052
#endif
2053
#ifdef LEX_QM
2054
    identifier_chars['?'] = '?';
2055
    operand_chars['?'] = '?';
2056
#endif
2057
    digit_chars['-'] = '-';
2058
    mnemonic_chars['_'] = '_';
2059
    mnemonic_chars['-'] = '-';
2060
    mnemonic_chars['.'] = '.';
2061
    identifier_chars['_'] = '_';
2062
    identifier_chars['.'] = '.';
2063
 
2064
    for (p = operand_special_chars; *p != '\0'; p++)
2065
      operand_chars[(unsigned char) *p] = *p;
2066
  }
2067
 
2068
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2069
  if (IS_ELF)
2070
    {
2071
      record_alignment (text_section, 2);
2072
      record_alignment (data_section, 2);
2073
      record_alignment (bss_section, 2);
2074
    }
2075
#endif
2076
 
2077
  if (flag_code == CODE_64BIT)
2078
    {
2079
      x86_dwarf2_return_column = 16;
2080
      x86_cie_data_alignment = -8;
2081
    }
2082
  else
2083
    {
2084
      x86_dwarf2_return_column = 8;
2085
      x86_cie_data_alignment = -4;
2086
    }
2087
}
2088
 
2089
void
2090
i386_print_statistics (FILE *file)
2091
{
2092
  hash_print_statistics (file, "i386 opcode", op_hash);
2093
  hash_print_statistics (file, "i386 register", reg_hash);
2094
}
2095
 
2096
#ifdef DEBUG386
2097
 
2098
/* Debugging routines for md_assemble.  */
2099
static void pte (template *);
2100
static void pt (i386_operand_type);
2101
static void pe (expressionS *);
2102
static void ps (symbolS *);
2103
 
2104
static void
2105
pi (char *line, i386_insn *x)
2106
{
2107
  unsigned int i;
2108
 
2109
  fprintf (stdout, "%s: template ", line);
2110
  pte (&x->tm);
2111
  fprintf (stdout, "  address: base %s  index %s  scale %x\n",
2112
           x->base_reg ? x->base_reg->reg_name : "none",
2113
           x->index_reg ? x->index_reg->reg_name : "none",
2114
           x->log2_scale_factor);
2115
  fprintf (stdout, "  modrm:  mode %x  reg %x  reg/mem %x\n",
2116
           x->rm.mode, x->rm.reg, x->rm.regmem);
2117
  fprintf (stdout, "  sib:  base %x  index %x  scale %x\n",
2118
           x->sib.base, x->sib.index, x->sib.scale);
2119
  fprintf (stdout, "  rex: 64bit %x  extX %x  extY %x  extZ %x\n",
2120
           (x->rex & REX_W) != 0,
2121
           (x->rex & REX_R) != 0,
2122
           (x->rex & REX_X) != 0,
2123
           (x->rex & REX_B) != 0);
2124
  fprintf (stdout, "  drex:  reg %d rex 0x%x\n",
2125
           x->drex.reg, x->drex.rex);
2126
  for (i = 0; i < x->operands; i++)
2127
    {
2128
      fprintf (stdout, "    #%d:  ", i + 1);
2129
      pt (x->types[i]);
2130
      fprintf (stdout, "\n");
2131
      if (x->types[i].bitfield.reg8
2132
          || x->types[i].bitfield.reg16
2133
          || x->types[i].bitfield.reg32
2134
          || x->types[i].bitfield.reg64
2135
          || x->types[i].bitfield.regmmx
2136
          || x->types[i].bitfield.regxmm
2137
          || x->types[i].bitfield.regymm
2138
          || x->types[i].bitfield.sreg2
2139
          || x->types[i].bitfield.sreg3
2140
          || x->types[i].bitfield.control
2141
          || x->types[i].bitfield.debug
2142
          || x->types[i].bitfield.test)
2143
        fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
2144
      if (operand_type_check (x->types[i], imm))
2145
        pe (x->op[i].imms);
2146
      if (operand_type_check (x->types[i], disp))
2147
        pe (x->op[i].disps);
2148
    }
2149
}
2150
 
2151
static void
2152
pte (template *t)
2153
{
2154
  unsigned int i;
2155
  fprintf (stdout, " %d operands ", t->operands);
2156
  fprintf (stdout, "opcode %x ", t->base_opcode);
2157
  if (t->extension_opcode != None)
2158
    fprintf (stdout, "ext %x ", t->extension_opcode);
2159
  if (t->opcode_modifier.d)
2160
    fprintf (stdout, "D");
2161
  if (t->opcode_modifier.w)
2162
    fprintf (stdout, "W");
2163
  fprintf (stdout, "\n");
2164
  for (i = 0; i < t->operands; i++)
2165
    {
2166
      fprintf (stdout, "    #%d type ", i + 1);
2167
      pt (t->operand_types[i]);
2168
      fprintf (stdout, "\n");
2169
    }
2170
}
2171
 
2172
static void
2173
pe (expressionS *e)
2174
{
2175
  fprintf (stdout, "    operation     %d\n", e->X_op);
2176
  fprintf (stdout, "    add_number    %ld (%lx)\n",
2177
           (long) e->X_add_number, (long) e->X_add_number);
2178
  if (e->X_add_symbol)
2179
    {
2180
      fprintf (stdout, "    add_symbol    ");
2181
      ps (e->X_add_symbol);
2182
      fprintf (stdout, "\n");
2183
    }
2184
  if (e->X_op_symbol)
2185
    {
2186
      fprintf (stdout, "    op_symbol    ");
2187
      ps (e->X_op_symbol);
2188
      fprintf (stdout, "\n");
2189
    }
2190
}
2191
 
2192
static void
2193
ps (symbolS *s)
2194
{
2195
  fprintf (stdout, "%s type %s%s",
2196
           S_GET_NAME (s),
2197
           S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2198
           segment_name (S_GET_SEGMENT (s)));
2199
}
2200
 
2201
static struct type_name
2202
  {
2203
    i386_operand_type mask;
2204
    const char *name;
2205
  }
2206
const type_names[] =
2207
{
2208
  { OPERAND_TYPE_REG8, "r8" },
2209
  { OPERAND_TYPE_REG16, "r16" },
2210
  { OPERAND_TYPE_REG32, "r32" },
2211
  { OPERAND_TYPE_REG64, "r64" },
2212
  { OPERAND_TYPE_IMM8, "i8" },
2213
  { OPERAND_TYPE_IMM8, "i8s" },
2214
  { OPERAND_TYPE_IMM16, "i16" },
2215
  { OPERAND_TYPE_IMM32, "i32" },
2216
  { OPERAND_TYPE_IMM32S, "i32s" },
2217
  { OPERAND_TYPE_IMM64, "i64" },
2218
  { OPERAND_TYPE_IMM1, "i1" },
2219
  { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2220
  { OPERAND_TYPE_DISP8, "d8" },
2221
  { OPERAND_TYPE_DISP16, "d16" },
2222
  { OPERAND_TYPE_DISP32, "d32" },
2223
  { OPERAND_TYPE_DISP32S, "d32s" },
2224
  { OPERAND_TYPE_DISP64, "d64" },
2225
  { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2226
  { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2227
  { OPERAND_TYPE_CONTROL, "control reg" },
2228
  { OPERAND_TYPE_TEST, "test reg" },
2229
  { OPERAND_TYPE_DEBUG, "debug reg" },
2230
  { OPERAND_TYPE_FLOATREG, "FReg" },
2231
  { OPERAND_TYPE_FLOATACC, "FAcc" },
2232
  { OPERAND_TYPE_SREG2, "SReg2" },
2233
  { OPERAND_TYPE_SREG3, "SReg3" },
2234
  { OPERAND_TYPE_ACC, "Acc" },
2235
  { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2236
  { OPERAND_TYPE_REGMMX, "rMMX" },
2237
  { OPERAND_TYPE_REGXMM, "rXMM" },
2238
  { OPERAND_TYPE_ESSEG, "es" },
2239
  { OPERAND_TYPE_VEX_IMM4, "VEX i4" },
2240
};
2241
 
2242
static void
2243
pt (i386_operand_type t)
2244
{
2245
  unsigned int j;
2246
  i386_operand_type a;
2247
 
2248
  for (j = 0; j < ARRAY_SIZE (type_names); j++)
2249
    {
2250
      a = operand_type_and (t, type_names[j].mask);
2251
      if (!UINTS_ALL_ZERO (a))
2252
        fprintf (stdout, "%s, ",  type_names[j].name);
2253
    }
2254
  fflush (stdout);
2255
}
2256
 
2257
#endif /* DEBUG386 */
2258
 
2259
static bfd_reloc_code_real_type
2260
reloc (unsigned int size,
2261
       int pcrel,
2262
       int sign,
2263
       bfd_reloc_code_real_type other)
2264
{
2265
  if (other != NO_RELOC)
2266
    {
2267
      reloc_howto_type *reloc;
2268
 
2269
      if (size == 8)
2270
        switch (other)
2271
          {
2272
          case BFD_RELOC_X86_64_GOT32:
2273
            return BFD_RELOC_X86_64_GOT64;
2274
            break;
2275
          case BFD_RELOC_X86_64_PLTOFF64:
2276
            return BFD_RELOC_X86_64_PLTOFF64;
2277
            break;
2278
          case BFD_RELOC_X86_64_GOTPC32:
2279
            other = BFD_RELOC_X86_64_GOTPC64;
2280
            break;
2281
          case BFD_RELOC_X86_64_GOTPCREL:
2282
            other = BFD_RELOC_X86_64_GOTPCREL64;
2283
            break;
2284
          case BFD_RELOC_X86_64_TPOFF32:
2285
            other = BFD_RELOC_X86_64_TPOFF64;
2286
            break;
2287
          case BFD_RELOC_X86_64_DTPOFF32:
2288
            other = BFD_RELOC_X86_64_DTPOFF64;
2289
            break;
2290
          default:
2291
            break;
2292
          }
2293
 
2294
      /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless.  */
2295
      if (size == 4 && flag_code != CODE_64BIT)
2296
        sign = -1;
2297
 
2298
      reloc = bfd_reloc_type_lookup (stdoutput, other);
2299
      if (!reloc)
2300
        as_bad (_("unknown relocation (%u)"), other);
2301
      else if (size != bfd_get_reloc_size (reloc))
2302
        as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2303
                bfd_get_reloc_size (reloc),
2304
                size);
2305
      else if (pcrel && !reloc->pc_relative)
2306
        as_bad (_("non-pc-relative relocation for pc-relative field"));
2307
      else if ((reloc->complain_on_overflow == complain_overflow_signed
2308
                && !sign)
2309
               || (reloc->complain_on_overflow == complain_overflow_unsigned
2310
                   && sign > 0))
2311
        as_bad (_("relocated field and relocation type differ in signedness"));
2312
      else
2313
        return other;
2314
      return NO_RELOC;
2315
    }
2316
 
2317
  if (pcrel)
2318
    {
2319
      if (!sign)
2320
        as_bad (_("there are no unsigned pc-relative relocations"));
2321
      switch (size)
2322
        {
2323
        case 1: return BFD_RELOC_8_PCREL;
2324
        case 2: return BFD_RELOC_16_PCREL;
2325
        case 4: return BFD_RELOC_32_PCREL;
2326
        case 8: return BFD_RELOC_64_PCREL;
2327
        }
2328
      as_bad (_("cannot do %u byte pc-relative relocation"), size);
2329
    }
2330
  else
2331
    {
2332
      if (sign > 0)
2333
        switch (size)
2334
          {
2335
          case 4: return BFD_RELOC_X86_64_32S;
2336
          }
2337
      else
2338
        switch (size)
2339
          {
2340
          case 1: return BFD_RELOC_8;
2341
          case 2: return BFD_RELOC_16;
2342
          case 4: return BFD_RELOC_32;
2343
          case 8: return BFD_RELOC_64;
2344
          }
2345
      as_bad (_("cannot do %s %u byte relocation"),
2346
              sign > 0 ? "signed" : "unsigned", size);
2347
    }
2348
 
2349
  abort ();
2350
  return BFD_RELOC_NONE;
2351
}
2352
 
2353
/* Here we decide which fixups can be adjusted to make them relative to
2354
   the beginning of the section instead of the symbol.  Basically we need
2355
   to make sure that the dynamic relocations are done correctly, so in
2356
   some cases we force the original symbol to be used.  */
2357
 
2358
int
2359
tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2360
{
2361
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2362
  if (!IS_ELF)
2363
    return 1;
2364
 
2365
  /* Don't adjust pc-relative references to merge sections in 64-bit
2366
     mode.  */
2367
  if (use_rela_relocations
2368
      && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2369
      && fixP->fx_pcrel)
2370
    return 0;
2371
 
2372
  /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2373
     and changed later by validate_fix.  */
2374
  if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2375
      && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2376
    return 0;
2377
 
2378
  /* adjust_reloc_syms doesn't know about the GOT.  */
2379
  if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2380
      || fixP->fx_r_type == BFD_RELOC_386_PLT32
2381
      || fixP->fx_r_type == BFD_RELOC_386_GOT32
2382
      || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2383
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2384
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2385
      || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2386
      || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2387
      || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2388
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2389
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2390
      || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2391
      || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2392
      || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2393
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2394
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2395
      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2396
      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2397
      || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2398
      || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2399
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2400
      || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2401
      || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2402
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2403
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2404
      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2405
      || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2406
      || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2407
    return 0;
2408
#endif
2409
  return 1;
2410
}
2411
 
2412
static int
2413
intel_float_operand (const char *mnemonic)
2414
{
2415
  /* Note that the value returned is meaningful only for opcodes with (memory)
2416
     operands, hence the code here is free to improperly handle opcodes that
2417
     have no operands (for better performance and smaller code). */
2418
 
2419
  if (mnemonic[0] != 'f')
2420
    return 0; /* non-math */
2421
 
2422
  switch (mnemonic[1])
2423
    {
2424
    /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2425
       the fs segment override prefix not currently handled because no
2426
       call path can make opcodes without operands get here */
2427
    case 'i':
2428
      return 2 /* integer op */;
2429
    case 'l':
2430
      if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2431
        return 3; /* fldcw/fldenv */
2432
      break;
2433
    case 'n':
2434
      if (mnemonic[2] != 'o' /* fnop */)
2435
        return 3; /* non-waiting control op */
2436
      break;
2437
    case 'r':
2438
      if (mnemonic[2] == 's')
2439
        return 3; /* frstor/frstpm */
2440
      break;
2441
    case 's':
2442
      if (mnemonic[2] == 'a')
2443
        return 3; /* fsave */
2444
      if (mnemonic[2] == 't')
2445
        {
2446
          switch (mnemonic[3])
2447
            {
2448
            case 'c': /* fstcw */
2449
            case 'd': /* fstdw */
2450
            case 'e': /* fstenv */
2451
            case 's': /* fsts[gw] */
2452
              return 3;
2453
            }
2454
        }
2455
      break;
2456
    case 'x':
2457
      if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2458
        return 0; /* fxsave/fxrstor are not really math ops */
2459
      break;
2460
    }
2461
 
2462
  return 1;
2463
}
2464
 
2465
/* Build the VEX prefix.  */
2466
 
2467
static void
2468
build_vex_prefix (void)
2469
{
2470
  unsigned int register_specifier;
2471
  unsigned int implied_prefix;
2472
  unsigned int vector_length;
2473
 
2474
  /* Check register specifier.  */
2475
  if (i.vex.register_specifier)
2476
    {
2477
      register_specifier = i.vex.register_specifier->reg_num;
2478
      if ((i.vex.register_specifier->reg_flags & RegRex))
2479
        register_specifier += 8;
2480
      register_specifier = ~register_specifier & 0xf;
2481
    }
2482
  else
2483
    register_specifier = 0xf;
2484
 
2485
  vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2486
 
2487
  switch ((i.tm.base_opcode >> 8) & 0xff)
2488
    {
2489
    case 0:
2490
      implied_prefix = 0;
2491
      break;
2492
    case DATA_PREFIX_OPCODE:
2493
      implied_prefix = 1;
2494
      break;
2495
    case REPE_PREFIX_OPCODE:
2496
      implied_prefix = 2;
2497
      break;
2498
    case REPNE_PREFIX_OPCODE:
2499
      implied_prefix = 3;
2500
      break;
2501
    default:
2502
      abort ();
2503
    }
2504
 
2505
  /* Use 2-byte VEX prefix if possible.  */
2506
  if (i.tm.opcode_modifier.vex0f
2507
      && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2508
    {
2509
      /* 2-byte VEX prefix.  */
2510
      unsigned int r;
2511
 
2512
      i.vex.length = 2;
2513
      i.vex.bytes[0] = 0xc5;
2514
 
2515
      /* Check the REX.R bit.  */
2516
      r = (i.rex & REX_R) ? 0 : 1;
2517
      i.vex.bytes[1] = (r << 7
2518
                        | register_specifier << 3
2519
                        | vector_length << 2
2520
                        | implied_prefix);
2521
    }
2522
  else
2523
    {
2524
      /* 3-byte VEX prefix.  */
2525
      unsigned int m, w;
2526
 
2527
      if (i.tm.opcode_modifier.vex0f)
2528
        m = 0x1;
2529
      else if (i.tm.opcode_modifier.vex0f38)
2530
        m = 0x2;
2531
      else if (i.tm.opcode_modifier.vex0f3a)
2532
        m = 0x3;
2533
      else
2534
        abort ();
2535
 
2536
      i.vex.length = 3;
2537
      i.vex.bytes[0] = 0xc4;
2538
 
2539
      /* The high 3 bits of the second VEX byte are 1's compliment
2540
         of RXB bits from REX.  */
2541
      i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2542
 
2543
      /* Check the REX.W bit.  */
2544
      w = (i.rex & REX_W) ? 1 : 0;
2545
      if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2546
        {
2547
          if (w)
2548
            abort ();
2549
 
2550
          if (i.tm.opcode_modifier.vexw1)
2551
            w = 1;
2552
        }
2553
 
2554
      i.vex.bytes[2] = (w << 7
2555
                        | register_specifier << 3
2556
                        | vector_length << 2
2557
                        | implied_prefix);
2558
    }
2559
}
2560
 
2561
static void
2562
process_immext (void)
2563
{
2564
  expressionS *exp;
2565
 
2566
  if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2567
    {
2568
      /* SSE3 Instructions have the fixed operands with an opcode
2569
         suffix which is coded in the same place as an 8-bit immediate
2570
         field would be.  Here we check those operands and remove them
2571
         afterwards.  */
2572
      unsigned int x;
2573
 
2574
      for (x = 0; x < i.operands; x++)
2575
        if (i.op[x].regs->reg_num != x)
2576
          as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2577
                  register_prefix, i.op[x].regs->reg_name, x + 1,
2578
                  i.tm.name);
2579
 
2580
      i.operands = 0;
2581
    }
2582
 
2583
  /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2584
     which is coded in the same place as an 8-bit immediate field
2585
     would be.  Here we fake an 8-bit immediate operand from the
2586
     opcode suffix stored in tm.extension_opcode.
2587
 
2588
     SSE5 and AVX instructions also use this encoding, for some of
2589
     3 argument instructions.  */
2590
 
2591
  assert (i.imm_operands == 0
2592
          && (i.operands <= 2
2593
              || (i.tm.cpu_flags.bitfield.cpusse5
2594
                  && i.operands <= 3)
2595
              || (i.tm.opcode_modifier.vex
2596
                  && i.operands <= 4)));
2597
 
2598
  exp = &im_expressions[i.imm_operands++];
2599
  i.op[i.operands].imms = exp;
2600
  i.types[i.operands] = imm8;
2601
  i.operands++;
2602
  exp->X_op = O_constant;
2603
  exp->X_add_number = i.tm.extension_opcode;
2604
  i.tm.extension_opcode = None;
2605
}
2606
 
2607
/* This is the guts of the machine-dependent assembler.  LINE points to a
2608
   machine dependent instruction.  This function is supposed to emit
2609
   the frags/bytes it assembles to.  */
2610
 
2611
void
2612
md_assemble (char *line)
2613
{
2614
  unsigned int j;
2615
  char mnemonic[MAX_MNEM_SIZE];
2616
 
2617
  /* Initialize globals.  */
2618
  memset (&i, '\0', sizeof (i));
2619
  for (j = 0; j < MAX_OPERANDS; j++)
2620
    i.reloc[j] = NO_RELOC;
2621
  memset (disp_expressions, '\0', sizeof (disp_expressions));
2622
  memset (im_expressions, '\0', sizeof (im_expressions));
2623
  save_stack_p = save_stack;
2624
 
2625
  /* First parse an instruction mnemonic & call i386_operand for the operands.
2626
     We assume that the scrubber has arranged it so that line[0] is the valid
2627
     start of a (possibly prefixed) mnemonic.  */
2628
 
2629
  line = parse_insn (line, mnemonic);
2630
  if (line == NULL)
2631
    return;
2632
 
2633
  line = parse_operands (line, mnemonic);
2634
  if (line == NULL)
2635
    return;
2636
 
2637
  /* Now we've parsed the mnemonic into a set of templates, and have the
2638
     operands at hand.  */
2639
 
2640
  /* All intel opcodes have reversed operands except for "bound" and
2641
     "enter".  We also don't reverse intersegment "jmp" and "call"
2642
     instructions with 2 immediate operands so that the immediate segment
2643
     precedes the offset, as it does when in AT&T mode. */
2644
  if (intel_syntax
2645
      && i.operands > 1
2646
      && (strcmp (mnemonic, "bound") != 0)
2647
      && (strcmp (mnemonic, "invlpga") != 0)
2648
      && !(operand_type_check (i.types[0], imm)
2649
           && operand_type_check (i.types[1], imm)))
2650
    swap_operands ();
2651
 
2652
  /* The order of the immediates should be reversed
2653
     for 2 immediates extrq and insertq instructions */
2654
  if (i.imm_operands == 2
2655
      && (strcmp (mnemonic, "extrq") == 0
2656
          || strcmp (mnemonic, "insertq") == 0))
2657
      swap_2_operands (0, 1);
2658
 
2659
  if (i.imm_operands)
2660
    optimize_imm ();
2661
 
2662
  /* Don't optimize displacement for movabs since it only takes 64bit
2663
     displacement.  */
2664
  if (i.disp_operands
2665
      && (flag_code != CODE_64BIT
2666
          || strcmp (mnemonic, "movabs") != 0))
2667
    optimize_disp ();
2668
 
2669
  /* Next, we find a template that matches the given insn,
2670
     making sure the overlap of the given operands types is consistent
2671
     with the template operand types.  */
2672
 
2673
  if (!match_template ())
2674
    return;
2675
 
2676
  if (sse_check != sse_check_none
2677
      && !i.tm.opcode_modifier.noavx
2678
      && (i.tm.cpu_flags.bitfield.cpusse
2679
          || i.tm.cpu_flags.bitfield.cpusse2
2680
          || i.tm.cpu_flags.bitfield.cpusse3
2681
          || i.tm.cpu_flags.bitfield.cpussse3
2682
          || i.tm.cpu_flags.bitfield.cpusse4_1
2683
          || i.tm.cpu_flags.bitfield.cpusse4_2))
2684
    {
2685
      (sse_check == sse_check_warning
2686
       ? as_warn
2687
       : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2688
    }
2689
 
2690
  /* Zap movzx and movsx suffix.  The suffix has been set from
2691
     "word ptr" or "byte ptr" on the source operand in Intel syntax
2692
     or extracted from mnemonic in AT&T syntax.  But we'll use
2693
     the destination register to choose the suffix for encoding.  */
2694
  if ((i.tm.base_opcode & ~9) == 0x0fb6)
2695
    {
2696
      /* In Intel syntax, there must be a suffix.  In AT&T syntax, if
2697
         there is no suffix, the default will be byte extension.  */
2698
      if (i.reg_operands != 2
2699
          && !i.suffix
2700
          && intel_syntax)
2701
        as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2702
 
2703
      i.suffix = 0;
2704
    }
2705
 
2706
  if (i.tm.opcode_modifier.fwait)
2707
    if (!add_prefix (FWAIT_OPCODE))
2708
      return;
2709
 
2710
  /* Check string instruction segment overrides.  */
2711
  if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2712
    {
2713
      if (!check_string ())
2714
        return;
2715
    }
2716
 
2717
  if (!process_suffix ())
2718
    return;
2719
 
2720
  /* Make still unresolved immediate matches conform to size of immediate
2721
     given in i.suffix.  */
2722
  if (!finalize_imm ())
2723
    return;
2724
 
2725
  if (i.types[0].bitfield.imm1)
2726
    i.imm_operands = 0;  /* kludge for shift insns.  */
2727
 
2728
  for (j = 0; j < 3; j++)
2729
    if (i.types[j].bitfield.inoutportreg
2730
        || i.types[j].bitfield.shiftcount
2731
        || i.types[j].bitfield.acc
2732
        || i.types[j].bitfield.floatacc)
2733
      i.reg_operands--;
2734
 
2735
  /* ImmExt should be processed after SSE2AVX.  */
2736
  if (!i.tm.opcode_modifier.sse2avx
2737
      && i.tm.opcode_modifier.immext)
2738
    process_immext ();
2739
 
2740
  /* For insns with operands there are more diddles to do to the opcode.  */
2741
  if (i.operands)
2742
    {
2743
      if (!process_operands ())
2744
        return;
2745
    }
2746
  else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2747
    {
2748
      /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.  */
2749
      as_warn (_("translating to `%sp'"), i.tm.name);
2750
    }
2751
 
2752
  if (i.tm.opcode_modifier.vex)
2753
    build_vex_prefix ();
2754
 
2755
  /* Handle conversion of 'int $3' --> special int3 insn.  */
2756
  if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2757
    {
2758
      i.tm.base_opcode = INT3_OPCODE;
2759
      i.imm_operands = 0;
2760
    }
2761
 
2762
  if ((i.tm.opcode_modifier.jump
2763
       || i.tm.opcode_modifier.jumpbyte
2764
       || i.tm.opcode_modifier.jumpdword)
2765
      && i.op[0].disps->X_op == O_constant)
2766
    {
2767
      /* Convert "jmp constant" (and "call constant") to a jump (call) to
2768
         the absolute address given by the constant.  Since ix86 jumps and
2769
         calls are pc relative, we need to generate a reloc.  */
2770
      i.op[0].disps->X_add_symbol = &abs_symbol;
2771
      i.op[0].disps->X_op = O_symbol;
2772
    }
2773
 
2774
  if (i.tm.opcode_modifier.rex64)
2775
    i.rex |= REX_W;
2776
 
2777
  /* For 8 bit registers we need an empty rex prefix.  Also if the
2778
     instruction already has a prefix, we need to convert old
2779
     registers to new ones.  */
2780
 
2781
  if ((i.types[0].bitfield.reg8
2782
       && (i.op[0].regs->reg_flags & RegRex64) != 0)
2783
      || (i.types[1].bitfield.reg8
2784
          && (i.op[1].regs->reg_flags & RegRex64) != 0)
2785
      || ((i.types[0].bitfield.reg8
2786
           || i.types[1].bitfield.reg8)
2787
          && i.rex != 0))
2788
    {
2789
      int x;
2790
 
2791
      i.rex |= REX_OPCODE;
2792
      for (x = 0; x < 2; x++)
2793
        {
2794
          /* Look for 8 bit operand that uses old registers.  */
2795
          if (i.types[x].bitfield.reg8
2796
              && (i.op[x].regs->reg_flags & RegRex64) == 0)
2797
            {
2798
              /* In case it is "hi" register, give up.  */
2799
              if (i.op[x].regs->reg_num > 3)
2800
                as_bad (_("can't encode register '%s%s' in an "
2801
                          "instruction requiring REX prefix."),
2802
                        register_prefix, i.op[x].regs->reg_name);
2803
 
2804
              /* Otherwise it is equivalent to the extended register.
2805
                 Since the encoding doesn't change this is merely
2806
                 cosmetic cleanup for debug output.  */
2807
 
2808
              i.op[x].regs = i.op[x].regs + 8;
2809
            }
2810
        }
2811
    }
2812
 
2813
  /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2814
     REX prefix.  */
2815
  if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2816
    {
2817
      i.drex.rex = i.rex;
2818
      i.rex = 0;
2819
    }
2820
  else if (i.rex != 0)
2821
    add_prefix (REX_OPCODE | i.rex);
2822
 
2823
  /* We are ready to output the insn.  */
2824
  output_insn ();
2825
}
2826
 
2827
static char *
2828
parse_insn (char *line, char *mnemonic)
2829
{
2830
  char *l = line;
2831
  char *token_start = l;
2832
  char *mnem_p;
2833
  int supported;
2834
  const template *t;
2835
 
2836
  /* Non-zero if we found a prefix only acceptable with string insns.  */
2837
  const char *expecting_string_instruction = NULL;
2838
 
2839
  while (1)
2840
    {
2841
      mnem_p = mnemonic;
2842
      while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2843
        {
2844
          mnem_p++;
2845
          if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2846
            {
2847
              as_bad (_("no such instruction: `%s'"), token_start);
2848
              return NULL;
2849
            }
2850
          l++;
2851
        }
2852
      if (!is_space_char (*l)
2853
          && *l != END_OF_INSN
2854
          && (intel_syntax
2855
              || (*l != PREFIX_SEPARATOR
2856
                  && *l != ',')))
2857
        {
2858
          as_bad (_("invalid character %s in mnemonic"),
2859
                  output_invalid (*l));
2860
          return NULL;
2861
        }
2862
      if (token_start == l)
2863
        {
2864
          if (!intel_syntax && *l == PREFIX_SEPARATOR)
2865
            as_bad (_("expecting prefix; got nothing"));
2866
          else
2867
            as_bad (_("expecting mnemonic; got nothing"));
2868
          return NULL;
2869
        }
2870
 
2871
      /* Look up instruction (or prefix) via hash table.  */
2872
      current_templates = hash_find (op_hash, mnemonic);
2873
 
2874
      if (*l != END_OF_INSN
2875
          && (!is_space_char (*l) || l[1] != END_OF_INSN)
2876
          && current_templates
2877
          && current_templates->start->opcode_modifier.isprefix)
2878
        {
2879
          if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2880
            {
2881
              as_bad ((flag_code != CODE_64BIT
2882
                       ? _("`%s' is only supported in 64-bit mode")
2883
                       : _("`%s' is not supported in 64-bit mode")),
2884
                      current_templates->start->name);
2885
              return NULL;
2886
            }
2887
          /* If we are in 16-bit mode, do not allow addr16 or data16.
2888
             Similarly, in 32-bit mode, do not allow addr32 or data32.  */
2889
          if ((current_templates->start->opcode_modifier.size16
2890
               || current_templates->start->opcode_modifier.size32)
2891
              && flag_code != CODE_64BIT
2892
              && (current_templates->start->opcode_modifier.size32
2893
                  ^ (flag_code == CODE_16BIT)))
2894
            {
2895
              as_bad (_("redundant %s prefix"),
2896
                      current_templates->start->name);
2897
              return NULL;
2898
            }
2899
          /* Add prefix, checking for repeated prefixes.  */
2900
          switch (add_prefix (current_templates->start->base_opcode))
2901
            {
2902
            case 0:
2903
              return NULL;
2904
            case 2:
2905
              expecting_string_instruction = current_templates->start->name;
2906
              break;
2907
            }
2908
          /* Skip past PREFIX_SEPARATOR and reset token_start.  */
2909
          token_start = ++l;
2910
        }
2911
      else
2912
        break;
2913
    }
2914
 
2915
  if (!current_templates)
2916
    {
2917
      /* See if we can get a match by trimming off a suffix.  */
2918
      switch (mnem_p[-1])
2919
        {
2920
        case WORD_MNEM_SUFFIX:
2921
          if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2922
            i.suffix = SHORT_MNEM_SUFFIX;
2923
          else
2924
        case BYTE_MNEM_SUFFIX:
2925
        case QWORD_MNEM_SUFFIX:
2926
          i.suffix = mnem_p[-1];
2927
          mnem_p[-1] = '\0';
2928
          current_templates = hash_find (op_hash, mnemonic);
2929
          break;
2930
        case SHORT_MNEM_SUFFIX:
2931
        case LONG_MNEM_SUFFIX:
2932
          if (!intel_syntax)
2933
            {
2934
              i.suffix = mnem_p[-1];
2935
              mnem_p[-1] = '\0';
2936
              current_templates = hash_find (op_hash, mnemonic);
2937
            }
2938
          break;
2939
 
2940
          /* Intel Syntax.  */
2941
        case 'd':
2942
          if (intel_syntax)
2943
            {
2944
              if (intel_float_operand (mnemonic) == 1)
2945
                i.suffix = SHORT_MNEM_SUFFIX;
2946
              else
2947
                i.suffix = LONG_MNEM_SUFFIX;
2948
              mnem_p[-1] = '\0';
2949
              current_templates = hash_find (op_hash, mnemonic);
2950
            }
2951
          break;
2952
        }
2953
      if (!current_templates)
2954
        {
2955
          as_bad (_("no such instruction: `%s'"), token_start);
2956
          return NULL;
2957
        }
2958
    }
2959
 
2960
  if (current_templates->start->opcode_modifier.jump
2961
      || current_templates->start->opcode_modifier.jumpbyte)
2962
    {
2963
      /* Check for a branch hint.  We allow ",pt" and ",pn" for
2964
         predict taken and predict not taken respectively.
2965
         I'm not sure that branch hints actually do anything on loop
2966
         and jcxz insns (JumpByte) for current Pentium4 chips.  They
2967
         may work in the future and it doesn't hurt to accept them
2968
         now.  */
2969
      if (l[0] == ',' && l[1] == 'p')
2970
        {
2971
          if (l[2] == 't')
2972
            {
2973
              if (!add_prefix (DS_PREFIX_OPCODE))
2974
                return NULL;
2975
              l += 3;
2976
            }
2977
          else if (l[2] == 'n')
2978
            {
2979
              if (!add_prefix (CS_PREFIX_OPCODE))
2980
                return NULL;
2981
              l += 3;
2982
            }
2983
        }
2984
    }
2985
  /* Any other comma loses.  */
2986
  if (*l == ',')
2987
    {
2988
      as_bad (_("invalid character %s in mnemonic"),
2989
              output_invalid (*l));
2990
      return NULL;
2991
    }
2992
 
2993
  /* Check if instruction is supported on specified architecture.  */
2994
  supported = 0;
2995
  for (t = current_templates->start; t < current_templates->end; ++t)
2996
    {
2997
      supported |= cpu_flags_match (t);
2998
      if (supported == CPU_FLAGS_PERFECT_MATCH)
2999
        goto skip;
3000
    }
3001
 
3002
  if (!(supported & CPU_FLAGS_64BIT_MATCH))
3003
    {
3004
      as_bad (flag_code == CODE_64BIT
3005
              ? _("`%s' is not supported in 64-bit mode")
3006
              : _("`%s' is only supported in 64-bit mode"),
3007
              current_templates->start->name);
3008
      return NULL;
3009
    }
3010
  if (supported != CPU_FLAGS_PERFECT_MATCH)
3011
    {
3012
      as_bad (_("`%s' is not supported on `%s%s'"),
3013
              current_templates->start->name, cpu_arch_name,
3014
              cpu_sub_arch_name ? cpu_sub_arch_name : "");
3015
      return NULL;
3016
    }
3017
 
3018
skip:
3019
  if (!cpu_arch_flags.bitfield.cpui386
3020
           && (flag_code != CODE_16BIT))
3021
    {
3022
      as_warn (_("use .code16 to ensure correct addressing mode"));
3023
    }
3024
 
3025
  /* Check for rep/repne without a string instruction.  */
3026
  if (expecting_string_instruction)
3027
    {
3028
      static templates override;
3029
 
3030
      for (t = current_templates->start; t < current_templates->end; ++t)
3031
        if (t->opcode_modifier.isstring)
3032
          break;
3033
      if (t >= current_templates->end)
3034
        {
3035
          as_bad (_("expecting string instruction after `%s'"),
3036
                  expecting_string_instruction);
3037
          return NULL;
3038
        }
3039
      for (override.start = t; t < current_templates->end; ++t)
3040
        if (!t->opcode_modifier.isstring)
3041
          break;
3042
      override.end = t;
3043
      current_templates = &override;
3044
    }
3045
 
3046
  return l;
3047
}
3048
 
3049
static char *
3050
parse_operands (char *l, const char *mnemonic)
3051
{
3052
  char *token_start;
3053
 
3054
  /* 1 if operand is pending after ','.  */
3055
  unsigned int expecting_operand = 0;
3056
 
3057
  /* Non-zero if operand parens not balanced.  */
3058
  unsigned int paren_not_balanced;
3059
 
3060
  while (*l != END_OF_INSN)
3061
    {
3062
      /* Skip optional white space before operand.  */
3063
      if (is_space_char (*l))
3064
        ++l;
3065
      if (!is_operand_char (*l) && *l != END_OF_INSN)
3066
        {
3067
          as_bad (_("invalid character %s before operand %d"),
3068
                  output_invalid (*l),
3069
                  i.operands + 1);
3070
          return NULL;
3071
        }
3072
      token_start = l;  /* after white space */
3073
      paren_not_balanced = 0;
3074
      while (paren_not_balanced || *l != ',')
3075
        {
3076
          if (*l == END_OF_INSN)
3077
            {
3078
              if (paren_not_balanced)
3079
                {
3080
                  if (!intel_syntax)
3081
                    as_bad (_("unbalanced parenthesis in operand %d."),
3082
                            i.operands + 1);
3083
                  else
3084
                    as_bad (_("unbalanced brackets in operand %d."),
3085
                            i.operands + 1);
3086
                  return NULL;
3087
                }
3088
              else
3089
                break;  /* we are done */
3090
            }
3091
          else if (!is_operand_char (*l) && !is_space_char (*l))
3092
            {
3093
              as_bad (_("invalid character %s in operand %d"),
3094
                      output_invalid (*l),
3095
                      i.operands + 1);
3096
              return NULL;
3097
            }
3098
          if (!intel_syntax)
3099
            {
3100
              if (*l == '(')
3101
                ++paren_not_balanced;
3102
              if (*l == ')')
3103
                --paren_not_balanced;
3104
            }
3105
          else
3106
            {
3107
              if (*l == '[')
3108
                ++paren_not_balanced;
3109
              if (*l == ']')
3110
                --paren_not_balanced;
3111
            }
3112
          l++;
3113
        }
3114
      if (l != token_start)
3115
        {                       /* Yes, we've read in another operand.  */
3116
          unsigned int operand_ok;
3117
          this_operand = i.operands++;
3118
          i.types[this_operand].bitfield.unspecified = 1;
3119
          if (i.operands > MAX_OPERANDS)
3120
            {
3121
              as_bad (_("spurious operands; (%d operands/instruction max)"),
3122
                      MAX_OPERANDS);
3123
              return NULL;
3124
            }
3125
          /* Now parse operand adding info to 'i' as we go along.  */
3126
          END_STRING_AND_SAVE (l);
3127
 
3128
          if (intel_syntax)
3129
            operand_ok =
3130
              i386_intel_operand (token_start,
3131
                                  intel_float_operand (mnemonic));
3132
          else
3133
            operand_ok = i386_att_operand (token_start);
3134
 
3135
          RESTORE_END_STRING (l);
3136
          if (!operand_ok)
3137
            return NULL;
3138
        }
3139
      else
3140
        {
3141
          if (expecting_operand)
3142
            {
3143
            expecting_operand_after_comma:
3144
              as_bad (_("expecting operand after ','; got nothing"));
3145
              return NULL;
3146
            }
3147
          if (*l == ',')
3148
            {
3149
              as_bad (_("expecting operand before ','; got nothing"));
3150
              return NULL;
3151
            }
3152
        }
3153
 
3154
      /* Now *l must be either ',' or END_OF_INSN.  */
3155
      if (*l == ',')
3156
        {
3157
          if (*++l == END_OF_INSN)
3158
            {
3159
              /* Just skip it, if it's \n complain.  */
3160
              goto expecting_operand_after_comma;
3161
            }
3162
          expecting_operand = 1;
3163
        }
3164
    }
3165
  return l;
3166
}
3167
 
3168
static void
3169
swap_2_operands (int xchg1, int xchg2)
3170
{
3171
  union i386_op temp_op;
3172
  i386_operand_type temp_type;
3173
  enum bfd_reloc_code_real temp_reloc;
3174
 
3175
  temp_type = i.types[xchg2];
3176
  i.types[xchg2] = i.types[xchg1];
3177
  i.types[xchg1] = temp_type;
3178
  temp_op = i.op[xchg2];
3179
  i.op[xchg2] = i.op[xchg1];
3180
  i.op[xchg1] = temp_op;
3181
  temp_reloc = i.reloc[xchg2];
3182
  i.reloc[xchg2] = i.reloc[xchg1];
3183
  i.reloc[xchg1] = temp_reloc;
3184
}
3185
 
3186
static void
3187
swap_operands (void)
3188
{
3189
  switch (i.operands)
3190
    {
3191
    case 5:
3192
    case 4:
3193
      swap_2_operands (1, i.operands - 2);
3194
    case 3:
3195
    case 2:
3196
      swap_2_operands (0, i.operands - 1);
3197
      break;
3198
    default:
3199
      abort ();
3200
    }
3201
 
3202
  if (i.mem_operands == 2)
3203
    {
3204
      const seg_entry *temp_seg;
3205
      temp_seg = i.seg[0];
3206
      i.seg[0] = i.seg[1];
3207
      i.seg[1] = temp_seg;
3208
    }
3209
}
3210
 
3211
/* Try to ensure constant immediates are represented in the smallest
3212
   opcode possible.  */
3213
static void
3214
optimize_imm (void)
3215
{
3216
  char guess_suffix = 0;
3217
  int op;
3218
 
3219
  if (i.suffix)
3220
    guess_suffix = i.suffix;
3221
  else if (i.reg_operands)
3222
    {
3223
      /* Figure out a suffix from the last register operand specified.
3224
         We can't do this properly yet, ie. excluding InOutPortReg,
3225
         but the following works for instructions with immediates.
3226
         In any case, we can't set i.suffix yet.  */
3227
      for (op = i.operands; --op >= 0;)
3228
        if (i.types[op].bitfield.reg8)
3229
          {
3230
            guess_suffix = BYTE_MNEM_SUFFIX;
3231
            break;
3232
          }
3233
        else if (i.types[op].bitfield.reg16)
3234
          {
3235
            guess_suffix = WORD_MNEM_SUFFIX;
3236
            break;
3237
          }
3238
        else if (i.types[op].bitfield.reg32)
3239
          {
3240
            guess_suffix = LONG_MNEM_SUFFIX;
3241
            break;
3242
          }
3243
        else if (i.types[op].bitfield.reg64)
3244
          {
3245
            guess_suffix = QWORD_MNEM_SUFFIX;
3246
            break;
3247
          }
3248
    }
3249
  else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3250
    guess_suffix = WORD_MNEM_SUFFIX;
3251
 
3252
  for (op = i.operands; --op >= 0;)
3253
    if (operand_type_check (i.types[op], imm))
3254
      {
3255
        switch (i.op[op].imms->X_op)
3256
          {
3257
          case O_constant:
3258
            /* If a suffix is given, this operand may be shortened.  */
3259
            switch (guess_suffix)
3260
              {
3261
              case LONG_MNEM_SUFFIX:
3262
                i.types[op].bitfield.imm32 = 1;
3263
                i.types[op].bitfield.imm64 = 1;
3264
                break;
3265
              case WORD_MNEM_SUFFIX:
3266
                i.types[op].bitfield.imm16 = 1;
3267
                i.types[op].bitfield.imm32 = 1;
3268
                i.types[op].bitfield.imm32s = 1;
3269
                i.types[op].bitfield.imm64 = 1;
3270
                break;
3271
              case BYTE_MNEM_SUFFIX:
3272
                i.types[op].bitfield.imm8 = 1;
3273
                i.types[op].bitfield.imm8s = 1;
3274
                i.types[op].bitfield.imm16 = 1;
3275
                i.types[op].bitfield.imm32 = 1;
3276
                i.types[op].bitfield.imm32s = 1;
3277
                i.types[op].bitfield.imm64 = 1;
3278
                break;
3279
              }
3280
 
3281
            /* If this operand is at most 16 bits, convert it
3282
               to a signed 16 bit number before trying to see
3283
               whether it will fit in an even smaller size.
3284
               This allows a 16-bit operand such as $0xffe0 to
3285
               be recognised as within Imm8S range.  */
3286
            if ((i.types[op].bitfield.imm16)
3287
                && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3288
              {
3289
                i.op[op].imms->X_add_number =
3290
                  (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3291
              }
3292
            if ((i.types[op].bitfield.imm32)
3293
                && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3294
                    == 0))
3295
              {
3296
                i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3297
                                                ^ ((offsetT) 1 << 31))
3298
                                               - ((offsetT) 1 << 31));
3299
              }
3300
            i.types[op]
3301
              = operand_type_or (i.types[op],
3302
                                 smallest_imm_type (i.op[op].imms->X_add_number));
3303
 
3304
            /* We must avoid matching of Imm32 templates when 64bit
3305
               only immediate is available.  */
3306
            if (guess_suffix == QWORD_MNEM_SUFFIX)
3307
              i.types[op].bitfield.imm32 = 0;
3308
            break;
3309
 
3310
          case O_absent:
3311
          case O_register:
3312
            abort ();
3313
 
3314
            /* Symbols and expressions.  */
3315
          default:
3316
            /* Convert symbolic operand to proper sizes for matching, but don't
3317
               prevent matching a set of insns that only supports sizes other
3318
               than those matching the insn suffix.  */
3319
            {
3320
              i386_operand_type mask, allowed;
3321
              const template *t;
3322
 
3323
              operand_type_set (&mask, 0);
3324
              operand_type_set (&allowed, 0);
3325
 
3326
              for (t = current_templates->start;
3327
                   t < current_templates->end;
3328
                   ++t)
3329
                allowed = operand_type_or (allowed,
3330
                                           t->operand_types[op]);
3331
              switch (guess_suffix)
3332
                {
3333
                case QWORD_MNEM_SUFFIX:
3334
                  mask.bitfield.imm64 = 1;
3335
                  mask.bitfield.imm32s = 1;
3336
                  break;
3337
                case LONG_MNEM_SUFFIX:
3338
                  mask.bitfield.imm32 = 1;
3339
                  break;
3340
                case WORD_MNEM_SUFFIX:
3341
                  mask.bitfield.imm16 = 1;
3342
                  break;
3343
                case BYTE_MNEM_SUFFIX:
3344
                  mask.bitfield.imm8 = 1;
3345
                  break;
3346
                default:
3347
                  break;
3348
                }
3349
              allowed = operand_type_and (mask, allowed);
3350
              if (!operand_type_all_zero (&allowed))
3351
                i.types[op] = operand_type_and (i.types[op], mask);
3352
            }
3353
            break;
3354
          }
3355
      }
3356
}
3357
 
3358
/* Try to use the smallest displacement type too.  */
3359
static void
3360
optimize_disp (void)
3361
{
3362
  int op;
3363
 
3364
  for (op = i.operands; --op >= 0;)
3365
    if (operand_type_check (i.types[op], disp))
3366
      {
3367
        if (i.op[op].disps->X_op == O_constant)
3368
          {
3369
            offsetT disp = i.op[op].disps->X_add_number;
3370
 
3371
            if (i.types[op].bitfield.disp16
3372
                && (disp & ~(offsetT) 0xffff) == 0)
3373
              {
3374
                /* If this operand is at most 16 bits, convert
3375
                   to a signed 16 bit number and don't use 64bit
3376
                   displacement.  */
3377
                disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
3378
                i.types[op].bitfield.disp64 = 0;
3379
              }
3380
            if (i.types[op].bitfield.disp32
3381
                && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3382
              {
3383
                /* If this operand is at most 32 bits, convert
3384
                   to a signed 32 bit number and don't use 64bit
3385
                   displacement.  */
3386
                disp &= (((offsetT) 2 << 31) - 1);
3387
                disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3388
                i.types[op].bitfield.disp64 = 0;
3389
              }
3390
            if (!disp && i.types[op].bitfield.baseindex)
3391
              {
3392
                i.types[op].bitfield.disp8 = 0;
3393
                i.types[op].bitfield.disp16 = 0;
3394
                i.types[op].bitfield.disp32 = 0;
3395
                i.types[op].bitfield.disp32s = 0;
3396
                i.types[op].bitfield.disp64 = 0;
3397
                i.op[op].disps = 0;
3398
                i.disp_operands--;
3399
              }
3400
            else if (flag_code == CODE_64BIT)
3401
              {
3402
                if (fits_in_signed_long (disp))
3403
                  {
3404
                    i.types[op].bitfield.disp64 = 0;
3405
                    i.types[op].bitfield.disp32s = 1;
3406
                  }
3407
                if (fits_in_unsigned_long (disp))
3408
                  i.types[op].bitfield.disp32 = 1;
3409
              }
3410
            if ((i.types[op].bitfield.disp32
3411
                 || i.types[op].bitfield.disp32s
3412
                 || i.types[op].bitfield.disp16)
3413
                && fits_in_signed_byte (disp))
3414
              i.types[op].bitfield.disp8 = 1;
3415
          }
3416
        else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3417
                 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3418
          {
3419
            fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3420
                         i.op[op].disps, 0, i.reloc[op]);
3421
            i.types[op].bitfield.disp8 = 0;
3422
            i.types[op].bitfield.disp16 = 0;
3423
            i.types[op].bitfield.disp32 = 0;
3424
            i.types[op].bitfield.disp32s = 0;
3425
            i.types[op].bitfield.disp64 = 0;
3426
          }
3427
        else
3428
          /* We only support 64bit displacement on constants.  */
3429
          i.types[op].bitfield.disp64 = 0;
3430
      }
3431
}
3432
 
3433
/* Check if operands are valid for the instrucrtion.  Update VEX
3434
   operand types.  */
3435
 
3436
static int
3437
VEX_check_operands (const template *t)
3438
{
3439
  if (!t->opcode_modifier.vex)
3440
    return 0;
3441
 
3442
  /* Only check VEX_Imm4, which must be the first operand.  */
3443
  if (t->operand_types[0].bitfield.vex_imm4)
3444
    {
3445
      if (i.op[0].imms->X_op != O_constant
3446
          || !fits_in_imm4 (i.op[0].imms->X_add_number))
3447
        return 1;
3448
 
3449
      /* Turn off Imm8 so that update_imm won't complain.  */
3450
      i.types[0] = vex_imm4;
3451
    }
3452
 
3453
  return 0;
3454
}
3455
 
3456
static int
3457
match_template (void)
3458
{
3459
  /* Points to template once we've found it.  */
3460
  const template *t;
3461
  i386_operand_type overlap0, overlap1, overlap2, overlap3;
3462
  i386_operand_type overlap4;
3463
  unsigned int found_reverse_match;
3464
  i386_opcode_modifier suffix_check;
3465
  i386_operand_type operand_types [MAX_OPERANDS];
3466
  int addr_prefix_disp;
3467
  unsigned int j;
3468
  unsigned int found_cpu_match;
3469
  unsigned int check_register;
3470
 
3471
#if MAX_OPERANDS != 5
3472
# error "MAX_OPERANDS must be 5."
3473
#endif
3474
 
3475
  found_reverse_match = 0;
3476
  addr_prefix_disp = -1;
3477
 
3478
  memset (&suffix_check, 0, sizeof (suffix_check));
3479
  if (i.suffix == BYTE_MNEM_SUFFIX)
3480
    suffix_check.no_bsuf = 1;
3481
  else if (i.suffix == WORD_MNEM_SUFFIX)
3482
    suffix_check.no_wsuf = 1;
3483
  else if (i.suffix == SHORT_MNEM_SUFFIX)
3484
    suffix_check.no_ssuf = 1;
3485
  else if (i.suffix == LONG_MNEM_SUFFIX)
3486
    suffix_check.no_lsuf = 1;
3487
  else if (i.suffix == QWORD_MNEM_SUFFIX)
3488
    suffix_check.no_qsuf = 1;
3489
  else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3490
    suffix_check.no_ldsuf = 1;
3491
 
3492
  for (t = current_templates->start; t < current_templates->end; t++)
3493
    {
3494
      addr_prefix_disp = -1;
3495
 
3496
      /* Must have right number of operands.  */
3497
      if (i.operands != t->operands)
3498
        continue;
3499
 
3500
      /* Check processor support.  */
3501
      found_cpu_match = (cpu_flags_match (t)
3502
                         == CPU_FLAGS_PERFECT_MATCH);
3503
      if (!found_cpu_match)
3504
        continue;
3505
 
3506
      /* Check old gcc support. */
3507
      if (!old_gcc && t->opcode_modifier.oldgcc)
3508
        continue;
3509
 
3510
      /* Check AT&T mnemonic.   */
3511
      if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3512
        continue;
3513
 
3514
      /* Check AT&T syntax Intel syntax.   */
3515
      if ((intel_syntax && t->opcode_modifier.attsyntax)
3516
          || (!intel_syntax && t->opcode_modifier.intelsyntax))
3517
        continue;
3518
 
3519
      /* Check the suffix, except for some instructions in intel mode.  */
3520
      if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3521
          && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3522
              || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3523
              || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3524
              || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3525
              || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3526
              || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3527
        continue;
3528
 
3529
      if (!operand_size_match (t))
3530
        continue;
3531
 
3532
      for (j = 0; j < MAX_OPERANDS; j++)
3533
        operand_types[j] = t->operand_types[j];
3534
 
3535
      /* In general, don't allow 64-bit operands in 32-bit mode.  */
3536
      if (i.suffix == QWORD_MNEM_SUFFIX
3537
          && flag_code != CODE_64BIT
3538
          && (intel_syntax
3539
              ? (!t->opcode_modifier.ignoresize
3540
                 && !intel_float_operand (t->name))
3541
              : intel_float_operand (t->name) != 2)
3542
          && ((!operand_types[0].bitfield.regmmx
3543
               && !operand_types[0].bitfield.regxmm
3544
               && !operand_types[0].bitfield.regymm)
3545
              || (!operand_types[t->operands > 1].bitfield.regmmx
3546
                  && !!operand_types[t->operands > 1].bitfield.regxmm
3547
                  && !!operand_types[t->operands > 1].bitfield.regymm))
3548
          && (t->base_opcode != 0x0fc7
3549
              || t->extension_opcode != 1 /* cmpxchg8b */))
3550
        continue;
3551
 
3552
      /* In general, don't allow 32-bit operands on pre-386.  */
3553
      else if (i.suffix == LONG_MNEM_SUFFIX
3554
               && !cpu_arch_flags.bitfield.cpui386
3555
               && (intel_syntax
3556
                   ? (!t->opcode_modifier.ignoresize
3557
                      && !intel_float_operand (t->name))
3558
                   : intel_float_operand (t->name) != 2)
3559
               && ((!operand_types[0].bitfield.regmmx
3560
                    && !operand_types[0].bitfield.regxmm)
3561
                   || (!operand_types[t->operands > 1].bitfield.regmmx
3562
                       && !!operand_types[t->operands > 1].bitfield.regxmm)))
3563
        continue;
3564
 
3565
      /* Do not verify operands when there are none.  */
3566
      else
3567
        {
3568
          if (!t->operands)
3569
            /* We've found a match; break out of loop.  */
3570
            break;
3571
        }
3572
 
3573
      /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3574
         into Disp32/Disp16/Disp32 operand.  */
3575
      if (i.prefix[ADDR_PREFIX] != 0)
3576
          {
3577
            /* There should be only one Disp operand.  */
3578
            switch (flag_code)
3579
            {
3580
            case CODE_16BIT:
3581
              for (j = 0; j < MAX_OPERANDS; j++)
3582
                {
3583
                  if (operand_types[j].bitfield.disp16)
3584
                    {
3585
                      addr_prefix_disp = j;
3586
                      operand_types[j].bitfield.disp32 = 1;
3587
                      operand_types[j].bitfield.disp16 = 0;
3588
                      break;
3589
                    }
3590
                }
3591
              break;
3592
            case CODE_32BIT:
3593
              for (j = 0; j < MAX_OPERANDS; j++)
3594
                {
3595
                  if (operand_types[j].bitfield.disp32)
3596
                    {
3597
                      addr_prefix_disp = j;
3598
                      operand_types[j].bitfield.disp32 = 0;
3599
                      operand_types[j].bitfield.disp16 = 1;
3600
                      break;
3601
                    }
3602
                }
3603
              break;
3604
            case CODE_64BIT:
3605
              for (j = 0; j < MAX_OPERANDS; j++)
3606
                {
3607
                  if (operand_types[j].bitfield.disp64)
3608
                    {
3609
                      addr_prefix_disp = j;
3610
                      operand_types[j].bitfield.disp64 = 0;
3611
                      operand_types[j].bitfield.disp32 = 1;
3612
                      break;
3613
                    }
3614
                }
3615
              break;
3616
            }
3617
          }
3618
 
3619
      /* We check register size only if size of operands can be
3620
         encoded the canonical way.  */
3621
      check_register = t->opcode_modifier.w;
3622
      overlap0 = operand_type_and (i.types[0], operand_types[0]);
3623
      switch (t->operands)
3624
        {
3625
        case 1:
3626
          if (!operand_type_match (overlap0, i.types[0]))
3627
            continue;
3628
          break;
3629
        case 2:
3630
          /* xchg %eax, %eax is a special case. It is an aliase for nop
3631
             only in 32bit mode and we can use opcode 0x90.  In 64bit
3632
             mode, we can't use 0x90 for xchg %eax, %eax since it should
3633
             zero-extend %eax to %rax.  */
3634
          if (flag_code == CODE_64BIT
3635
              && t->base_opcode == 0x90
3636
              && operand_type_equal (&i.types [0], &acc32)
3637
              && operand_type_equal (&i.types [1], &acc32))
3638
            continue;
3639
        case 3:
3640
        case 4:
3641
        case 5:
3642
          overlap1 = operand_type_and (i.types[1], operand_types[1]);
3643
          if (!operand_type_match (overlap0, i.types[0])
3644
              || !operand_type_match (overlap1, i.types[1])
3645
              || (check_register
3646
                  && !operand_type_register_match (overlap0, i.types[0],
3647
                                                   operand_types[0],
3648
                                                   overlap1, i.types[1],
3649
                                                   operand_types[1])))
3650
            {
3651
              /* Check if other direction is valid ...  */
3652
              if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3653
                continue;
3654
 
3655
              /* Try reversing direction of operands.  */
3656
              overlap0 = operand_type_and (i.types[0], operand_types[1]);
3657
              overlap1 = operand_type_and (i.types[1], operand_types[0]);
3658
              if (!operand_type_match (overlap0, i.types[0])
3659
                  || !operand_type_match (overlap1, i.types[1])
3660
                  || (check_register
3661
                      && !operand_type_register_match (overlap0,
3662
                                                       i.types[0],
3663
                                                       operand_types[1],
3664
                                                       overlap1,
3665
                                                       i.types[1],
3666
                                                       operand_types[0])))
3667
                {
3668
                  /* Does not match either direction.  */
3669
                  continue;
3670
                }
3671
              /* found_reverse_match holds which of D or FloatDR
3672
                 we've found.  */
3673
              if (t->opcode_modifier.d)
3674
                found_reverse_match = Opcode_D;
3675
              else if (t->opcode_modifier.floatd)
3676
                found_reverse_match = Opcode_FloatD;
3677
              else
3678
                found_reverse_match = 0;
3679
              if (t->opcode_modifier.floatr)
3680
                found_reverse_match |= Opcode_FloatR;
3681
            }
3682
          else
3683
            {
3684
              /* Found a forward 2 operand match here.  */
3685
              switch (t->operands)
3686
                {
3687
                case 5:
3688
                  overlap4 = operand_type_and (i.types[4],
3689
                                               operand_types[4]);
3690
                case 4:
3691
                  overlap3 = operand_type_and (i.types[3],
3692
                                               operand_types[3]);
3693
                case 3:
3694
                  overlap2 = operand_type_and (i.types[2],
3695
                                               operand_types[2]);
3696
                  break;
3697
                }
3698
 
3699
              switch (t->operands)
3700
                {
3701
                case 5:
3702
                  if (!operand_type_match (overlap4, i.types[4])
3703
                      || !operand_type_register_match (overlap3,
3704
                                                       i.types[3],
3705
                                                       operand_types[3],
3706
                                                       overlap4,
3707
                                                       i.types[4],
3708
                                                       operand_types[4]))
3709
                    continue;
3710
                case 4:
3711
                  if (!operand_type_match (overlap3, i.types[3])
3712
                      || (check_register
3713
                          && !operand_type_register_match (overlap2,
3714
                                                           i.types[2],
3715
                                                           operand_types[2],
3716
                                                           overlap3,
3717
                                                           i.types[3],
3718
                                                           operand_types[3])))
3719
                    continue;
3720
                case 3:
3721
                  /* Here we make use of the fact that there are no
3722
                     reverse match 3 operand instructions, and all 3
3723
                     operand instructions only need to be checked for
3724
                     register consistency between operands 2 and 3.  */
3725
                  if (!operand_type_match (overlap2, i.types[2])
3726
                      || (check_register
3727
                          && !operand_type_register_match (overlap1,
3728
                                                           i.types[1],
3729
                                                           operand_types[1],
3730
                                                           overlap2,
3731
                                                           i.types[2],
3732
                                                           operand_types[2])))
3733
                    continue;
3734
                  break;
3735
                }
3736
            }
3737
          /* Found either forward/reverse 2, 3 or 4 operand match here:
3738
             slip through to break.  */
3739
        }
3740
      if (!found_cpu_match)
3741
        {
3742
          found_reverse_match = 0;
3743
          continue;
3744
        }
3745
 
3746
      /* Check if VEX operands are valid.  */
3747
      if (VEX_check_operands (t))
3748
        continue;
3749
 
3750
      /* We've found a match; break out of loop.  */
3751
      break;
3752
    }
3753
 
3754
  if (t == current_templates->end)
3755
    {
3756
      /* We found no match.  */
3757
      as_bad (_("suffix or operands invalid for `%s'"),
3758
              current_templates->start->name);
3759
      return 0;
3760
    }
3761
 
3762
  if (!quiet_warnings)
3763
    {
3764
      if (!intel_syntax
3765
          && (i.types[0].bitfield.jumpabsolute
3766
              != operand_types[0].bitfield.jumpabsolute))
3767
        {
3768
          as_warn (_("indirect %s without `*'"), t->name);
3769
        }
3770
 
3771
      if (t->opcode_modifier.isprefix
3772
          && t->opcode_modifier.ignoresize)
3773
        {
3774
          /* Warn them that a data or address size prefix doesn't
3775
             affect assembly of the next line of code.  */
3776
          as_warn (_("stand-alone `%s' prefix"), t->name);
3777
        }
3778
    }
3779
 
3780
  /* Copy the template we found.  */
3781
  i.tm = *t;
3782
 
3783
  if (addr_prefix_disp != -1)
3784
    i.tm.operand_types[addr_prefix_disp]
3785
      = operand_types[addr_prefix_disp];
3786
 
3787
  if (found_reverse_match)
3788
    {
3789
      /* If we found a reverse match we must alter the opcode
3790
         direction bit.  found_reverse_match holds bits to change
3791
         (different for int & float insns).  */
3792
 
3793
      i.tm.base_opcode ^= found_reverse_match;
3794
 
3795
      i.tm.operand_types[0] = operand_types[1];
3796
      i.tm.operand_types[1] = operand_types[0];
3797
    }
3798
 
3799
  return 1;
3800
}
3801
 
3802
static int
3803
check_string (void)
3804
{
3805
  int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3806
  if (i.tm.operand_types[mem_op].bitfield.esseg)
3807
    {
3808
      if (i.seg[0] != NULL && i.seg[0] != &es)
3809
        {
3810
          as_bad (_("`%s' operand %d must use `%%es' segment"),
3811
                  i.tm.name,
3812
                  mem_op + 1);
3813
          return 0;
3814
        }
3815
      /* There's only ever one segment override allowed per instruction.
3816
         This instruction possibly has a legal segment override on the
3817
         second operand, so copy the segment to where non-string
3818
         instructions store it, allowing common code.  */
3819
      i.seg[0] = i.seg[1];
3820
    }
3821
  else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3822
    {
3823
      if (i.seg[1] != NULL && i.seg[1] != &es)
3824
        {
3825
          as_bad (_("`%s' operand %d must use `%%es' segment"),
3826
                  i.tm.name,
3827
                  mem_op + 2);
3828
          return 0;
3829
        }
3830
    }
3831
  return 1;
3832
}
3833
 
3834
static int
3835
process_suffix (void)
3836
{
3837
  /* If matched instruction specifies an explicit instruction mnemonic
3838
     suffix, use it.  */
3839
  if (i.tm.opcode_modifier.size16)
3840
    i.suffix = WORD_MNEM_SUFFIX;
3841
  else if (i.tm.opcode_modifier.size32)
3842
    i.suffix = LONG_MNEM_SUFFIX;
3843
  else if (i.tm.opcode_modifier.size64)
3844
    i.suffix = QWORD_MNEM_SUFFIX;
3845
  else if (i.reg_operands)
3846
    {
3847
      /* If there's no instruction mnemonic suffix we try to invent one
3848
         based on register operands.  */
3849
      if (!i.suffix)
3850
        {
3851
          /* We take i.suffix from the last register operand specified,
3852
             Destination register type is more significant than source
3853
             register type.  crc32 in SSE4.2 prefers source register
3854
             type. */
3855
          if (i.tm.base_opcode == 0xf20f38f1)
3856
            {
3857
              if (i.types[0].bitfield.reg16)
3858
                i.suffix = WORD_MNEM_SUFFIX;
3859
              else if (i.types[0].bitfield.reg32)
3860
                i.suffix = LONG_MNEM_SUFFIX;
3861
              else if (i.types[0].bitfield.reg64)
3862
                i.suffix = QWORD_MNEM_SUFFIX;
3863
            }
3864
          else if (i.tm.base_opcode == 0xf20f38f0)
3865
            {
3866
              if (i.types[0].bitfield.reg8)
3867
                i.suffix = BYTE_MNEM_SUFFIX;
3868
            }
3869
 
3870
          if (!i.suffix)
3871
            {
3872
              int op;
3873
 
3874
              if (i.tm.base_opcode == 0xf20f38f1
3875
                  || i.tm.base_opcode == 0xf20f38f0)
3876
                {
3877
                  /* We have to know the operand size for crc32.  */
3878
                  as_bad (_("ambiguous memory operand size for `%s`"),
3879
                          i.tm.name);
3880
                  return 0;
3881
                }
3882
 
3883
              for (op = i.operands; --op >= 0;)
3884
                if (!i.tm.operand_types[op].bitfield.inoutportreg)
3885
                  {
3886
                    if (i.types[op].bitfield.reg8)
3887
                      {
3888
                        i.suffix = BYTE_MNEM_SUFFIX;
3889
                        break;
3890
                      }
3891
                    else if (i.types[op].bitfield.reg16)
3892
                      {
3893
                        i.suffix = WORD_MNEM_SUFFIX;
3894
                        break;
3895
                      }
3896
                    else if (i.types[op].bitfield.reg32)
3897
                      {
3898
                        i.suffix = LONG_MNEM_SUFFIX;
3899
                        break;
3900
                      }
3901
                    else if (i.types[op].bitfield.reg64)
3902
                      {
3903
                        i.suffix = QWORD_MNEM_SUFFIX;
3904
                        break;
3905
                      }
3906
                  }
3907
            }
3908
        }
3909
      else if (i.suffix == BYTE_MNEM_SUFFIX)
3910
        {
3911
          if (!check_byte_reg ())
3912
            return 0;
3913
        }
3914
      else if (i.suffix == LONG_MNEM_SUFFIX)
3915
        {
3916
          if (!check_long_reg ())
3917
            return 0;
3918
        }
3919
      else if (i.suffix == QWORD_MNEM_SUFFIX)
3920
        {
3921
          if (intel_syntax
3922
              && i.tm.opcode_modifier.ignoresize
3923
              && i.tm.opcode_modifier.no_qsuf)
3924
            i.suffix = 0;
3925
          else if (!check_qword_reg ())
3926
            return 0;
3927
        }
3928
      else if (i.suffix == WORD_MNEM_SUFFIX)
3929
        {
3930
          if (!check_word_reg ())
3931
            return 0;
3932
        }
3933
      else if (i.suffix == XMMWORD_MNEM_SUFFIX
3934
               || i.suffix == YMMWORD_MNEM_SUFFIX)
3935
        {
3936
          /* Skip if the instruction has x/y suffix.  match_template
3937
             should check if it is a valid suffix.  */
3938
        }
3939
      else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3940
        /* Do nothing if the instruction is going to ignore the prefix.  */
3941
        ;
3942
      else
3943
        abort ();
3944
    }
3945
  else if (i.tm.opcode_modifier.defaultsize
3946
           && !i.suffix
3947
           /* exclude fldenv/frstor/fsave/fstenv */
3948
           && i.tm.opcode_modifier.no_ssuf)
3949
    {
3950
      i.suffix = stackop_size;
3951
    }
3952
  else if (intel_syntax
3953
           && !i.suffix
3954
           && (i.tm.operand_types[0].bitfield.jumpabsolute
3955
               || i.tm.opcode_modifier.jumpbyte
3956
               || i.tm.opcode_modifier.jumpintersegment
3957
               || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3958
                   && i.tm.extension_opcode <= 3)))
3959
    {
3960
      switch (flag_code)
3961
        {
3962
        case CODE_64BIT:
3963
          if (!i.tm.opcode_modifier.no_qsuf)
3964
            {
3965
              i.suffix = QWORD_MNEM_SUFFIX;
3966
              break;
3967
            }
3968
        case CODE_32BIT:
3969
          if (!i.tm.opcode_modifier.no_lsuf)
3970
            i.suffix = LONG_MNEM_SUFFIX;
3971
          break;
3972
        case CODE_16BIT:
3973
          if (!i.tm.opcode_modifier.no_wsuf)
3974
            i.suffix = WORD_MNEM_SUFFIX;
3975
          break;
3976
        }
3977
    }
3978
 
3979
  if (!i.suffix)
3980
    {
3981
      if (!intel_syntax)
3982
        {
3983
          if (i.tm.opcode_modifier.w)
3984
            {
3985
              as_bad (_("no instruction mnemonic suffix given and "
3986
                        "no register operands; can't size instruction"));
3987
              return 0;
3988
            }
3989
        }
3990
      else
3991
        {
3992
          unsigned int suffixes;
3993
 
3994
          suffixes = !i.tm.opcode_modifier.no_bsuf;
3995
          if (!i.tm.opcode_modifier.no_wsuf)
3996
            suffixes |= 1 << 1;
3997
          if (!i.tm.opcode_modifier.no_lsuf)
3998
            suffixes |= 1 << 2;
3999
          if (!i.tm.opcode_modifier.no_ldsuf)
4000
            suffixes |= 1 << 3;
4001
          if (!i.tm.opcode_modifier.no_ssuf)
4002
            suffixes |= 1 << 4;
4003
          if (!i.tm.opcode_modifier.no_qsuf)
4004
            suffixes |= 1 << 5;
4005
 
4006
          /* There are more than suffix matches.  */
4007
          if (i.tm.opcode_modifier.w
4008
              || ((suffixes & (suffixes - 1))
4009
                  && !i.tm.opcode_modifier.defaultsize
4010
                  && !i.tm.opcode_modifier.ignoresize))
4011
            {
4012
              as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4013
              return 0;
4014
            }
4015
        }
4016
    }
4017
 
4018
  /* Change the opcode based on the operand size given by i.suffix;
4019
     We don't need to change things for byte insns.  */
4020
 
4021
  if (i.suffix
4022
      && i.suffix != BYTE_MNEM_SUFFIX
4023
      && i.suffix != XMMWORD_MNEM_SUFFIX
4024
      && i.suffix != YMMWORD_MNEM_SUFFIX)
4025
    {
4026
      /* It's not a byte, select word/dword operation.  */
4027
      if (i.tm.opcode_modifier.w)
4028
        {
4029
          if (i.tm.opcode_modifier.shortform)
4030
            i.tm.base_opcode |= 8;
4031
          else
4032
            i.tm.base_opcode |= 1;
4033
        }
4034
 
4035
      /* Now select between word & dword operations via the operand
4036
         size prefix, except for instructions that will ignore this
4037
         prefix anyway.  */
4038
      if (i.tm.opcode_modifier.addrprefixop0)
4039
        {
4040
          /* The address size override prefix changes the size of the
4041
             first operand.  */
4042
          if ((flag_code == CODE_32BIT
4043
               && i.op->regs[0].reg_type.bitfield.reg16)
4044
              || (flag_code != CODE_32BIT
4045
                  && i.op->regs[0].reg_type.bitfield.reg32))
4046
            if (!add_prefix (ADDR_PREFIX_OPCODE))
4047
              return 0;
4048
        }
4049
      else if (i.suffix != QWORD_MNEM_SUFFIX
4050
               && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
4051
               && !i.tm.opcode_modifier.ignoresize
4052
               && !i.tm.opcode_modifier.floatmf
4053
               && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4054
                   || (flag_code == CODE_64BIT
4055
                       && i.tm.opcode_modifier.jumpbyte)))
4056
        {
4057
          unsigned int prefix = DATA_PREFIX_OPCODE;
4058
 
4059
          if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
4060
            prefix = ADDR_PREFIX_OPCODE;
4061
 
4062
          if (!add_prefix (prefix))
4063
            return 0;
4064
        }
4065
 
4066
      /* Set mode64 for an operand.  */
4067
      if (i.suffix == QWORD_MNEM_SUFFIX
4068
          && flag_code == CODE_64BIT
4069
          && !i.tm.opcode_modifier.norex64)
4070
        {
4071
          /* Special case for xchg %rax,%rax.  It is NOP and doesn't
4072
             need rex64.  cmpxchg8b is also a special case. */
4073
          if (! (i.operands == 2
4074
                 && i.tm.base_opcode == 0x90
4075
                 && i.tm.extension_opcode == None
4076
                 && operand_type_equal (&i.types [0], &acc64)
4077
                 && operand_type_equal (&i.types [1], &acc64))
4078
              && ! (i.operands == 1
4079
                    && i.tm.base_opcode == 0xfc7
4080
                    && i.tm.extension_opcode == 1
4081
                    && !operand_type_check (i.types [0], reg)
4082
                    && operand_type_check (i.types [0], anymem)))
4083
            i.rex |= REX_W;
4084
        }
4085
 
4086
      /* Size floating point instruction.  */
4087
      if (i.suffix == LONG_MNEM_SUFFIX)
4088
        if (i.tm.opcode_modifier.floatmf)
4089
          i.tm.base_opcode ^= 4;
4090
    }
4091
 
4092
  return 1;
4093
}
4094
 
4095
static int
4096
check_byte_reg (void)
4097
{
4098
  int op;
4099
 
4100
  for (op = i.operands; --op >= 0;)
4101
    {
4102
      /* If this is an eight bit register, it's OK.  If it's the 16 or
4103
         32 bit version of an eight bit register, we will just use the
4104
         low portion, and that's OK too.  */
4105
      if (i.types[op].bitfield.reg8)
4106
        continue;
4107
 
4108
      /* Don't generate this warning if not needed.  */
4109
      if (intel_syntax && i.tm.opcode_modifier.byteokintel)
4110
        continue;
4111
 
4112
      /* crc32 doesn't generate this warning.  */
4113
      if (i.tm.base_opcode == 0xf20f38f0)
4114
        continue;
4115
 
4116
      if ((i.types[op].bitfield.reg16
4117
           || i.types[op].bitfield.reg32
4118
           || i.types[op].bitfield.reg64)
4119
          && i.op[op].regs->reg_num < 4)
4120
        {
4121
          /* Prohibit these changes in the 64bit mode, since the
4122
             lowering is more complicated.  */
4123
          if (flag_code == CODE_64BIT
4124
              && !i.tm.operand_types[op].bitfield.inoutportreg)
4125
            {
4126
              as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4127
                      register_prefix, i.op[op].regs->reg_name,
4128
                      i.suffix);
4129
              return 0;
4130
            }
4131
#if REGISTER_WARNINGS
4132
          if (!quiet_warnings
4133
              && !i.tm.operand_types[op].bitfield.inoutportreg)
4134
            as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4135
                     register_prefix,
4136
                     (i.op[op].regs + (i.types[op].bitfield.reg16
4137
                                       ? REGNAM_AL - REGNAM_AX
4138
                                       : REGNAM_AL - REGNAM_EAX))->reg_name,
4139
                     register_prefix,
4140
                     i.op[op].regs->reg_name,
4141
                     i.suffix);
4142
#endif
4143
          continue;
4144
        }
4145
      /* Any other register is bad.  */
4146
      if (i.types[op].bitfield.reg16
4147
          || i.types[op].bitfield.reg32
4148
          || i.types[op].bitfield.reg64
4149
          || i.types[op].bitfield.regmmx
4150
          || i.types[op].bitfield.regxmm
4151
          || i.types[op].bitfield.regymm
4152
          || i.types[op].bitfield.sreg2
4153
          || i.types[op].bitfield.sreg3
4154
          || i.types[op].bitfield.control
4155
          || i.types[op].bitfield.debug
4156
          || i.types[op].bitfield.test
4157
          || i.types[op].bitfield.floatreg
4158
          || i.types[op].bitfield.floatacc)
4159
        {
4160
          as_bad (_("`%s%s' not allowed with `%s%c'"),
4161
                  register_prefix,
4162
                  i.op[op].regs->reg_name,
4163
                  i.tm.name,
4164
                  i.suffix);
4165
          return 0;
4166
        }
4167
    }
4168
  return 1;
4169
}
4170
 
4171
static int
4172
check_long_reg (void)
4173
{
4174
  int op;
4175
 
4176
  for (op = i.operands; --op >= 0;)
4177
    /* Reject eight bit registers, except where the template requires
4178
       them. (eg. movzb)  */
4179
    if (i.types[op].bitfield.reg8
4180
        && (i.tm.operand_types[op].bitfield.reg16
4181
            || i.tm.operand_types[op].bitfield.reg32
4182
            || i.tm.operand_types[op].bitfield.acc))
4183
      {
4184
        as_bad (_("`%s%s' not allowed with `%s%c'"),
4185
                register_prefix,
4186
                i.op[op].regs->reg_name,
4187
                i.tm.name,
4188
                i.suffix);
4189
        return 0;
4190
      }
4191
  /* Warn if the e prefix on a general reg is missing.  */
4192
    else if ((!quiet_warnings || flag_code == CODE_64BIT)
4193
             && i.types[op].bitfield.reg16
4194
             && (i.tm.operand_types[op].bitfield.reg32
4195
                 || i.tm.operand_types[op].bitfield.acc))
4196
      {
4197
        /* Prohibit these changes in the 64bit mode, since the
4198
           lowering is more complicated.  */
4199
        if (flag_code == CODE_64BIT)
4200
          {
4201
            as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4202
                    register_prefix, i.op[op].regs->reg_name,
4203
                    i.suffix);
4204
            return 0;
4205
          }
4206
#if REGISTER_WARNINGS
4207
        else
4208
          as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4209
                   register_prefix,
4210
                   (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
4211
                   register_prefix,
4212
                   i.op[op].regs->reg_name,
4213
                   i.suffix);
4214
#endif
4215
      }
4216
  /* Warn if the r prefix on a general reg is missing.  */
4217
    else if (i.types[op].bitfield.reg64
4218
             && (i.tm.operand_types[op].bitfield.reg32
4219
                 || i.tm.operand_types[op].bitfield.acc))
4220
      {
4221
        if (intel_syntax
4222
            && i.tm.opcode_modifier.toqword
4223
            && !i.types[0].bitfield.regxmm)
4224
          {
4225
            /* Convert to QWORD.  We want REX byte. */
4226
            i.suffix = QWORD_MNEM_SUFFIX;
4227
          }
4228
        else
4229
          {
4230
            as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4231
                    register_prefix, i.op[op].regs->reg_name,
4232
                    i.suffix);
4233
            return 0;
4234
          }
4235
      }
4236
  return 1;
4237
}
4238
 
4239
static int
4240
check_qword_reg (void)
4241
{
4242
  int op;
4243
 
4244
  for (op = i.operands; --op >= 0; )
4245
    /* Reject eight bit registers, except where the template requires
4246
       them. (eg. movzb)  */
4247
    if (i.types[op].bitfield.reg8
4248
        && (i.tm.operand_types[op].bitfield.reg16
4249
            || i.tm.operand_types[op].bitfield.reg32
4250
            || i.tm.operand_types[op].bitfield.acc))
4251
      {
4252
        as_bad (_("`%s%s' not allowed with `%s%c'"),
4253
                register_prefix,
4254
                i.op[op].regs->reg_name,
4255
                i.tm.name,
4256
                i.suffix);
4257
        return 0;
4258
      }
4259
  /* Warn if the e prefix on a general reg is missing.  */
4260
    else if ((i.types[op].bitfield.reg16
4261
              || i.types[op].bitfield.reg32)
4262
             && (i.tm.operand_types[op].bitfield.reg32
4263
                 || i.tm.operand_types[op].bitfield.acc))
4264
      {
4265
        /* Prohibit these changes in the 64bit mode, since the
4266
           lowering is more complicated.  */
4267
        if (intel_syntax
4268
            && i.tm.opcode_modifier.todword
4269
            && !i.types[0].bitfield.regxmm)
4270
          {
4271
            /* Convert to DWORD.  We don't want REX byte. */
4272
            i.suffix = LONG_MNEM_SUFFIX;
4273
          }
4274
        else
4275
          {
4276
            as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4277
                    register_prefix, i.op[op].regs->reg_name,
4278
                    i.suffix);
4279
            return 0;
4280
          }
4281
      }
4282
  return 1;
4283
}
4284
 
4285
static int
4286
check_word_reg (void)
4287
{
4288
  int op;
4289
  for (op = i.operands; --op >= 0;)
4290
    /* Reject eight bit registers, except where the template requires
4291
       them. (eg. movzb)  */
4292
    if (i.types[op].bitfield.reg8
4293
        && (i.tm.operand_types[op].bitfield.reg16
4294
            || i.tm.operand_types[op].bitfield.reg32
4295
            || i.tm.operand_types[op].bitfield.acc))
4296
      {
4297
        as_bad (_("`%s%s' not allowed with `%s%c'"),
4298
                register_prefix,
4299
                i.op[op].regs->reg_name,
4300
                i.tm.name,
4301
                i.suffix);
4302
        return 0;
4303
      }
4304
  /* Warn if the e prefix on a general reg is present.  */
4305
    else if ((!quiet_warnings || flag_code == CODE_64BIT)
4306
             && i.types[op].bitfield.reg32
4307
             && (i.tm.operand_types[op].bitfield.reg16
4308
                 || i.tm.operand_types[op].bitfield.acc))
4309
      {
4310
        /* Prohibit these changes in the 64bit mode, since the
4311
           lowering is more complicated.  */
4312
        if (flag_code == CODE_64BIT)
4313
          {
4314
            as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4315
                    register_prefix, i.op[op].regs->reg_name,
4316
                    i.suffix);
4317
            return 0;
4318
          }
4319
        else
4320
#if REGISTER_WARNINGS
4321
          as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4322
                   register_prefix,
4323
                   (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
4324
                   register_prefix,
4325
                   i.op[op].regs->reg_name,
4326
                   i.suffix);
4327
#endif
4328
      }
4329
  return 1;
4330
}
4331
 
4332
static int
4333
update_imm (unsigned int j)
4334
{
4335
  i386_operand_type overlap;
4336
 
4337
  overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
4338
  if ((overlap.bitfield.imm8
4339
       || overlap.bitfield.imm8s
4340
       || overlap.bitfield.imm16
4341
       || overlap.bitfield.imm32
4342
       || overlap.bitfield.imm32s
4343
       || overlap.bitfield.imm64)
4344
      && !operand_type_equal (&overlap, &imm8)
4345
      && !operand_type_equal (&overlap, &imm8s)
4346
      && !operand_type_equal (&overlap, &imm16)
4347
      && !operand_type_equal (&overlap, &imm32)
4348
      && !operand_type_equal (&overlap, &imm32s)
4349
      && !operand_type_equal (&overlap, &imm64))
4350
    {
4351
      if (i.suffix)
4352
        {
4353
          i386_operand_type temp;
4354
 
4355
          operand_type_set (&temp, 0);
4356
          if (i.suffix == BYTE_MNEM_SUFFIX)
4357
            {
4358
              temp.bitfield.imm8 = overlap.bitfield.imm8;
4359
              temp.bitfield.imm8s = overlap.bitfield.imm8s;
4360
            }
4361
          else if (i.suffix == WORD_MNEM_SUFFIX)
4362
            temp.bitfield.imm16 = overlap.bitfield.imm16;
4363
          else if (i.suffix == QWORD_MNEM_SUFFIX)
4364
            {
4365
              temp.bitfield.imm64 = overlap.bitfield.imm64;
4366
              temp.bitfield.imm32s = overlap.bitfield.imm32s;
4367
            }
4368
          else
4369
            temp.bitfield.imm32 = overlap.bitfield.imm32;
4370
          overlap = temp;
4371
        }
4372
      else if (operand_type_equal (&overlap, &imm16_32_32s)
4373
               || operand_type_equal (&overlap, &imm16_32)
4374
               || operand_type_equal (&overlap, &imm16_32s))
4375
        {
4376
          if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4377
            overlap = imm16;
4378
          else
4379
            overlap = imm32s;
4380
        }
4381
      if (!operand_type_equal (&overlap, &imm8)
4382
          && !operand_type_equal (&overlap, &imm8s)
4383
          && !operand_type_equal (&overlap, &imm16)
4384
          && !operand_type_equal (&overlap, &imm32)
4385
          && !operand_type_equal (&overlap, &imm32s)
4386
          && !operand_type_equal (&overlap, &imm64))
4387
        {
4388
          as_bad (_("no instruction mnemonic suffix given; "
4389
                    "can't determine immediate size"));
4390
          return 0;
4391
        }
4392
    }
4393
  i.types[j] = overlap;
4394
 
4395
  return 1;
4396
}
4397
 
4398
static int
4399
finalize_imm (void)
4400
{
4401
  unsigned int j;
4402
 
4403
  for (j = 0; j < 2; j++)
4404
    if (update_imm (j) == 0)
4405
      return 0;
4406
 
4407
  i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
4408
  assert (operand_type_check (i.types[2], imm) == 0);
4409
 
4410
  return 1;
4411
}
4412
 
4413
static void
4414
process_drex (void)
4415
{
4416
  i.drex.modrm_reg = 0;
4417
  i.drex.modrm_regmem = 0;
4418
 
4419
  /* SSE5 4 operand instructions must have the destination the same as
4420
     one of the inputs.  Figure out the destination register and cache
4421
     it away in the drex field, and remember which fields to use for
4422
     the modrm byte.  */
4423
  if (i.tm.opcode_modifier.drex
4424
      && i.tm.opcode_modifier.drexv
4425
      && i.operands == 4)
4426
    {
4427
      i.tm.extension_opcode = None;
4428
 
4429
      /* Case 1: 4 operand insn, dest = src1, src3 = register.  */
4430
      if (i.types[0].bitfield.regxmm != 0
4431
          && i.types[1].bitfield.regxmm != 0
4432
          && i.types[2].bitfield.regxmm != 0
4433
          && i.types[3].bitfield.regxmm != 0
4434
          && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4435
          && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4436
        {
4437
          /* Clear the arguments that are stored in drex.  */
4438
          operand_type_set (&i.types[0], 0);
4439
          operand_type_set (&i.types[3], 0);
4440
          i.reg_operands -= 2;
4441
 
4442
          /* There are two different ways to encode a 4 operand
4443
             instruction with all registers that uses OC1 set to
4444
 
4445
             actions of other SSE5 assemblers.  Use modrm encoding 2
4446
             for register/register.  Include the high order bit that
4447
             is normally stored in the REX byte in the register
4448
             field.  */
4449
          i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4450
          i.drex.modrm_reg = 2;
4451
          i.drex.modrm_regmem = 1;
4452
          i.drex.reg = (i.op[3].regs->reg_num
4453
                        + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4454
        }
4455
 
4456
      /* Case 2: 4 operand insn, dest = src1, src3 = memory.  */
4457
      else if (i.types[0].bitfield.regxmm != 0
4458
               && i.types[1].bitfield.regxmm != 0
4459
               && (i.types[2].bitfield.regxmm
4460
                   || operand_type_check (i.types[2], anymem))
4461
               && i.types[3].bitfield.regxmm != 0
4462
               && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4463
               && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4464
        {
4465
          /* clear the arguments that are stored in drex */
4466
          operand_type_set (&i.types[0], 0);
4467
          operand_type_set (&i.types[3], 0);
4468
          i.reg_operands -= 2;
4469
 
4470
          /* Specify the modrm encoding for memory addressing.  Include
4471
             the high order bit that is normally stored in the REX byte
4472
             in the register field.  */
4473
          i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4474
          i.drex.modrm_reg = 1;
4475
          i.drex.modrm_regmem = 2;
4476
          i.drex.reg = (i.op[3].regs->reg_num
4477
                        + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4478
        }
4479
 
4480
      /* Case 3: 4 operand insn, dest = src1, src2 = memory.  */
4481
      else if (i.types[0].bitfield.regxmm != 0
4482
               && operand_type_check (i.types[1], anymem) != 0
4483
               && i.types[2].bitfield.regxmm != 0
4484
               && i.types[3].bitfield.regxmm != 0
4485
               && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4486
               && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4487
        {
4488
          /* Clear the arguments that are stored in drex.  */
4489
          operand_type_set (&i.types[0], 0);
4490
          operand_type_set (&i.types[3], 0);
4491
          i.reg_operands -= 2;
4492
 
4493
          /* Specify the modrm encoding for memory addressing.  Include
4494
             the high order bit that is normally stored in the REX byte
4495
             in the register field.  */
4496
          i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4497
          i.drex.modrm_reg = 2;
4498
          i.drex.modrm_regmem = 1;
4499
          i.drex.reg = (i.op[3].regs->reg_num
4500
                        + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4501
        }
4502
 
4503
      /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4504
      else if (i.types[0].bitfield.regxmm != 0
4505
               && i.types[1].bitfield.regxmm != 0
4506
               && i.types[2].bitfield.regxmm != 0
4507
               && i.types[3].bitfield.regxmm != 0
4508
               && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4509
               && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4510
        {
4511
          /* clear the arguments that are stored in drex */
4512
          operand_type_set (&i.types[2], 0);
4513
          operand_type_set (&i.types[3], 0);
4514
          i.reg_operands -= 2;
4515
 
4516
          /* There are two different ways to encode a 4 operand
4517
             instruction with all registers that uses OC1 set to
4518
 
4519
             actions of other SSE5 assemblers.  Use modrm encoding
4520
             2 for register/register.  Include the high order bit that
4521
             is normally stored in the REX byte in the register
4522
             field.  */
4523
          i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4524
          i.drex.modrm_reg = 1;
4525
          i.drex.modrm_regmem = 0;
4526
 
4527
          /* Remember the register, including the upper bits */
4528
          i.drex.reg = (i.op[3].regs->reg_num
4529
                        + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4530
        }
4531
 
4532
      /* Case 5: 4 operand insn, dest = src3, src2 = memory.  */
4533
      else if (i.types[0].bitfield.regxmm != 0
4534
               && (i.types[1].bitfield.regxmm
4535
                   || operand_type_check (i.types[1], anymem))
4536
               && i.types[2].bitfield.regxmm != 0
4537
               && i.types[3].bitfield.regxmm != 0
4538
               && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4539
               && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4540
        {
4541
          /* Clear the arguments that are stored in drex.  */
4542
          operand_type_set (&i.types[2], 0);
4543
          operand_type_set (&i.types[3], 0);
4544
          i.reg_operands -= 2;
4545
 
4546
          /* Specify the modrm encoding and remember the register
4547
             including the bits normally stored in the REX byte. */
4548
          i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4549
          i.drex.modrm_reg = 0;
4550
          i.drex.modrm_regmem = 1;
4551
          i.drex.reg = (i.op[3].regs->reg_num
4552
                        + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4553
        }
4554
 
4555
      /* Case 6: 4 operand insn, dest = src3, src1 = memory.  */
4556
      else if (operand_type_check (i.types[0], anymem) != 0
4557
               && i.types[1].bitfield.regxmm != 0
4558
               && i.types[2].bitfield.regxmm != 0
4559
               && i.types[3].bitfield.regxmm != 0
4560
               && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4561
               && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4562
        {
4563
          /* clear the arguments that are stored in drex */
4564
          operand_type_set (&i.types[2], 0);
4565
          operand_type_set (&i.types[3], 0);
4566
          i.reg_operands -= 2;
4567
 
4568
          /* Specify the modrm encoding and remember the register
4569
             including the bits normally stored in the REX byte. */
4570
          i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4571
          i.drex.modrm_reg = 1;
4572
          i.drex.modrm_regmem = 0;
4573
          i.drex.reg = (i.op[3].regs->reg_num
4574
                        + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4575
        }
4576
 
4577
      else
4578
        as_bad (_("Incorrect operands for the '%s' instruction"),
4579
                i.tm.name);
4580
    }
4581
 
4582
  /* SSE5 instructions with the DREX byte where the only memory operand
4583
     is in the 2nd argument, and the first and last xmm register must
4584
     match, and is encoded in the DREX byte. */
4585
  else if (i.tm.opcode_modifier.drex
4586
           && !i.tm.opcode_modifier.drexv
4587
           && i.operands == 4)
4588
    {
4589
      /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem.  */
4590
      if (i.types[0].bitfield.regxmm != 0
4591
          && (i.types[1].bitfield.regxmm
4592
              || operand_type_check(i.types[1], anymem))
4593
          && i.types[2].bitfield.regxmm != 0
4594
          && i.types[3].bitfield.regxmm != 0
4595
          && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4596
          && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4597
        {
4598
          /* clear the arguments that are stored in drex */
4599
          operand_type_set (&i.types[0], 0);
4600
          operand_type_set (&i.types[3], 0);
4601
          i.reg_operands -= 2;
4602
 
4603
          /* Specify the modrm encoding and remember the register
4604
             including the high bit normally stored in the REX
4605
             byte.  */
4606
          i.drex.modrm_reg = 2;
4607
          i.drex.modrm_regmem = 1;
4608
          i.drex.reg = (i.op[3].regs->reg_num
4609
                        + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4610
        }
4611
 
4612
      else
4613
        as_bad (_("Incorrect operands for the '%s' instruction"),
4614
                i.tm.name);
4615
    }
4616
 
4617
  /* SSE5 3 operand instructions that the result is a register, being
4618
     either operand can be a memory operand, using OC0 to note which
4619
     one is the memory.  */
4620
  else if (i.tm.opcode_modifier.drex
4621
           && i.tm.opcode_modifier.drexv
4622
           && i.operands == 3)
4623
    {
4624
      i.tm.extension_opcode = None;
4625
 
4626
      /* Case 1: 3 operand insn, src1 = register.  */
4627
      if (i.types[0].bitfield.regxmm != 0
4628
          && i.types[1].bitfield.regxmm != 0
4629
          && i.types[2].bitfield.regxmm != 0)
4630
        {
4631
          /* Clear the arguments that are stored in drex.  */
4632
          operand_type_set (&i.types[2], 0);
4633
          i.reg_operands--;
4634
 
4635
          /* Specify the modrm encoding and remember the register
4636
             including the high bit normally stored in the REX byte.  */
4637
          i.tm.extension_opcode = DREX_XMEM_X1_X2;
4638
          i.drex.modrm_reg = 1;
4639
          i.drex.modrm_regmem = 0;
4640
          i.drex.reg = (i.op[2].regs->reg_num
4641
                        + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4642
        }
4643
 
4644
      /* Case 2: 3 operand insn, src1 = memory.  */
4645
      else if (operand_type_check (i.types[0], anymem) != 0
4646
               && i.types[1].bitfield.regxmm != 0
4647
               && i.types[2].bitfield.regxmm != 0)
4648
        {
4649
          /* Clear the arguments that are stored in drex.  */
4650
          operand_type_set (&i.types[2], 0);
4651
          i.reg_operands--;
4652
 
4653
          /* Specify the modrm encoding and remember the register
4654
             including the high bit normally stored in the REX
4655
             byte.  */
4656
          i.tm.extension_opcode = DREX_XMEM_X1_X2;
4657
          i.drex.modrm_reg = 1;
4658
          i.drex.modrm_regmem = 0;
4659
          i.drex.reg = (i.op[2].regs->reg_num
4660
                        + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4661
        }
4662
 
4663
      /* Case 3: 3 operand insn, src2 = memory.  */
4664
      else if (i.types[0].bitfield.regxmm != 0
4665
               && operand_type_check (i.types[1], anymem) != 0
4666
               && i.types[2].bitfield.regxmm != 0)
4667
        {
4668
          /* Clear the arguments that are stored in drex.  */
4669
          operand_type_set (&i.types[2], 0);
4670
          i.reg_operands--;
4671
 
4672
          /* Specify the modrm encoding and remember the register
4673
             including the high bit normally stored in the REX byte.  */
4674
          i.tm.extension_opcode = DREX_X1_XMEM_X2;
4675
          i.drex.modrm_reg = 0;
4676
          i.drex.modrm_regmem = 1;
4677
          i.drex.reg = (i.op[2].regs->reg_num
4678
                        + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4679
        }
4680
 
4681
      else
4682
        as_bad (_("Incorrect operands for the '%s' instruction"),
4683
                i.tm.name);
4684
    }
4685
 
4686
  /* SSE5 4 operand instructions that are the comparison instructions
4687
     where the first operand is the immediate value of the comparison
4688
     to be done.  */
4689
  else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4690
    {
4691
      /* Case 1: 4 operand insn, src1 = reg/memory. */
4692
      if (operand_type_check (i.types[0], imm) != 0
4693
          && (i.types[1].bitfield.regxmm
4694
              || operand_type_check (i.types[1], anymem))
4695
          && i.types[2].bitfield.regxmm != 0
4696
          && i.types[3].bitfield.regxmm != 0)
4697
        {
4698
          /* clear the arguments that are stored in drex */
4699
          operand_type_set (&i.types[3], 0);
4700
          i.reg_operands--;
4701
 
4702
          /* Specify the modrm encoding and remember the register
4703
             including the high bit normally stored in the REX byte.  */
4704
          i.drex.modrm_reg = 2;
4705
          i.drex.modrm_regmem = 1;
4706
          i.drex.reg = (i.op[3].regs->reg_num
4707
                        + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4708
        }
4709
 
4710
      /* Case 2: 3 operand insn with ImmExt that places the
4711
         opcode_extension as an immediate argument.  This is used for
4712
         all of the varients of comparison that supplies the appropriate
4713
         value as part of the instruction.  */
4714
      else if ((i.types[0].bitfield.regxmm
4715
                || operand_type_check (i.types[0], anymem))
4716
               && i.types[1].bitfield.regxmm != 0
4717
               && i.types[2].bitfield.regxmm != 0
4718
               && operand_type_check (i.types[3], imm) != 0)
4719
        {
4720
          /* clear the arguments that are stored in drex */
4721
          operand_type_set (&i.types[2], 0);
4722
          i.reg_operands--;
4723
 
4724
          /* Specify the modrm encoding and remember the register
4725
             including the high bit normally stored in the REX byte.  */
4726
          i.drex.modrm_reg = 1;
4727
          i.drex.modrm_regmem = 0;
4728
          i.drex.reg = (i.op[2].regs->reg_num
4729
                        + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4730
        }
4731
 
4732
      else
4733
        as_bad (_("Incorrect operands for the '%s' instruction"),
4734
                i.tm.name);
4735
    }
4736
 
4737
  else if (i.tm.opcode_modifier.drex
4738
           || i.tm.opcode_modifier.drexv
4739
           || i.tm.opcode_modifier.drexc)
4740
    as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4741
}
4742
 
4743
static int
4744
bad_implicit_operand (int xmm)
4745
{
4746
  const char *reg = xmm ? "xmm0" : "ymm0";
4747
  if (intel_syntax)
4748
    as_bad (_("the last operand of `%s' must be `%s%s'"),
4749
            i.tm.name, register_prefix, reg);
4750
  else
4751
    as_bad (_("the first operand of `%s' must be `%s%s'"),
4752
            i.tm.name, register_prefix, reg);
4753
  return 0;
4754
}
4755
 
4756
static int
4757
process_operands (void)
4758
{
4759
  /* Default segment register this instruction will use for memory
4760
     accesses.  0 means unknown.  This is only for optimizing out
4761
     unnecessary segment overrides.  */
4762
  const seg_entry *default_seg = 0;
4763
 
4764
  /* Handle all of the DREX munging that SSE5 needs.  */
4765
  if (i.tm.opcode_modifier.drex
4766
      || i.tm.opcode_modifier.drexv
4767
      || i.tm.opcode_modifier.drexc)
4768
    process_drex ();
4769
 
4770
  if (i.tm.opcode_modifier.sse2avx
4771
      && (i.tm.opcode_modifier.vexnds
4772
          || i.tm.opcode_modifier.vexndd))
4773
    {
4774
      unsigned int dup = i.operands;
4775
      unsigned int dest = dup - 1;
4776
      unsigned int j;
4777
 
4778
      /* The destination must be an xmm register.  */
4779
      assert (i.reg_operands
4780
              && MAX_OPERANDS > dup
4781
              && operand_type_equal (&i.types[dest], &regxmm));
4782
 
4783
      if (i.tm.opcode_modifier.firstxmm0)
4784
        {
4785
          /* The first operand is implicit and must be xmm0.  */
4786
          assert (operand_type_equal (&i.types[0], &regxmm));
4787
          if (i.op[0].regs->reg_num != 0)
4788
            return bad_implicit_operand (1);
4789
 
4790
          if (i.tm.opcode_modifier.vex3sources)
4791
            {
4792
              /* Keep xmm0 for instructions with VEX prefix and 3
4793
                 sources.  */
4794
              goto duplicate;
4795
            }
4796
          else
4797
            {
4798
              /* We remove the first xmm0 and keep the number of
4799
                 operands unchanged, which in fact duplicates the
4800
                 destination.  */
4801
              for (j = 1; j < i.operands; j++)
4802
                {
4803
                  i.op[j - 1] = i.op[j];
4804
                  i.types[j - 1] = i.types[j];
4805
                  i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4806
                }
4807
            }
4808
        }
4809
      else if (i.tm.opcode_modifier.implicit1stxmm0)
4810
        {
4811
          assert ((MAX_OPERANDS - 1) > dup
4812
                  && i.tm.opcode_modifier.vex3sources);
4813
 
4814
          /* Add the implicit xmm0 for instructions with VEX prefix
4815
             and 3 sources.  */
4816
          for (j = i.operands; j > 0; j--)
4817
            {
4818
              i.op[j] = i.op[j - 1];
4819
              i.types[j] = i.types[j - 1];
4820
              i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4821
            }
4822
          i.op[0].regs
4823
            = (const reg_entry *) hash_find (reg_hash, "xmm0");
4824
          i.types[0] = regxmm;
4825
          i.tm.operand_types[0] = regxmm;
4826
 
4827
          i.operands += 2;
4828
          i.reg_operands += 2;
4829
          i.tm.operands += 2;
4830
 
4831
          dup++;
4832
          dest++;
4833
          i.op[dup] = i.op[dest];
4834
          i.types[dup] = i.types[dest];
4835
          i.tm.operand_types[dup] = i.tm.operand_types[dest];
4836
        }
4837
      else
4838
        {
4839
duplicate:
4840
          i.operands++;
4841
          i.reg_operands++;
4842
          i.tm.operands++;
4843
 
4844
          i.op[dup] = i.op[dest];
4845
          i.types[dup] = i.types[dest];
4846
          i.tm.operand_types[dup] = i.tm.operand_types[dest];
4847
        }
4848
 
4849
       if (i.tm.opcode_modifier.immext)
4850
         process_immext ();
4851
    }
4852
  else if (i.tm.opcode_modifier.firstxmm0)
4853
    {
4854
      unsigned int j;
4855
 
4856
      /* The first operand is implicit and must be xmm0/ymm0.  */
4857
      assert (i.reg_operands
4858
              && (operand_type_equal (&i.types[0], &regxmm)
4859
                  || operand_type_equal (&i.types[0], &regymm)));
4860
      if (i.op[0].regs->reg_num != 0)
4861
        return bad_implicit_operand (i.types[0].bitfield.regxmm);
4862
 
4863
      for (j = 1; j < i.operands; j++)
4864
        {
4865
          i.op[j - 1] = i.op[j];
4866
          i.types[j - 1] = i.types[j];
4867
 
4868
          /* We need to adjust fields in i.tm since they are used by
4869
             build_modrm_byte.  */
4870
          i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4871
        }
4872
 
4873
      i.operands--;
4874
      i.reg_operands--;
4875
      i.tm.operands--;
4876
    }
4877
  else if (i.tm.opcode_modifier.regkludge)
4878
    {
4879
      /* The imul $imm, %reg instruction is converted into
4880
         imul $imm, %reg, %reg, and the clr %reg instruction
4881
         is converted into xor %reg, %reg.  */
4882
 
4883
      unsigned int first_reg_op;
4884
 
4885
      if (operand_type_check (i.types[0], reg))
4886
        first_reg_op = 0;
4887
      else
4888
        first_reg_op = 1;
4889
      /* Pretend we saw the extra register operand.  */
4890
      assert (i.reg_operands == 1
4891
              && i.op[first_reg_op + 1].regs == 0);
4892
      i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4893
      i.types[first_reg_op + 1] = i.types[first_reg_op];
4894
      i.operands++;
4895
      i.reg_operands++;
4896
    }
4897
 
4898
  if (i.tm.opcode_modifier.shortform)
4899
    {
4900
      if (i.types[0].bitfield.sreg2
4901
          || i.types[0].bitfield.sreg3)
4902
        {
4903
          if (i.tm.base_opcode == POP_SEG_SHORT
4904
              && i.op[0].regs->reg_num == 1)
4905
            {
4906
              as_bad (_("you can't `pop %%cs'"));
4907
              return 0;
4908
            }
4909
          i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4910
          if ((i.op[0].regs->reg_flags & RegRex) != 0)
4911
            i.rex |= REX_B;
4912
        }
4913
      else
4914
        {
4915
          /* The register or float register operand is in operand
4916
 
4917
          unsigned int op;
4918
 
4919
           if (i.types[0].bitfield.floatreg
4920
               || operand_type_check (i.types[0], reg))
4921
             op = 0;
4922
           else
4923
             op = 1;
4924
          /* Register goes in low 3 bits of opcode.  */
4925
          i.tm.base_opcode |= i.op[op].regs->reg_num;
4926
          if ((i.op[op].regs->reg_flags & RegRex) != 0)
4927
            i.rex |= REX_B;
4928
          if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4929
            {
4930
              /* Warn about some common errors, but press on regardless.
4931
                 The first case can be generated by gcc (<= 2.8.1).  */
4932
              if (i.operands == 2)
4933
                {
4934
                  /* Reversed arguments on faddp, fsubp, etc.  */
4935
                  as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4936
                           register_prefix, i.op[1].regs->reg_name,
4937
                           register_prefix, i.op[0].regs->reg_name);
4938
                }
4939
              else
4940
                {
4941
                  /* Extraneous `l' suffix on fp insn.  */
4942
                  as_warn (_("translating to `%s %s%s'"), i.tm.name,
4943
                           register_prefix, i.op[0].regs->reg_name);
4944
                }
4945
            }
4946
        }
4947
    }
4948
  else if (i.tm.opcode_modifier.modrm)
4949
    {
4950
      /* The opcode is completed (modulo i.tm.extension_opcode which
4951
         must be put into the modrm byte).  Now, we make the modrm and
4952
         index base bytes based on all the info we've collected.  */
4953
 
4954
      default_seg = build_modrm_byte ();
4955
    }
4956
  else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4957
    {
4958
      default_seg = &ds;
4959
    }
4960
  else if (i.tm.opcode_modifier.isstring)
4961
    {
4962
      /* For the string instructions that allow a segment override
4963
         on one of their operands, the default segment is ds.  */
4964
      default_seg = &ds;
4965
    }
4966
 
4967
  if (i.tm.base_opcode == 0x8d /* lea */
4968
      && i.seg[0]
4969
      && !quiet_warnings)
4970
    as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4971
 
4972
  /* If a segment was explicitly specified, and the specified segment
4973
     is not the default, use an opcode prefix to select it.  If we
4974
     never figured out what the default segment is, then default_seg
4975
     will be zero at this point, and the specified segment prefix will
4976
     always be used.  */
4977
  if ((i.seg[0]) && (i.seg[0] != default_seg))
4978
    {
4979
      if (!add_prefix (i.seg[0]->seg_prefix))
4980
        return 0;
4981
    }
4982
  return 1;
4983
}
4984
 
4985
static const seg_entry *
4986
build_modrm_byte (void)
4987
{
4988
  const seg_entry *default_seg = 0;
4989
  unsigned int source, dest;
4990
  int vex_3_sources;
4991
 
4992
  /* The first operand of instructions with VEX prefix and 3 sources
4993
     must be VEX_Imm4.  */
4994
  vex_3_sources = i.tm.opcode_modifier.vex3sources;
4995
  if (vex_3_sources)
4996
    {
4997
      unsigned int nds, reg;
4998
 
4999
      if (i.tm.opcode_modifier.veximmext
5000
          && i.tm.opcode_modifier.immext)
5001
        {
5002
          dest = i.operands - 2;
5003
          assert (dest == 3);
5004
        }
5005
      else
5006
        dest = i.operands - 1;
5007
      nds = dest - 1;
5008
 
5009
      /* There are 2 kinds of instructions:
5010
            1. 5 operands: one immediate operand and 4 register
5011
            operands or 3 register operands plus 1 memory operand.
5012
            It must have VexNDS and VexW0 or VexW1.  The destination
5013
            must be either XMM or YMM register.
5014
            2. 4 operands: 4 register operands or 3 register operands
5015
            plus 1 memory operand.  It must have VexNDS and VexImmExt.  */
5016
      if (!((i.reg_operands == 4
5017
             || (i.reg_operands == 3 && i.mem_operands == 1))
5018
            && i.tm.opcode_modifier.vexnds
5019
            && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5020
                || operand_type_equal (&i.tm.operand_types[dest], &regymm))
5021
            && ((dest == 4
5022
                 && i.imm_operands == 1
5023
                 && i.types[0].bitfield.vex_imm4
5024
                 && (i.tm.opcode_modifier.vexw0
5025
                     || i.tm.opcode_modifier.vexw1))
5026
                || (dest == 3
5027
                    && (i.imm_operands == 0
5028
                        || (i.imm_operands == 1
5029
                            && i.tm.opcode_modifier.immext))
5030
                    && i.tm.opcode_modifier.veximmext))))
5031
        abort ();
5032
 
5033
      if (i.imm_operands == 0)
5034
        {
5035
          /* When there is no immediate operand, generate an 8bit
5036
             immediate operand to encode the first operand.  */
5037
          expressionS *exp = &im_expressions[i.imm_operands++];
5038
          i.op[i.operands].imms = exp;
5039
          i.types[i.operands] = imm8;
5040
          i.operands++;
5041
          /* If VexW1 is set, the first operand is the source and
5042
             the second operand is encoded in the immediate operand.  */
5043
          if (i.tm.opcode_modifier.vexw1)
5044
            {
5045
              source = 0;
5046
              reg = 1;
5047
            }
5048
          else
5049
            {
5050
              source = 1;
5051
              reg = 0;
5052
            }
5053
 
5054
          /* FMA swaps REG and NDS.  */
5055
          if (i.tm.cpu_flags.bitfield.cpufma)
5056
            {
5057
              unsigned int tmp;
5058
              tmp = reg;
5059
              reg = nds;
5060
              nds = tmp;
5061
            }
5062
 
5063
          assert (operand_type_equal (&i.tm.operand_types[reg], &regxmm)
5064
                  || operand_type_equal (&i.tm.operand_types[reg],
5065
                                         &regymm));
5066
          exp->X_op = O_constant;
5067
          exp->X_add_number
5068
            = ((i.op[reg].regs->reg_num
5069
                + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5070
        }
5071
      else
5072
        {
5073
          unsigned int imm;
5074
 
5075
          if (i.tm.opcode_modifier.vexw0)
5076
            {
5077
              /* If VexW0 is set, the third operand is the source and
5078
                 the second operand is encoded in the immediate
5079
                 operand.  */
5080
              source = 2;
5081
              reg = 1;
5082
            }
5083
          else
5084
            {
5085
              /* VexW1 is set, the second operand is the source and
5086
                 the third operand is encoded in the immediate
5087
                 operand.  */
5088
              source = 1;
5089
              reg = 2;
5090
            }
5091
 
5092
          if (i.tm.opcode_modifier.immext)
5093
            {
5094
              /* When ImmExt is set, the immdiate byte is the last
5095
                 operand.  */
5096
              imm = i.operands - 1;
5097
              source--;
5098
              reg--;
5099
            }
5100
          else
5101
            {
5102
              imm = 0;
5103
 
5104
              /* Turn on Imm8 so that output_imm will generate it.  */
5105
              i.types[imm].bitfield.imm8 = 1;
5106
            }
5107
 
5108
          assert (operand_type_equal (&i.tm.operand_types[reg], &regxmm)
5109
                  || operand_type_equal (&i.tm.operand_types[reg],
5110
                                         &regymm));
5111
          i.op[imm].imms->X_add_number
5112
            |= ((i.op[reg].regs->reg_num
5113
                 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5114
        }
5115
 
5116
      assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5117
              || operand_type_equal (&i.tm.operand_types[nds], &regymm));
5118
      i.vex.register_specifier = i.op[nds].regs;
5119
 
5120
    }
5121
  else
5122
    source = dest = 0;
5123
 
5124
  /* SSE5 4 operand instructions are encoded in such a way that one of
5125
     the inputs must match the destination register.  Process_drex hides
5126
     the 3rd argument in the drex field, so that by the time we get
5127
     here, it looks to GAS as if this is a 2 operand instruction.  */
5128
  if ((i.tm.opcode_modifier.drex
5129
       || i.tm.opcode_modifier.drexv
5130
       || i.tm.opcode_modifier.drexc)
5131
      && i.reg_operands == 2)
5132
    {
5133
      const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5134
      const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5135
 
5136
      i.rm.reg = reg->reg_num;
5137
      i.rm.regmem = regmem->reg_num;
5138
      i.rm.mode = 3;
5139
      if ((reg->reg_flags & RegRex) != 0)
5140
        i.rex |= REX_R;
5141
      if ((regmem->reg_flags & RegRex) != 0)
5142
        i.rex |= REX_B;
5143
    }
5144
 
5145
  /* i.reg_operands MUST be the number of real register operands;
5146
     implicit registers do not count.  If there are 3 register
5147
     operands, it must be a instruction with VexNDS.  For a
5148
     instruction with VexNDD, the destination register is encoded
5149
     in VEX prefix.  If there are 4 register operands, it must be
5150
     a instruction with VEX prefix and 3 sources.  */
5151
  else if (i.mem_operands == 0
5152
           && ((i.reg_operands == 2
5153
                && !i.tm.opcode_modifier.vexndd)
5154
               || (i.reg_operands == 3
5155
                   && i.tm.opcode_modifier.vexnds)
5156
               || (i.reg_operands == 4 && vex_3_sources)))
5157
    {
5158
      switch (i.operands)
5159
        {
5160
        case 2:
5161
          source = 0;
5162
          break;
5163
        case 3:
5164
          /* When there are 3 operands, one of them may be immediate,
5165
             which may be the first or the last operand.  Otherwise,
5166
             the first operand must be shift count register (cl) or it
5167
             is an instruction with VexNDS. */
5168
          assert (i.imm_operands == 1
5169
                  || (i.imm_operands == 0
5170
                      && (i.tm.opcode_modifier.vexnds
5171
                          || i.types[0].bitfield.shiftcount)));
5172
          if (operand_type_check (i.types[0], imm)
5173
              || i.types[0].bitfield.shiftcount)
5174
            source = 1;
5175
          else
5176
            source = 0;
5177
          break;
5178
        case 4:
5179
          /* When there are 4 operands, the first two must be 8bit
5180
             immediate operands. The source operand will be the 3rd
5181
             one.
5182
 
5183
             For instructions with VexNDS, if the first operand
5184
             an imm8, the source operand is the 2nd one.  If the last
5185
             operand is imm8, the source operand is the first one.  */
5186
          assert ((i.imm_operands == 2
5187
                   && i.types[0].bitfield.imm8
5188
                   && i.types[1].bitfield.imm8)
5189
                  || (i.tm.opcode_modifier.vexnds
5190
                      && i.imm_operands == 1
5191
                      && (i.types[0].bitfield.imm8
5192
                          || i.types[i.operands - 1].bitfield.imm8)));
5193
          if (i.tm.opcode_modifier.vexnds)
5194
            {
5195
              if (i.types[0].bitfield.imm8)
5196
                source = 1;
5197
              else
5198
                source = 0;
5199
            }
5200
          else
5201
            source = 2;
5202
          break;
5203
        case 5:
5204
          break;
5205
        default:
5206
          abort ();
5207
        }
5208
 
5209
      if (!vex_3_sources)
5210
        {
5211
          dest = source + 1;
5212
 
5213
          if (i.tm.opcode_modifier.vexnds)
5214
            {
5215
              /* For instructions with VexNDS, the register-only
5216
                 source operand must be XMM or YMM register. It is
5217
                 encoded in VEX prefix.  */
5218
              if ((dest + 1) >= i.operands
5219
                  || (!operand_type_equal (&i.tm.operand_types[dest],
5220
                                           &regxmm)
5221
                      && !operand_type_equal (&i.tm.operand_types[dest],
5222
                                              &regymm)))
5223
                abort ();
5224
              i.vex.register_specifier = i.op[dest].regs;
5225
              dest++;
5226
            }
5227
        }
5228
 
5229
      i.rm.mode = 3;
5230
      /* One of the register operands will be encoded in the i.tm.reg
5231
         field, the other in the combined i.tm.mode and i.tm.regmem
5232
         fields.  If no form of this instruction supports a memory
5233
         destination operand, then we assume the source operand may
5234
         sometimes be a memory operand and so we need to store the
5235
         destination in the i.rm.reg field.  */
5236
      if (!i.tm.operand_types[dest].bitfield.regmem
5237
          && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
5238
        {
5239
          i.rm.reg = i.op[dest].regs->reg_num;
5240
          i.rm.regmem = i.op[source].regs->reg_num;
5241
          if ((i.op[dest].regs->reg_flags & RegRex) != 0)
5242
            i.rex |= REX_R;
5243
          if ((i.op[source].regs->reg_flags & RegRex) != 0)
5244
            i.rex |= REX_B;
5245
        }
5246
      else
5247
        {
5248
          i.rm.reg = i.op[source].regs->reg_num;
5249
          i.rm.regmem = i.op[dest].regs->reg_num;
5250
          if ((i.op[dest].regs->reg_flags & RegRex) != 0)
5251
            i.rex |= REX_B;
5252
          if ((i.op[source].regs->reg_flags & RegRex) != 0)
5253
            i.rex |= REX_R;
5254
        }
5255
      if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
5256
        {
5257
          if (!i.types[0].bitfield.control
5258
              && !i.types[1].bitfield.control)
5259
            abort ();
5260
          i.rex &= ~(REX_R | REX_B);
5261
          add_prefix (LOCK_PREFIX_OPCODE);
5262
        }
5263
    }
5264
  else
5265
    {                   /* If it's not 2 reg operands...  */
5266
      unsigned int mem;
5267
 
5268
      if (i.mem_operands)
5269
        {
5270
          unsigned int fake_zero_displacement = 0;
5271
          unsigned int op;
5272
 
5273
          /* This has been precalculated for SSE5 instructions
5274
             that have a DREX field earlier in process_drex.  */
5275
          if (i.tm.opcode_modifier.drex
5276
              || i.tm.opcode_modifier.drexv
5277
              || i.tm.opcode_modifier.drexc)
5278
            op = i.drex.modrm_regmem;
5279
          else
5280
            {
5281
              for (op = 0; op < i.operands; op++)
5282
                if (operand_type_check (i.types[op], anymem))
5283
                  break;
5284
              assert (op < i.operands);
5285
            }
5286
 
5287
          default_seg = &ds;
5288
 
5289
          if (i.base_reg == 0)
5290
            {
5291
              i.rm.mode = 0;
5292
              if (!i.disp_operands)
5293
                fake_zero_displacement = 1;
5294
              if (i.index_reg == 0)
5295
                {
5296
                  /* Operand is just <disp>  */
5297
                  if (flag_code == CODE_64BIT)
5298
                    {
5299
                      /* 64bit mode overwrites the 32bit absolute
5300
                         addressing by RIP relative addressing and
5301
                         absolute addressing is encoded by one of the
5302
                         redundant SIB forms.  */
5303
                      i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5304
                      i.sib.base = NO_BASE_REGISTER;
5305
                      i.sib.index = NO_INDEX_REGISTER;
5306
                      i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
5307
                                     ? disp32s : disp32);
5308
                    }
5309
                  else if ((flag_code == CODE_16BIT)
5310
                           ^ (i.prefix[ADDR_PREFIX] != 0))
5311
                    {
5312
                      i.rm.regmem = NO_BASE_REGISTER_16;
5313
                      i.types[op] = disp16;
5314
                    }
5315
                  else
5316
                    {
5317
                      i.rm.regmem = NO_BASE_REGISTER;
5318
                      i.types[op] = disp32;
5319
                    }
5320
                }
5321
              else /* !i.base_reg && i.index_reg  */
5322
                {
5323
                  if (i.index_reg->reg_num == RegEiz
5324
                      || i.index_reg->reg_num == RegRiz)
5325
                    i.sib.index = NO_INDEX_REGISTER;
5326
                  else
5327
                    i.sib.index = i.index_reg->reg_num;
5328
                  i.sib.base = NO_BASE_REGISTER;
5329
                  i.sib.scale = i.log2_scale_factor;
5330
                  i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5331
                  i.types[op].bitfield.disp8 = 0;
5332
                  i.types[op].bitfield.disp16 = 0;
5333
                  i.types[op].bitfield.disp64 = 0;
5334
                  if (flag_code != CODE_64BIT)
5335
                    {
5336
                      /* Must be 32 bit */
5337
                      i.types[op].bitfield.disp32 = 1;
5338
                      i.types[op].bitfield.disp32s = 0;
5339
                    }
5340
                  else
5341
                    {
5342
                      i.types[op].bitfield.disp32 = 0;
5343
                      i.types[op].bitfield.disp32s = 1;
5344
                    }
5345
                  if ((i.index_reg->reg_flags & RegRex) != 0)
5346
                    i.rex |= REX_X;
5347
                }
5348
            }
5349
          /* RIP addressing for 64bit mode.  */
5350
          else if (i.base_reg->reg_num == RegRip ||
5351
                   i.base_reg->reg_num == RegEip)
5352
            {
5353
              i.rm.regmem = NO_BASE_REGISTER;
5354
              i.types[op].bitfield.disp8 = 0;
5355
              i.types[op].bitfield.disp16 = 0;
5356
              i.types[op].bitfield.disp32 = 0;
5357
              i.types[op].bitfield.disp32s = 1;
5358
              i.types[op].bitfield.disp64 = 0;
5359
              i.flags[op] |= Operand_PCrel;
5360
              if (! i.disp_operands)
5361
                fake_zero_displacement = 1;
5362
            }
5363
          else if (i.base_reg->reg_type.bitfield.reg16)
5364
            {
5365
              switch (i.base_reg->reg_num)
5366
                {
5367
                case 3: /* (%bx)  */
5368
                  if (i.index_reg == 0)
5369
                    i.rm.regmem = 7;
5370
                  else /* (%bx,%si) -> 0, or (%bx,%di) -> 1  */
5371
                    i.rm.regmem = i.index_reg->reg_num - 6;
5372
                  break;
5373
                case 5: /* (%bp)  */
5374
                  default_seg = &ss;
5375
                  if (i.index_reg == 0)
5376
                    {
5377
                      i.rm.regmem = 6;
5378
                      if (operand_type_check (i.types[op], disp) == 0)
5379
                        {
5380
                          /* fake (%bp) into 0(%bp)  */
5381
                          i.types[op].bitfield.disp8 = 1;
5382
                          fake_zero_displacement = 1;
5383
                        }
5384
                    }
5385
                  else /* (%bp,%si) -> 2, or (%bp,%di) -> 3  */
5386
                    i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5387
                  break;
5388
                default: /* (%si) -> 4 or (%di) -> 5  */
5389
                  i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5390
                }
5391
              i.rm.mode = mode_from_disp_size (i.types[op]);
5392
            }
5393
          else /* i.base_reg and 32/64 bit mode  */
5394
            {
5395
              if (flag_code == CODE_64BIT
5396
                  && operand_type_check (i.types[op], disp))
5397
                {
5398
                  i386_operand_type temp;
5399
                  operand_type_set (&temp, 0);
5400
                  temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5401
                  i.types[op] = temp;
5402
                  if (i.prefix[ADDR_PREFIX] == 0)
5403
                    i.types[op].bitfield.disp32s = 1;
5404
                  else
5405
                    i.types[op].bitfield.disp32 = 1;
5406
                }
5407
 
5408
              i.rm.regmem = i.base_reg->reg_num;
5409
              if ((i.base_reg->reg_flags & RegRex) != 0)
5410
                i.rex |= REX_B;
5411
              i.sib.base = i.base_reg->reg_num;
5412
              /* x86-64 ignores REX prefix bit here to avoid decoder
5413
                 complications.  */
5414
              if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5415
                {
5416
                  default_seg = &ss;
5417
                  if (i.disp_operands == 0)
5418
                    {
5419
                      fake_zero_displacement = 1;
5420
                      i.types[op].bitfield.disp8 = 1;
5421
                    }
5422
                }
5423
              else if (i.base_reg->reg_num == ESP_REG_NUM)
5424
                {
5425
                  default_seg = &ss;
5426
                }
5427
              i.sib.scale = i.log2_scale_factor;
5428
              if (i.index_reg == 0)
5429
                {
5430
                  /* <disp>(%esp) becomes two byte modrm with no index
5431
                     register.  We've already stored the code for esp
5432
                     in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5433
                     Any base register besides %esp will not use the
5434
                     extra modrm byte.  */
5435
                  i.sib.index = NO_INDEX_REGISTER;
5436
                }
5437
              else
5438
                {
5439
                  if (i.index_reg->reg_num == RegEiz
5440
                      || i.index_reg->reg_num == RegRiz)
5441
                    i.sib.index = NO_INDEX_REGISTER;
5442
                  else
5443
                    i.sib.index = i.index_reg->reg_num;
5444
                  i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5445
                  if ((i.index_reg->reg_flags & RegRex) != 0)
5446
                    i.rex |= REX_X;
5447
                }
5448
 
5449
              if (i.disp_operands
5450
                  && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5451
                      || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5452
                i.rm.mode = 0;
5453
              else
5454
                i.rm.mode = mode_from_disp_size (i.types[op]);
5455
            }
5456
 
5457
          if (fake_zero_displacement)
5458
            {
5459
              /* Fakes a zero displacement assuming that i.types[op]
5460
                 holds the correct displacement size.  */
5461
              expressionS *exp;
5462
 
5463
              assert (i.op[op].disps == 0);
5464
              exp = &disp_expressions[i.disp_operands++];
5465
              i.op[op].disps = exp;
5466
              exp->X_op = O_constant;
5467
              exp->X_add_number = 0;
5468
              exp->X_add_symbol = (symbolS *) 0;
5469
              exp->X_op_symbol = (symbolS *) 0;
5470
            }
5471
 
5472
          mem = op;
5473
        }
5474
      else
5475
        mem = ~0;
5476
 
5477
      /* Fill in i.rm.reg or i.rm.regmem field with register operand
5478
         (if any) based on i.tm.extension_opcode.  Again, we must be
5479
         careful to make sure that segment/control/debug/test/MMX
5480
         registers are coded into the i.rm.reg field.  */
5481
      if (i.reg_operands)
5482
        {
5483
          unsigned int op;
5484
 
5485
          /* This has been precalculated for SSE5 instructions
5486
             that have a DREX field earlier in process_drex.  */
5487
          if (i.tm.opcode_modifier.drex
5488
              || i.tm.opcode_modifier.drexv
5489
              || i.tm.opcode_modifier.drexc)
5490
            {
5491
              op = i.drex.modrm_reg;
5492
              i.rm.reg = i.op[op].regs->reg_num;
5493
              if ((i.op[op].regs->reg_flags & RegRex) != 0)
5494
                i.rex |= REX_R;
5495
            }
5496
          else
5497
            {
5498
              unsigned int vex_reg = ~0;
5499
 
5500
              for (op = 0; op < i.operands; op++)
5501
                if (i.types[op].bitfield.reg8
5502
                    || i.types[op].bitfield.reg16
5503
                    || i.types[op].bitfield.reg32
5504
                    || i.types[op].bitfield.reg64
5505
                    || i.types[op].bitfield.regmmx
5506
                    || i.types[op].bitfield.regxmm
5507
                    || i.types[op].bitfield.regymm
5508
                    || i.types[op].bitfield.sreg2
5509
                    || i.types[op].bitfield.sreg3
5510
                    || i.types[op].bitfield.control
5511
                    || i.types[op].bitfield.debug
5512
                    || i.types[op].bitfield.test)
5513
                  break;
5514
 
5515
              if (vex_3_sources)
5516
                op = dest;
5517
              else if (i.tm.opcode_modifier.vexnds)
5518
                {
5519
                  /* For instructions with VexNDS, the register-only
5520
                     source operand is encoded in VEX prefix. */
5521
                  assert (mem != (unsigned int) ~0);
5522
 
5523
                  if (op > mem)
5524
                    {
5525
                      vex_reg = op++;
5526
                      assert (op < i.operands);
5527
                    }
5528
                  else
5529
                    {
5530
                      vex_reg = op + 1;
5531
                      assert (vex_reg < i.operands);
5532
                    }
5533
                }
5534
              else if (i.tm.opcode_modifier.vexndd)
5535
                {
5536
                  /* For instructions with VexNDD, there should be
5537
                     no memory operand and the register destination
5538
                     is encoded in VEX prefix.  */
5539
                  assert (i.mem_operands == 0
5540
                          && (op + 2) == i.operands);
5541
                  vex_reg = op + 1;
5542
                }
5543
              else
5544
                assert (op < i.operands);
5545
 
5546
              if (vex_reg != (unsigned int) ~0)
5547
                {
5548
                  assert (i.reg_operands == 2);
5549
 
5550
                  if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5551
                                           & regxmm)
5552
                      && !operand_type_equal (&i.tm.operand_types[vex_reg],
5553
                                              &regymm))
5554
                    abort ();
5555
                  i.vex.register_specifier = i.op[vex_reg].regs;
5556
                }
5557
 
5558
              /* If there is an extension opcode to put here, the
5559
                 register number must be put into the regmem field.  */
5560
              if (i.tm.extension_opcode != None)
5561
                {
5562
                  i.rm.regmem = i.op[op].regs->reg_num;
5563
                  if ((i.op[op].regs->reg_flags & RegRex) != 0)
5564
                    i.rex |= REX_B;
5565
                }
5566
              else
5567
                {
5568
                  i.rm.reg = i.op[op].regs->reg_num;
5569
                  if ((i.op[op].regs->reg_flags & RegRex) != 0)
5570
                    i.rex |= REX_R;
5571
                }
5572
            }
5573
 
5574
          /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5575
             must set it to 3 to indicate this is a register operand
5576
             in the regmem field.  */
5577
          if (!i.mem_operands)
5578
            i.rm.mode = 3;
5579
        }
5580
 
5581
      /* Fill in i.rm.reg field with extension opcode (if any).  */
5582
      if (i.tm.extension_opcode != None
5583
          && !(i.tm.opcode_modifier.drex
5584
              || i.tm.opcode_modifier.drexv
5585
              || i.tm.opcode_modifier.drexc))
5586
        i.rm.reg = i.tm.extension_opcode;
5587
    }
5588
  return default_seg;
5589
}
5590
 
5591
static void
5592
output_branch (void)
5593
{
5594
  char *p;
5595
  int code16;
5596
  int prefix;
5597
  relax_substateT subtype;
5598
  symbolS *sym;
5599
  offsetT off;
5600
 
5601
  code16 = 0;
5602
  if (flag_code == CODE_16BIT)
5603
    code16 = CODE16;
5604
 
5605
  prefix = 0;
5606
  if (i.prefix[DATA_PREFIX] != 0)
5607
    {
5608
      prefix = 1;
5609
      i.prefixes -= 1;
5610
      code16 ^= CODE16;
5611
    }
5612
  /* Pentium4 branch hints.  */
5613
  if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5614
      || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5615
    {
5616
      prefix++;
5617
      i.prefixes--;
5618
    }
5619
  if (i.prefix[REX_PREFIX] != 0)
5620
    {
5621
      prefix++;
5622
      i.prefixes--;
5623
    }
5624
 
5625
  if (i.prefixes != 0 && !intel_syntax)
5626
    as_warn (_("skipping prefixes on this instruction"));
5627
 
5628
  /* It's always a symbol;  End frag & setup for relax.
5629
     Make sure there is enough room in this frag for the largest
5630
     instruction we may generate in md_convert_frag.  This is 2
5631
     bytes for the opcode and room for the prefix and largest
5632
     displacement.  */
5633
  frag_grow (prefix + 2 + 4);
5634
  /* Prefix and 1 opcode byte go in fr_fix.  */
5635
  p = frag_more (prefix + 1);
5636
  if (i.prefix[DATA_PREFIX] != 0)
5637
    *p++ = DATA_PREFIX_OPCODE;
5638
  if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5639
      || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5640
    *p++ = i.prefix[SEG_PREFIX];
5641
  if (i.prefix[REX_PREFIX] != 0)
5642
    *p++ = i.prefix[REX_PREFIX];
5643
  *p = i.tm.base_opcode;
5644
 
5645
  if ((unsigned char) *p == JUMP_PC_RELATIVE)
5646
    subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
5647
  else if (cpu_arch_flags.bitfield.cpui386)
5648
    subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5649
  else
5650
    subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5651
  subtype |= code16;
5652
 
5653
  sym = i.op[0].disps->X_add_symbol;
5654
  off = i.op[0].disps->X_add_number;
5655
 
5656
  if (i.op[0].disps->X_op != O_constant
5657
      && i.op[0].disps->X_op != O_symbol)
5658
    {
5659
      /* Handle complex expressions.  */
5660
      sym = make_expr_symbol (i.op[0].disps);
5661
      off = 0;
5662
    }
5663
 
5664
  /* 1 possible extra opcode + 4 byte displacement go in var part.
5665
     Pass reloc in fr_var.  */
5666
  frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5667
}
5668
 
5669
static void
5670
output_jump (void)
5671
{
5672
  char *p;
5673
  int size;
5674
  fixS *fixP;
5675
 
5676
  if (i.tm.opcode_modifier.jumpbyte)
5677
    {
5678
      /* This is a loop or jecxz type instruction.  */
5679
      size = 1;
5680
      if (i.prefix[ADDR_PREFIX] != 0)
5681
        {
5682
          FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5683
          i.prefixes -= 1;
5684
        }
5685
      /* Pentium4 branch hints.  */
5686
      if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5687
          || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5688
        {
5689
          FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5690
          i.prefixes--;
5691
        }
5692
    }
5693
  else
5694
    {
5695
      int code16;
5696
 
5697
      code16 = 0;
5698
      if (flag_code == CODE_16BIT)
5699
        code16 = CODE16;
5700
 
5701
      if (i.prefix[DATA_PREFIX] != 0)
5702
        {
5703
          FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5704
          i.prefixes -= 1;
5705
          code16 ^= CODE16;
5706
        }
5707
 
5708
      size = 4;
5709
      if (code16)
5710
        size = 2;
5711
    }
5712
 
5713
  if (i.prefix[REX_PREFIX] != 0)
5714
    {
5715
      FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5716
      i.prefixes -= 1;
5717
    }
5718
 
5719
  if (i.prefixes != 0 && !intel_syntax)
5720
    as_warn (_("skipping prefixes on this instruction"));
5721
 
5722
  p = frag_more (1 + size);
5723
  *p++ = i.tm.base_opcode;
5724
 
5725
  fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5726
                      i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5727
 
5728
  /* All jumps handled here are signed, but don't use a signed limit
5729
     check for 32 and 16 bit jumps as we want to allow wrap around at
5730
     4G and 64k respectively.  */
5731
  if (size == 1)
5732
    fixP->fx_signed = 1;
5733
}
5734
 
5735
static void
5736
output_interseg_jump (void)
5737
{
5738
  char *p;
5739
  int size;
5740
  int prefix;
5741
  int code16;
5742
 
5743
  code16 = 0;
5744
  if (flag_code == CODE_16BIT)
5745
    code16 = CODE16;
5746
 
5747
  prefix = 0;
5748
  if (i.prefix[DATA_PREFIX] != 0)
5749
    {
5750
      prefix = 1;
5751
      i.prefixes -= 1;
5752
      code16 ^= CODE16;
5753
    }
5754
  if (i.prefix[REX_PREFIX] != 0)
5755
    {
5756
      prefix++;
5757
      i.prefixes -= 1;
5758
    }
5759
 
5760
  size = 4;
5761
  if (code16)
5762
    size = 2;
5763
 
5764
  if (i.prefixes != 0 && !intel_syntax)
5765
    as_warn (_("skipping prefixes on this instruction"));
5766
 
5767
  /* 1 opcode; 2 segment; offset  */
5768
  p = frag_more (prefix + 1 + 2 + size);
5769
 
5770
  if (i.prefix[DATA_PREFIX] != 0)
5771
    *p++ = DATA_PREFIX_OPCODE;
5772
 
5773
  if (i.prefix[REX_PREFIX] != 0)
5774
    *p++ = i.prefix[REX_PREFIX];
5775
 
5776
  *p++ = i.tm.base_opcode;
5777
  if (i.op[1].imms->X_op == O_constant)
5778
    {
5779
      offsetT n = i.op[1].imms->X_add_number;
5780
 
5781
      if (size == 2
5782
          && !fits_in_unsigned_word (n)
5783
          && !fits_in_signed_word (n))
5784
        {
5785
          as_bad (_("16-bit jump out of range"));
5786
          return;
5787
        }
5788
      md_number_to_chars (p, n, size);
5789
    }
5790
  else
5791
    fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5792
                 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5793
  if (i.op[0].imms->X_op != O_constant)
5794
    as_bad (_("can't handle non absolute segment in `%s'"),
5795
            i.tm.name);
5796
  md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5797
}
5798
 
5799
static void
5800
output_insn (void)
5801
{
5802
  fragS *insn_start_frag;
5803
  offsetT insn_start_off;
5804
 
5805
  /* Tie dwarf2 debug info to the address at the start of the insn.
5806
     We can't do this after the insn has been output as the current
5807
     frag may have been closed off.  eg. by frag_var.  */
5808
  dwarf2_emit_insn (0);
5809
 
5810
  insn_start_frag = frag_now;
5811
  insn_start_off = frag_now_fix ();
5812
 
5813
  /* Output jumps.  */
5814
  if (i.tm.opcode_modifier.jump)
5815
    output_branch ();
5816
  else if (i.tm.opcode_modifier.jumpbyte
5817
           || i.tm.opcode_modifier.jumpdword)
5818
    output_jump ();
5819
  else if (i.tm.opcode_modifier.jumpintersegment)
5820
    output_interseg_jump ();
5821
  else
5822
    {
5823
      /* Output normal instructions here.  */
5824
      char *p;
5825
      unsigned char *q;
5826
      unsigned int j;
5827
      unsigned int prefix;
5828
 
5829
      /* Since the VEX prefix contains the implicit prefix, we don't
5830
          need the explicit prefix.  */
5831
      if (!i.tm.opcode_modifier.vex)
5832
        {
5833
          switch (i.tm.opcode_length)
5834
            {
5835
            case 3:
5836
              if (i.tm.base_opcode & 0xff000000)
5837
                {
5838
                  prefix = (i.tm.base_opcode >> 24) & 0xff;
5839
                  goto check_prefix;
5840
                }
5841
              break;
5842
            case 2:
5843
              if ((i.tm.base_opcode & 0xff0000) != 0)
5844
                {
5845
                  prefix = (i.tm.base_opcode >> 16) & 0xff;
5846
                  if (i.tm.cpu_flags.bitfield.cpupadlock)
5847
                    {
5848
check_prefix:
5849
                      if (prefix != REPE_PREFIX_OPCODE
5850
                          || (i.prefix[LOCKREP_PREFIX]
5851
                              != REPE_PREFIX_OPCODE))
5852
                        add_prefix (prefix);
5853
                    }
5854
                  else
5855
                    add_prefix (prefix);
5856
                }
5857
              break;
5858
            case 1:
5859
              break;
5860
            default:
5861
              abort ();
5862
            }
5863
 
5864
          /* The prefix bytes.  */
5865
          for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5866
            if (*q)
5867
              FRAG_APPEND_1_CHAR (*q);
5868
        }
5869
 
5870
      if (i.tm.opcode_modifier.vex)
5871
        {
5872
          for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5873
            if (*q)
5874
              switch (j)
5875
                {
5876
                case REX_PREFIX:
5877
                  /* REX byte is encoded in VEX prefix.  */
5878
                  break;
5879
                case SEG_PREFIX:
5880
                case ADDR_PREFIX:
5881
                  FRAG_APPEND_1_CHAR (*q);
5882
                  break;
5883
                default:
5884
                  /* There should be no other prefixes for instructions
5885
                     with VEX prefix.  */
5886
                  abort ();
5887
                }
5888
 
5889
          /* Now the VEX prefix.  */
5890
          p = frag_more (i.vex.length);
5891
          for (j = 0; j < i.vex.length; j++)
5892
            p[j] = i.vex.bytes[j];
5893
        }
5894
 
5895
      /* Now the opcode; be careful about word order here!  */
5896
      if (i.tm.opcode_length == 1)
5897
        {
5898
          FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5899
        }
5900
      else
5901
        {
5902
          switch (i.tm.opcode_length)
5903
            {
5904
            case 3:
5905
              p = frag_more (3);
5906
              *p++ = (i.tm.base_opcode >> 16) & 0xff;
5907
              break;
5908
            case 2:
5909
              p = frag_more (2);
5910
              break;
5911
            default:
5912
              abort ();
5913
              break;
5914
            }
5915
 
5916
          /* Put out high byte first: can't use md_number_to_chars!  */
5917
          *p++ = (i.tm.base_opcode >> 8) & 0xff;
5918
          *p = i.tm.base_opcode & 0xff;
5919
 
5920
          /* On SSE5, encode the OC1 bit in the DREX field if this
5921
             encoding has multiple formats.  */
5922
          if (i.tm.opcode_modifier.drex
5923
              && i.tm.opcode_modifier.drexv
5924
              && DREX_OC1 (i.tm.extension_opcode))
5925
            *p |= DREX_OC1_MASK;
5926
        }
5927
 
5928
      /* Now the modrm byte and sib byte (if present).  */
5929
      if (i.tm.opcode_modifier.modrm)
5930
        {
5931
          FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5932
                               | i.rm.reg << 3
5933
                               | i.rm.mode << 6));
5934
          /* If i.rm.regmem == ESP (4)
5935
             && i.rm.mode != (Register mode)
5936
             && not 16 bit
5937
             ==> need second modrm byte.  */
5938
          if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5939
              && i.rm.mode != 3
5940
              && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5941
            FRAG_APPEND_1_CHAR ((i.sib.base << 0
5942
                                 | i.sib.index << 3
5943
                                 | i.sib.scale << 6));
5944
        }
5945
 
5946
      /* Write the DREX byte if needed.  */
5947
      if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5948
        {
5949
          p = frag_more (1);
5950
          *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5951
 
5952
          /* Encode the OC0 bit if this encoding has multiple
5953
             formats.  */
5954
          if ((i.tm.opcode_modifier.drex
5955
               || i.tm.opcode_modifier.drexv)
5956
              && DREX_OC0 (i.tm.extension_opcode))
5957
            *p |= DREX_OC0_MASK;
5958
        }
5959
 
5960
      if (i.disp_operands)
5961
        output_disp (insn_start_frag, insn_start_off);
5962
 
5963
      if (i.imm_operands)
5964
        output_imm (insn_start_frag, insn_start_off);
5965
    }
5966
 
5967
#ifdef DEBUG386
5968
  if (flag_debug)
5969
    {
5970
      pi ("" /*line*/, &i);
5971
    }
5972
#endif /* DEBUG386  */
5973
}
5974
 
5975
/* Return the size of the displacement operand N.  */
5976
 
5977
static int
5978
disp_size (unsigned int n)
5979
{
5980
  int size = 4;
5981
  if (i.types[n].bitfield.disp64)
5982
    size = 8;
5983
  else if (i.types[n].bitfield.disp8)
5984
    size = 1;
5985
  else if (i.types[n].bitfield.disp16)
5986
    size = 2;
5987
  return size;
5988
}
5989
 
5990
/* Return the size of the immediate operand N.  */
5991
 
5992
static int
5993
imm_size (unsigned int n)
5994
{
5995
  int size = 4;
5996
  if (i.types[n].bitfield.imm64)
5997
    size = 8;
5998
  else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5999
    size = 1;
6000
  else if (i.types[n].bitfield.imm16)
6001
    size = 2;
6002
  return size;
6003
}
6004
 
6005
static void
6006
output_disp (fragS *insn_start_frag, offsetT insn_start_off)
6007
{
6008
  char *p;
6009
  unsigned int n;
6010
 
6011
  for (n = 0; n < i.operands; n++)
6012
    {
6013
      if (operand_type_check (i.types[n], disp))
6014
        {
6015
          if (i.op[n].disps->X_op == O_constant)
6016
            {
6017
              int size = disp_size (n);
6018
              offsetT val;
6019
 
6020
              val = offset_in_range (i.op[n].disps->X_add_number,
6021
                                     size);
6022
              p = frag_more (size);
6023
              md_number_to_chars (p, val, size);
6024
            }
6025
          else
6026
            {
6027
              enum bfd_reloc_code_real reloc_type;
6028
              int size = disp_size (n);
6029
              int sign = i.types[n].bitfield.disp32s;
6030
              int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6031
 
6032
              /* We can't have 8 bit displacement here.  */
6033
              assert (!i.types[n].bitfield.disp8);
6034
 
6035
              /* The PC relative address is computed relative
6036
                 to the instruction boundary, so in case immediate
6037
                 fields follows, we need to adjust the value.  */
6038
              if (pcrel && i.imm_operands)
6039
                {
6040
                  unsigned int n1;
6041
                  int sz = 0;
6042
 
6043
                  for (n1 = 0; n1 < i.operands; n1++)
6044
                    if (operand_type_check (i.types[n1], imm))
6045
                      {
6046
                        /* Only one immediate is allowed for PC
6047
                           relative address.  */
6048
                        assert (sz == 0);
6049
                        sz = imm_size (n1);
6050
                        i.op[n].disps->X_add_number -= sz;
6051
                      }
6052
                  /* We should find the immediate.  */
6053
                  assert (sz != 0);
6054
                }
6055
 
6056
              p = frag_more (size);
6057
              reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
6058
              if (GOT_symbol
6059
                  && GOT_symbol == i.op[n].disps->X_add_symbol
6060
                  && (((reloc_type == BFD_RELOC_32
6061
                        || reloc_type == BFD_RELOC_X86_64_32S
6062
                        || (reloc_type == BFD_RELOC_64
6063
                            && object_64bit))
6064
                       && (i.op[n].disps->X_op == O_symbol
6065
                           || (i.op[n].disps->X_op == O_add
6066
                               && ((symbol_get_value_expression
6067
                                    (i.op[n].disps->X_op_symbol)->X_op)
6068
                                   == O_subtract))))
6069
                      || reloc_type == BFD_RELOC_32_PCREL))
6070
                {
6071
                  offsetT add;
6072
 
6073
                  if (insn_start_frag == frag_now)
6074
                    add = (p - frag_now->fr_literal) - insn_start_off;
6075
                  else
6076
                    {
6077
                      fragS *fr;
6078
 
6079
                      add = insn_start_frag->fr_fix - insn_start_off;
6080
                      for (fr = insn_start_frag->fr_next;
6081
                           fr && fr != frag_now; fr = fr->fr_next)
6082
                        add += fr->fr_fix;
6083
                      add += p - frag_now->fr_literal;
6084
                    }
6085
 
6086
                  if (!object_64bit)
6087
                    {
6088
                      reloc_type = BFD_RELOC_386_GOTPC;
6089
                      i.op[n].imms->X_add_number += add;
6090
                    }
6091
                  else if (reloc_type == BFD_RELOC_64)
6092
                    reloc_type = BFD_RELOC_X86_64_GOTPC64;
6093
                  else
6094
                    /* Don't do the adjustment for x86-64, as there
6095
                       the pcrel addressing is relative to the _next_
6096
                       insn, and that is taken care of in other code.  */
6097
                    reloc_type = BFD_RELOC_X86_64_GOTPC32;
6098
                }
6099
              fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6100
                           i.op[n].disps, pcrel, reloc_type);
6101
            }
6102
        }
6103
    }
6104
}
6105
 
6106
static void
6107
output_imm (fragS *insn_start_frag, offsetT insn_start_off)
6108
{
6109
  char *p;
6110
  unsigned int n;
6111
 
6112
  for (n = 0; n < i.operands; n++)
6113
    {
6114
      if (operand_type_check (i.types[n], imm))
6115
        {
6116
          if (i.op[n].imms->X_op == O_constant)
6117
            {
6118
              int size = imm_size (n);
6119
              offsetT val;
6120
 
6121
              val = offset_in_range (i.op[n].imms->X_add_number,
6122
                                     size);
6123
              p = frag_more (size);
6124
              md_number_to_chars (p, val, size);
6125
            }
6126
          else
6127
            {
6128
              /* Not absolute_section.
6129
                 Need a 32-bit fixup (don't support 8bit
6130
                 non-absolute imms).  Try to support other
6131
                 sizes ...  */
6132
              enum bfd_reloc_code_real reloc_type;
6133
              int size = imm_size (n);
6134
              int sign;
6135
 
6136
              if (i.types[n].bitfield.imm32s
6137
                  && (i.suffix == QWORD_MNEM_SUFFIX
6138
                      || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
6139
                sign = 1;
6140
              else
6141
                sign = 0;
6142
 
6143
              p = frag_more (size);
6144
              reloc_type = reloc (size, 0, sign, i.reloc[n]);
6145
 
6146
              /*   This is tough to explain.  We end up with this one if we
6147
               * have operands that look like
6148
               * "_GLOBAL_OFFSET_TABLE_+[.-.L284]".  The goal here is to
6149
               * obtain the absolute address of the GOT, and it is strongly
6150
               * preferable from a performance point of view to avoid using
6151
               * a runtime relocation for this.  The actual sequence of
6152
               * instructions often look something like:
6153
               *
6154
               *        call    .L66
6155
               * .L66:
6156
               *        popl    %ebx
6157
               *        addl    $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6158
               *
6159
               *   The call and pop essentially return the absolute address
6160
               * of the label .L66 and store it in %ebx.  The linker itself
6161
               * will ultimately change the first operand of the addl so
6162
               * that %ebx points to the GOT, but to keep things simple, the
6163
               * .o file must have this operand set so that it generates not
6164
               * the absolute address of .L66, but the absolute address of
6165
               * itself.  This allows the linker itself simply treat a GOTPC
6166
               * relocation as asking for a pcrel offset to the GOT to be
6167
               * added in, and the addend of the relocation is stored in the
6168
               * operand field for the instruction itself.
6169
               *
6170
               *   Our job here is to fix the operand so that it would add
6171
               * the correct offset so that %ebx would point to itself.  The
6172
               * thing that is tricky is that .-.L66 will point to the
6173
               * beginning of the instruction, so we need to further modify
6174
               * the operand so that it will point to itself.  There are
6175
               * other cases where you have something like:
6176
               *
6177
               *        .long   $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6178
               *
6179
               * and here no correction would be required.  Internally in
6180
               * the assembler we treat operands of this form as not being
6181
               * pcrel since the '.' is explicitly mentioned, and I wonder
6182
               * whether it would simplify matters to do it this way.  Who
6183
               * knows.  In earlier versions of the PIC patches, the
6184
               * pcrel_adjust field was used to store the correction, but
6185
               * since the expression is not pcrel, I felt it would be
6186
               * confusing to do it this way.  */
6187
 
6188
              if ((reloc_type == BFD_RELOC_32
6189
                   || reloc_type == BFD_RELOC_X86_64_32S
6190
                   || reloc_type == BFD_RELOC_64)
6191
                  && GOT_symbol
6192
                  && GOT_symbol == i.op[n].imms->X_add_symbol
6193
                  && (i.op[n].imms->X_op == O_symbol
6194
                      || (i.op[n].imms->X_op == O_add
6195
                          && ((symbol_get_value_expression
6196
                               (i.op[n].imms->X_op_symbol)->X_op)
6197
                              == O_subtract))))
6198
                {
6199
                  offsetT add;
6200
 
6201
                  if (insn_start_frag == frag_now)
6202
                    add = (p - frag_now->fr_literal) - insn_start_off;
6203
                  else
6204
                    {
6205
                      fragS *fr;
6206
 
6207
                      add = insn_start_frag->fr_fix - insn_start_off;
6208
                      for (fr = insn_start_frag->fr_next;
6209
                           fr && fr != frag_now; fr = fr->fr_next)
6210
                        add += fr->fr_fix;
6211
                      add += p - frag_now->fr_literal;
6212
                    }
6213
 
6214
                  if (!object_64bit)
6215
                    reloc_type = BFD_RELOC_386_GOTPC;
6216
                  else if (size == 4)
6217
                    reloc_type = BFD_RELOC_X86_64_GOTPC32;
6218
                  else if (size == 8)
6219
                    reloc_type = BFD_RELOC_X86_64_GOTPC64;
6220
                  i.op[n].imms->X_add_number += add;
6221
                }
6222
              fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6223
                           i.op[n].imms, 0, reloc_type);
6224
            }
6225
        }
6226
    }
6227
}
6228
 
6229
/* x86_cons_fix_new is called via the expression parsing code when a
6230
   reloc is needed.  We use this hook to get the correct .got reloc.  */
6231
static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6232
static int cons_sign = -1;
6233
 
6234
void
6235
x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
6236
                  expressionS *exp)
6237
{
6238
  enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6239
 
6240
  got_reloc = NO_RELOC;
6241
 
6242
#ifdef TE_PE
6243
  if (exp->X_op == O_secrel)
6244
    {
6245
      exp->X_op = O_symbol;
6246
      r = BFD_RELOC_32_SECREL;
6247
    }
6248
#endif
6249
 
6250
  fix_new_exp (frag, off, len, exp, 0, r);
6251
}
6252
 
6253
#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6254
# define lex_got(reloc, adjust, types) NULL
6255
#else
6256
/* Parse operands of the form
6257
   <symbol>@GOTOFF+<nnn>
6258
   and similar .plt or .got references.
6259
 
6260
   If we find one, set up the correct relocation in RELOC and copy the
6261
   input string, minus the `@GOTOFF' into a malloc'd buffer for
6262
   parsing by the calling routine.  Return this buffer, and if ADJUST
6263
   is non-null set it to the length of the string we removed from the
6264
   input line.  Otherwise return NULL.  */
6265
static char *
6266
lex_got (enum bfd_reloc_code_real *reloc,
6267
         int *adjust,
6268
         i386_operand_type *types)
6269
{
6270
  /* Some of the relocations depend on the size of what field is to
6271
     be relocated.  But in our callers i386_immediate and i386_displacement
6272
     we don't yet know the operand size (this will be set by insn
6273
     matching).  Hence we record the word32 relocation here,
6274
     and adjust the reloc according to the real size in reloc().  */
6275
  static const struct {
6276
    const char *str;
6277
    const enum bfd_reloc_code_real rel[2];
6278
    const i386_operand_type types64;
6279
  } gotrel[] = {
6280
    { "PLTOFF",   { 0,
6281
                    BFD_RELOC_X86_64_PLTOFF64 },
6282
      OPERAND_TYPE_IMM64 },
6283
    { "PLT",      { BFD_RELOC_386_PLT32,
6284
                    BFD_RELOC_X86_64_PLT32    },
6285
      OPERAND_TYPE_IMM32_32S_DISP32 },
6286
    { "GOTPLT",   { 0,
6287
                    BFD_RELOC_X86_64_GOTPLT64 },
6288
      OPERAND_TYPE_IMM64_DISP64 },
6289
    { "GOTOFF",   { BFD_RELOC_386_GOTOFF,
6290
                    BFD_RELOC_X86_64_GOTOFF64 },
6291
      OPERAND_TYPE_IMM64_DISP64 },
6292
    { "GOTPCREL", { 0,
6293
                    BFD_RELOC_X86_64_GOTPCREL },
6294
      OPERAND_TYPE_IMM32_32S_DISP32 },
6295
    { "TLSGD",    { BFD_RELOC_386_TLS_GD,
6296
                    BFD_RELOC_X86_64_TLSGD    },
6297
      OPERAND_TYPE_IMM32_32S_DISP32 },
6298
    { "TLSLDM",   { BFD_RELOC_386_TLS_LDM,
6299
 
6300
      OPERAND_TYPE_NONE },
6301
    { "TLSLD",    { 0,
6302
                    BFD_RELOC_X86_64_TLSLD    },
6303
      OPERAND_TYPE_IMM32_32S_DISP32 },
6304
    { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6305
                    BFD_RELOC_X86_64_GOTTPOFF },
6306
      OPERAND_TYPE_IMM32_32S_DISP32 },
6307
    { "TPOFF",    { BFD_RELOC_386_TLS_LE_32,
6308
                    BFD_RELOC_X86_64_TPOFF32  },
6309
      OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6310
    { "NTPOFF",   { BFD_RELOC_386_TLS_LE,
6311
 
6312
      OPERAND_TYPE_NONE },
6313
    { "DTPOFF",   { BFD_RELOC_386_TLS_LDO_32,
6314
                    BFD_RELOC_X86_64_DTPOFF32 },
6315
 
6316
      OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6317
    { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6318
 
6319
      OPERAND_TYPE_NONE },
6320
    { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6321
 
6322
      OPERAND_TYPE_NONE },
6323
    { "GOT",      { BFD_RELOC_386_GOT32,
6324
                    BFD_RELOC_X86_64_GOT32    },
6325
      OPERAND_TYPE_IMM32_32S_64_DISP32 },
6326
    { "TLSDESC",  { BFD_RELOC_386_TLS_GOTDESC,
6327
                    BFD_RELOC_X86_64_GOTPC32_TLSDESC },
6328
      OPERAND_TYPE_IMM32_32S_DISP32 },
6329
    { "TLSCALL",  { BFD_RELOC_386_TLS_DESC_CALL,
6330
                    BFD_RELOC_X86_64_TLSDESC_CALL },
6331
      OPERAND_TYPE_IMM32_32S_DISP32 },
6332
  };
6333
  char *cp;
6334
  unsigned int j;
6335
 
6336
  if (!IS_ELF)
6337
    return NULL;
6338
 
6339
  for (cp = input_line_pointer; *cp != '@'; cp++)
6340
    if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
6341
      return NULL;
6342
 
6343
  for (j = 0; j < ARRAY_SIZE (gotrel); j++)
6344
    {
6345
      int len;
6346
 
6347
      len = strlen (gotrel[j].str);
6348
      if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
6349
        {
6350
          if (gotrel[j].rel[object_64bit] != 0)
6351
            {
6352
              int first, second;
6353
              char *tmpbuf, *past_reloc;
6354
 
6355
              *reloc = gotrel[j].rel[object_64bit];
6356
              if (adjust)
6357
                *adjust = len;
6358
 
6359
              if (types)
6360
                {
6361
                  if (flag_code != CODE_64BIT)
6362
                    {
6363
                      types->bitfield.imm32 = 1;
6364
                      types->bitfield.disp32 = 1;
6365
                    }
6366
                  else
6367
                    *types = gotrel[j].types64;
6368
                }
6369
 
6370
              if (GOT_symbol == NULL)
6371
                GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6372
 
6373
              /* The length of the first part of our input line.  */
6374
              first = cp - input_line_pointer;
6375
 
6376
              /* The second part goes from after the reloc token until
6377
                 (and including) an end_of_line char or comma.  */
6378
              past_reloc = cp + 1 + len;
6379
              cp = past_reloc;
6380
              while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6381
                ++cp;
6382
              second = cp + 1 - past_reloc;
6383
 
6384
              /* Allocate and copy string.  The trailing NUL shouldn't
6385
                 be necessary, but be safe.  */
6386
              tmpbuf = xmalloc (first + second + 2);
6387
              memcpy (tmpbuf, input_line_pointer, first);
6388
              if (second != 0 && *past_reloc != ' ')
6389
                /* Replace the relocation token with ' ', so that
6390
                   errors like foo@GOTOFF1 will be detected.  */
6391
                tmpbuf[first++] = ' ';
6392
              memcpy (tmpbuf + first, past_reloc, second);
6393
              tmpbuf[first + second] = '\0';
6394
              return tmpbuf;
6395
            }
6396
 
6397
          as_bad (_("@%s reloc is not supported with %d-bit output format"),
6398
                  gotrel[j].str, 1 << (5 + object_64bit));
6399
          return NULL;
6400
        }
6401
    }
6402
 
6403
  /* Might be a symbol version string.  Don't as_bad here.  */
6404
  return NULL;
6405
}
6406
 
6407
void
6408
x86_cons (expressionS *exp, int size)
6409
{
6410
  if (size == 4 || (object_64bit && size == 8))
6411
    {
6412
      /* Handle @GOTOFF and the like in an expression.  */
6413
      char *save;
6414
      char *gotfree_input_line;
6415
      int adjust;
6416
 
6417
      save = input_line_pointer;
6418
      gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
6419
      if (gotfree_input_line)
6420
        input_line_pointer = gotfree_input_line;
6421
 
6422
      expression (exp);
6423
 
6424
      if (gotfree_input_line)
6425
        {
6426
          /* expression () has merrily parsed up to the end of line,
6427
             or a comma - in the wrong buffer.  Transfer how far
6428
             input_line_pointer has moved to the right buffer.  */
6429
          input_line_pointer = (save
6430
                                + (input_line_pointer - gotfree_input_line)
6431
                                + adjust);
6432
          free (gotfree_input_line);
6433
          if (exp->X_op == O_constant
6434
              || exp->X_op == O_absent
6435
              || exp->X_op == O_illegal
6436
              || exp->X_op == O_register
6437
              || exp->X_op == O_big)
6438
            {
6439
              char c = *input_line_pointer;
6440
              *input_line_pointer = 0;
6441
              as_bad (_("missing or invalid expression `%s'"), save);
6442
              *input_line_pointer = c;
6443
            }
6444
        }
6445
    }
6446
  else
6447
    expression (exp);
6448
}
6449
#endif
6450
 
6451
static void signed_cons (int size)
6452
{
6453
  if (flag_code == CODE_64BIT)
6454
    cons_sign = 1;
6455
  cons (size);
6456
  cons_sign = -1;
6457
}
6458
 
6459
#ifdef TE_PE
6460
static void
6461
pe_directive_secrel (dummy)
6462
     int dummy ATTRIBUTE_UNUSED;
6463
{
6464
  expressionS exp;
6465
 
6466
  do
6467
    {
6468
      expression (&exp);
6469
      if (exp.X_op == O_symbol)
6470
        exp.X_op = O_secrel;
6471
 
6472
      emit_expr (&exp, 4);
6473
    }
6474
  while (*input_line_pointer++ == ',');
6475
 
6476
  input_line_pointer--;
6477
  demand_empty_rest_of_line ();
6478
}
6479
#endif
6480
 
6481
static int
6482
i386_immediate (char *imm_start)
6483
{
6484
  char *save_input_line_pointer;
6485
  char *gotfree_input_line;
6486
  segT exp_seg = 0;
6487
  expressionS *exp;
6488
  i386_operand_type types;
6489
 
6490
  operand_type_set (&types, ~0);
6491
 
6492
  if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6493
    {
6494
      as_bad (_("at most %d immediate operands are allowed"),
6495
              MAX_IMMEDIATE_OPERANDS);
6496
      return 0;
6497
    }
6498
 
6499
  exp = &im_expressions[i.imm_operands++];
6500
  i.op[this_operand].imms = exp;
6501
 
6502
  if (is_space_char (*imm_start))
6503
    ++imm_start;
6504
 
6505
  save_input_line_pointer = input_line_pointer;
6506
  input_line_pointer = imm_start;
6507
 
6508
  gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6509
  if (gotfree_input_line)
6510
    input_line_pointer = gotfree_input_line;
6511
 
6512
  exp_seg = expression (exp);
6513
 
6514
  SKIP_WHITESPACE ();
6515
  if (*input_line_pointer)
6516
    as_bad (_("junk `%s' after expression"), input_line_pointer);
6517
 
6518
  input_line_pointer = save_input_line_pointer;
6519
  if (gotfree_input_line)
6520
    free (gotfree_input_line);
6521
 
6522
  if (exp->X_op == O_absent
6523
      || exp->X_op == O_illegal
6524
      || exp->X_op == O_big
6525
      || (gotfree_input_line
6526
          && (exp->X_op == O_constant
6527
              || exp->X_op == O_register)))
6528
    {
6529
      as_bad (_("missing or invalid immediate expression `%s'"),
6530
              imm_start);
6531
      return 0;
6532
    }
6533
  else if (exp->X_op == O_constant)
6534
    {
6535
      /* Size it properly later.  */
6536
      i.types[this_operand].bitfield.imm64 = 1;
6537
      /* If BFD64, sign extend val.  */
6538
      if (!use_rela_relocations
6539
          && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6540
        exp->X_add_number
6541
          = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
6542
    }
6543
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6544
  else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
6545
           && exp_seg != absolute_section
6546
           && exp_seg != text_section
6547
           && exp_seg != data_section
6548
           && exp_seg != bss_section
6549
           && exp_seg != undefined_section
6550
           && !bfd_is_com_section (exp_seg))
6551
    {
6552
      as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6553
      return 0;
6554
    }
6555
#endif
6556
  else if (!intel_syntax && exp->X_op == O_register)
6557
    {
6558
      as_bad (_("illegal immediate register operand %s"), imm_start);
6559
      return 0;
6560
    }
6561
  else
6562
    {
6563
      /* This is an address.  The size of the address will be
6564
         determined later, depending on destination register,
6565
         suffix, or the default for the section.  */
6566
      i.types[this_operand].bitfield.imm8 = 1;
6567
      i.types[this_operand].bitfield.imm16 = 1;
6568
      i.types[this_operand].bitfield.imm32 = 1;
6569
      i.types[this_operand].bitfield.imm32s = 1;
6570
      i.types[this_operand].bitfield.imm64 = 1;
6571
      i.types[this_operand] = operand_type_and (i.types[this_operand],
6572
                                                types);
6573
    }
6574
 
6575
  return 1;
6576
}
6577
 
6578
static char *
6579
i386_scale (char *scale)
6580
{
6581
  offsetT val;
6582
  char *save = input_line_pointer;
6583
 
6584
  input_line_pointer = scale;
6585
  val = get_absolute_expression ();
6586
 
6587
  switch (val)
6588
    {
6589
    case 1:
6590
      i.log2_scale_factor = 0;
6591
      break;
6592
    case 2:
6593
      i.log2_scale_factor = 1;
6594
      break;
6595
    case 4:
6596
      i.log2_scale_factor = 2;
6597
      break;
6598
    case 8:
6599
      i.log2_scale_factor = 3;
6600
      break;
6601
    default:
6602
      {
6603
        char sep = *input_line_pointer;
6604
 
6605
        *input_line_pointer = '\0';
6606
        as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6607
                scale);
6608
        *input_line_pointer = sep;
6609
        input_line_pointer = save;
6610
        return NULL;
6611
      }
6612
    }
6613
  if (i.log2_scale_factor != 0 && i.index_reg == 0)
6614
    {
6615
      as_warn (_("scale factor of %d without an index register"),
6616
               1 << i.log2_scale_factor);
6617
      i.log2_scale_factor = 0;
6618
    }
6619
  scale = input_line_pointer;
6620
  input_line_pointer = save;
6621
  return scale;
6622
}
6623
 
6624
static int
6625
i386_displacement (char *disp_start, char *disp_end)
6626
{
6627
  expressionS *exp;
6628
  segT exp_seg = 0;
6629
  char *save_input_line_pointer;
6630
  char *gotfree_input_line;
6631
  int override;
6632
  i386_operand_type bigdisp, types = anydisp;
6633
  int ret;
6634
 
6635
  if (i.disp_operands == MAX_MEMORY_OPERANDS)
6636
    {
6637
      as_bad (_("at most %d displacement operands are allowed"),
6638
              MAX_MEMORY_OPERANDS);
6639
      return 0;
6640
    }
6641
 
6642
  operand_type_set (&bigdisp, 0);
6643
  if ((i.types[this_operand].bitfield.jumpabsolute)
6644
      || (!current_templates->start->opcode_modifier.jump
6645
          && !current_templates->start->opcode_modifier.jumpdword))
6646
    {
6647
      bigdisp.bitfield.disp32 = 1;
6648
      override = (i.prefix[ADDR_PREFIX] != 0);
6649
      if (flag_code == CODE_64BIT)
6650
        {
6651
          if (!override)
6652
            {
6653
              bigdisp.bitfield.disp32s = 1;
6654
              bigdisp.bitfield.disp64 = 1;
6655
            }
6656
        }
6657
      else if ((flag_code == CODE_16BIT) ^ override)
6658
        {
6659
          bigdisp.bitfield.disp32 = 0;
6660
          bigdisp.bitfield.disp16 = 1;
6661
        }
6662
    }
6663
  else
6664
    {
6665
      /* For PC-relative branches, the width of the displacement
6666
         is dependent upon data size, not address size.  */
6667
      override = (i.prefix[DATA_PREFIX] != 0);
6668
      if (flag_code == CODE_64BIT)
6669
        {
6670
          if (override || i.suffix == WORD_MNEM_SUFFIX)
6671
            bigdisp.bitfield.disp16 = 1;
6672
          else
6673
            {
6674
              bigdisp.bitfield.disp32 = 1;
6675
              bigdisp.bitfield.disp32s = 1;
6676
            }
6677
        }
6678
      else
6679
        {
6680
          if (!override)
6681
            override = (i.suffix == (flag_code != CODE_16BIT
6682
                                     ? WORD_MNEM_SUFFIX
6683
                                     : LONG_MNEM_SUFFIX));
6684
          bigdisp.bitfield.disp32 = 1;
6685
          if ((flag_code == CODE_16BIT) ^ override)
6686
            {
6687
              bigdisp.bitfield.disp32 = 0;
6688
              bigdisp.bitfield.disp16 = 1;
6689
            }
6690
        }
6691
    }
6692
  i.types[this_operand] = operand_type_or (i.types[this_operand],
6693
                                           bigdisp);
6694
 
6695
  exp = &disp_expressions[i.disp_operands];
6696
  i.op[this_operand].disps = exp;
6697
  i.disp_operands++;
6698
  save_input_line_pointer = input_line_pointer;
6699
  input_line_pointer = disp_start;
6700
  END_STRING_AND_SAVE (disp_end);
6701
 
6702
#ifndef GCC_ASM_O_HACK
6703
#define GCC_ASM_O_HACK 0
6704
#endif
6705
#if GCC_ASM_O_HACK
6706
  END_STRING_AND_SAVE (disp_end + 1);
6707
  if (i.types[this_operand].bitfield.baseIndex
6708
      && displacement_string_end[-1] == '+')
6709
    {
6710
      /* This hack is to avoid a warning when using the "o"
6711
         constraint within gcc asm statements.
6712
         For instance:
6713
 
6714
         #define _set_tssldt_desc(n,addr,limit,type) \
6715
         __asm__ __volatile__ ( \
6716
         "movw %w2,%0\n\t" \
6717
         "movw %w1,2+%0\n\t" \
6718
         "rorl $16,%1\n\t" \
6719
         "movb %b1,4+%0\n\t" \
6720
         "movb %4,5+%0\n\t" \
6721
         "movb $0,6+%0\n\t" \
6722
         "movb %h1,7+%0\n\t" \
6723
         "rorl $16,%1" \
6724
         : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6725
 
6726
         This works great except that the output assembler ends
6727
         up looking a bit weird if it turns out that there is
6728
         no offset.  You end up producing code that looks like:
6729
 
6730
         #APP
6731
         movw $235,(%eax)
6732
         movw %dx,2+(%eax)
6733
         rorl $16,%edx
6734
         movb %dl,4+(%eax)
6735
         movb $137,5+(%eax)
6736
         movb $0,6+(%eax)
6737
         movb %dh,7+(%eax)
6738
         rorl $16,%edx
6739
         #NO_APP
6740
 
6741
         So here we provide the missing zero.  */
6742
 
6743
      *displacement_string_end = '0';
6744
    }
6745
#endif
6746
  gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6747
  if (gotfree_input_line)
6748
    input_line_pointer = gotfree_input_line;
6749
 
6750
  exp_seg = expression (exp);
6751
 
6752
  SKIP_WHITESPACE ();
6753
  if (*input_line_pointer)
6754
    as_bad (_("junk `%s' after expression"), input_line_pointer);
6755
#if GCC_ASM_O_HACK
6756
  RESTORE_END_STRING (disp_end + 1);
6757
#endif
6758
  input_line_pointer = save_input_line_pointer;
6759
  if (gotfree_input_line)
6760
    free (gotfree_input_line);
6761
  ret = 1;
6762
 
6763
  /* We do this to make sure that the section symbol is in
6764
     the symbol table.  We will ultimately change the relocation
6765
     to be relative to the beginning of the section.  */
6766
  if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
6767
      || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6768
      || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6769
    {
6770
      if (exp->X_op != O_symbol)
6771
        goto inv_disp;
6772
 
6773
      if (S_IS_LOCAL (exp->X_add_symbol)
6774
          && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6775
        section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
6776
      exp->X_op = O_subtract;
6777
      exp->X_op_symbol = GOT_symbol;
6778
      if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
6779
        i.reloc[this_operand] = BFD_RELOC_32_PCREL;
6780
      else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6781
        i.reloc[this_operand] = BFD_RELOC_64;
6782
      else
6783
        i.reloc[this_operand] = BFD_RELOC_32;
6784
    }
6785
 
6786
  else if (exp->X_op == O_absent
6787
           || exp->X_op == O_illegal
6788
           || exp->X_op == O_big
6789
           || (gotfree_input_line
6790
               && (exp->X_op == O_constant
6791
                   || exp->X_op == O_register)))
6792
    {
6793
    inv_disp:
6794
      as_bad (_("missing or invalid displacement expression `%s'"),
6795
              disp_start);
6796
      ret = 0;
6797
    }
6798
 
6799
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6800
  else if (exp->X_op != O_constant
6801
           && OUTPUT_FLAVOR == bfd_target_aout_flavour
6802
           && exp_seg != absolute_section
6803
           && exp_seg != text_section
6804
           && exp_seg != data_section
6805
           && exp_seg != bss_section
6806
           && exp_seg != undefined_section
6807
           && !bfd_is_com_section (exp_seg))
6808
    {
6809
      as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6810
      ret = 0;
6811
    }
6812
#endif
6813
 
6814
  RESTORE_END_STRING (disp_end);
6815
 
6816
  /* Check if this is a displacement only operand.  */
6817
  bigdisp = i.types[this_operand];
6818
  bigdisp.bitfield.disp8 = 0;
6819
  bigdisp.bitfield.disp16 = 0;
6820
  bigdisp.bitfield.disp32 = 0;
6821
  bigdisp.bitfield.disp32s = 0;
6822
  bigdisp.bitfield.disp64 = 0;
6823
  if (operand_type_all_zero (&bigdisp))
6824
    i.types[this_operand] = operand_type_and (i.types[this_operand],
6825
                                              types);
6826
 
6827
  return ret;
6828
}
6829
 
6830
/* Make sure the memory operand we've been dealt is valid.
6831
   Return 1 on success, 0 on a failure.  */
6832
 
6833
static int
6834
i386_index_check (const char *operand_string)
6835
{
6836
  int ok;
6837
#if INFER_ADDR_PREFIX
6838
  int fudged = 0;
6839
 
6840
 tryprefix:
6841
#endif
6842
  ok = 1;
6843
  if (flag_code == CODE_64BIT)
6844
    {
6845
      if ((i.base_reg
6846
           && ((i.prefix[ADDR_PREFIX] == 0
6847
                && !i.base_reg->reg_type.bitfield.reg64)
6848
               || (i.prefix[ADDR_PREFIX]
6849
                   && !i.base_reg->reg_type.bitfield.reg32))
6850
           && (i.index_reg
6851
               || i.base_reg->reg_num !=
6852
                  (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
6853
          || (i.index_reg
6854
              && (!i.index_reg->reg_type.bitfield.baseindex
6855
                  || (i.prefix[ADDR_PREFIX] == 0
6856
                      && i.index_reg->reg_num != RegRiz
6857
                      && !i.index_reg->reg_type.bitfield.reg64
6858
                      )
6859
                  || (i.prefix[ADDR_PREFIX]
6860
                      && i.index_reg->reg_num != RegEiz
6861
                      && !i.index_reg->reg_type.bitfield.reg32))))
6862
        ok = 0;
6863
    }
6864
  else
6865
    {
6866
      if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6867
        {
6868
          /* 16bit checks.  */
6869
          if ((i.base_reg
6870
               && (!i.base_reg->reg_type.bitfield.reg16
6871
                   || !i.base_reg->reg_type.bitfield.baseindex))
6872
              || (i.index_reg
6873
                  && (!i.index_reg->reg_type.bitfield.reg16
6874
                      || !i.index_reg->reg_type.bitfield.baseindex
6875
                      || !(i.base_reg
6876
                           && i.base_reg->reg_num < 6
6877
                           && i.index_reg->reg_num >= 6
6878
                           && i.log2_scale_factor == 0))))
6879
            ok = 0;
6880
        }
6881
      else
6882
        {
6883
          /* 32bit checks.  */
6884
          if ((i.base_reg
6885
               && !i.base_reg->reg_type.bitfield.reg32)
6886
              || (i.index_reg
6887
                  && ((!i.index_reg->reg_type.bitfield.reg32
6888
                       && i.index_reg->reg_num != RegEiz)
6889
                      || !i.index_reg->reg_type.bitfield.baseindex)))
6890
            ok = 0;
6891
        }
6892
    }
6893
  if (!ok)
6894
    {
6895
#if INFER_ADDR_PREFIX
6896
      if (i.prefix[ADDR_PREFIX] == 0)
6897
        {
6898
          i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6899
          i.prefixes += 1;
6900
          /* Change the size of any displacement too.  At most one of
6901
             Disp16 or Disp32 is set.
6902
             FIXME.  There doesn't seem to be any real need for separate
6903
             Disp16 and Disp32 flags.  The same goes for Imm16 and Imm32.
6904
             Removing them would probably clean up the code quite a lot.  */
6905
          if (flag_code != CODE_64BIT
6906
              && (i.types[this_operand].bitfield.disp16
6907
                  || i.types[this_operand].bitfield.disp32))
6908
            i.types[this_operand]
6909
              = operand_type_xor (i.types[this_operand], disp16_32);
6910
          fudged = 1;
6911
          goto tryprefix;
6912
        }
6913
      if (fudged)
6914
        as_bad (_("`%s' is not a valid base/index expression"),
6915
                operand_string);
6916
      else
6917
#endif
6918
        as_bad (_("`%s' is not a valid %s bit base/index expression"),
6919
                operand_string,
6920
                flag_code_names[flag_code]);
6921
    }
6922
  return ok;
6923
}
6924
 
6925
/* Parse OPERAND_STRING into the i386_insn structure I.  Returns non-zero
6926
   on error.  */
6927
 
6928
static int
6929
i386_att_operand (char *operand_string)
6930
{
6931
  const reg_entry *r;
6932
  char *end_op;
6933
  char *op_string = operand_string;
6934
 
6935
  if (is_space_char (*op_string))
6936
    ++op_string;
6937
 
6938
  /* We check for an absolute prefix (differentiating,
6939
     for example, 'jmp pc_relative_label' from 'jmp *absolute_label'.  */
6940
  if (*op_string == ABSOLUTE_PREFIX)
6941
    {
6942
      ++op_string;
6943
      if (is_space_char (*op_string))
6944
        ++op_string;
6945
      i.types[this_operand].bitfield.jumpabsolute = 1;
6946
    }
6947
 
6948
  /* Check if operand is a register.  */
6949
  if ((r = parse_register (op_string, &end_op)) != NULL)
6950
    {
6951
      i386_operand_type temp;
6952
 
6953
      /* Check for a segment override by searching for ':' after a
6954
         segment register.  */
6955
      op_string = end_op;
6956
      if (is_space_char (*op_string))
6957
        ++op_string;
6958
      if (*op_string == ':'
6959
          && (r->reg_type.bitfield.sreg2
6960
              || r->reg_type.bitfield.sreg3))
6961
        {
6962
          switch (r->reg_num)
6963
            {
6964
            case 0:
6965
              i.seg[i.mem_operands] = &es;
6966
              break;
6967
            case 1:
6968
              i.seg[i.mem_operands] = &cs;
6969
              break;
6970
            case 2:
6971
              i.seg[i.mem_operands] = &ss;
6972
              break;
6973
            case 3:
6974
              i.seg[i.mem_operands] = &ds;
6975
              break;
6976
            case 4:
6977
              i.seg[i.mem_operands] = &fs;
6978
              break;
6979
            case 5:
6980
              i.seg[i.mem_operands] = &gs;
6981
              break;
6982
            }
6983
 
6984
          /* Skip the ':' and whitespace.  */
6985
          ++op_string;
6986
          if (is_space_char (*op_string))
6987
            ++op_string;
6988
 
6989
          if (!is_digit_char (*op_string)
6990
              && !is_identifier_char (*op_string)
6991
              && *op_string != '('
6992
              && *op_string != ABSOLUTE_PREFIX)
6993
            {
6994
              as_bad (_("bad memory operand `%s'"), op_string);
6995
              return 0;
6996
            }
6997
          /* Handle case of %es:*foo.  */
6998
          if (*op_string == ABSOLUTE_PREFIX)
6999
            {
7000
              ++op_string;
7001
              if (is_space_char (*op_string))
7002
                ++op_string;
7003
              i.types[this_operand].bitfield.jumpabsolute = 1;
7004
            }
7005
          goto do_memory_reference;
7006
        }
7007
      if (*op_string)
7008
        {
7009
          as_bad (_("junk `%s' after register"), op_string);
7010
          return 0;
7011
        }
7012
      temp = r->reg_type;
7013
      temp.bitfield.baseindex = 0;
7014
      i.types[this_operand] = operand_type_or (i.types[this_operand],
7015
                                               temp);
7016
      i.types[this_operand].bitfield.unspecified = 0;
7017
      i.op[this_operand].regs = r;
7018
      i.reg_operands++;
7019
    }
7020
  else if (*op_string == REGISTER_PREFIX)
7021
    {
7022
      as_bad (_("bad register name `%s'"), op_string);
7023
      return 0;
7024
    }
7025
  else if (*op_string == IMMEDIATE_PREFIX)
7026
    {
7027
      ++op_string;
7028
      if (i.types[this_operand].bitfield.jumpabsolute)
7029
        {
7030
          as_bad (_("immediate operand illegal with absolute jump"));
7031
          return 0;
7032
        }
7033
      if (!i386_immediate (op_string))
7034
        return 0;
7035
    }
7036
  else if (is_digit_char (*op_string)
7037
           || is_identifier_char (*op_string)
7038
           || *op_string == '(')
7039
    {
7040
      /* This is a memory reference of some sort.  */
7041
      char *base_string;
7042
 
7043
      /* Start and end of displacement string expression (if found).  */
7044
      char *displacement_string_start;
7045
      char *displacement_string_end;
7046
 
7047
    do_memory_reference:
7048
      if ((i.mem_operands == 1
7049
           && !current_templates->start->opcode_modifier.isstring)
7050
          || i.mem_operands == 2)
7051
        {
7052
          as_bad (_("too many memory references for `%s'"),
7053
                  current_templates->start->name);
7054
          return 0;
7055
        }
7056
 
7057
      /* Check for base index form.  We detect the base index form by
7058
         looking for an ')' at the end of the operand, searching
7059
         for the '(' matching it, and finding a REGISTER_PREFIX or ','
7060
         after the '('.  */
7061
      base_string = op_string + strlen (op_string);
7062
 
7063
      --base_string;
7064
      if (is_space_char (*base_string))
7065
        --base_string;
7066
 
7067
      /* If we only have a displacement, set-up for it to be parsed later.  */
7068
      displacement_string_start = op_string;
7069
      displacement_string_end = base_string + 1;
7070
 
7071
      if (*base_string == ')')
7072
        {
7073
          char *temp_string;
7074
          unsigned int parens_balanced = 1;
7075
          /* We've already checked that the number of left & right ()'s are
7076
             equal, so this loop will not be infinite.  */
7077
          do
7078
            {
7079
              base_string--;
7080
              if (*base_string == ')')
7081
                parens_balanced++;
7082
              if (*base_string == '(')
7083
                parens_balanced--;
7084
            }
7085
          while (parens_balanced);
7086
 
7087
          temp_string = base_string;
7088
 
7089
          /* Skip past '(' and whitespace.  */
7090
          ++base_string;
7091
          if (is_space_char (*base_string))
7092
            ++base_string;
7093
 
7094
          if (*base_string == ','
7095
              || ((i.base_reg = parse_register (base_string, &end_op))
7096
                  != NULL))
7097
            {
7098
              displacement_string_end = temp_string;
7099
 
7100
              i.types[this_operand].bitfield.baseindex = 1;
7101
 
7102
              if (i.base_reg)
7103
                {
7104
                  base_string = end_op;
7105
                  if (is_space_char (*base_string))
7106
                    ++base_string;
7107
                }
7108
 
7109
              /* There may be an index reg or scale factor here.  */
7110
              if (*base_string == ',')
7111
                {
7112
                  ++base_string;
7113
                  if (is_space_char (*base_string))
7114
                    ++base_string;
7115
 
7116
                  if ((i.index_reg = parse_register (base_string, &end_op))
7117
                      != NULL)
7118
                    {
7119
                      base_string = end_op;
7120
                      if (is_space_char (*base_string))
7121
                        ++base_string;
7122
                      if (*base_string == ',')
7123
                        {
7124
                          ++base_string;
7125
                          if (is_space_char (*base_string))
7126
                            ++base_string;
7127
                        }
7128
                      else if (*base_string != ')')
7129
                        {
7130
                          as_bad (_("expecting `,' or `)' "
7131
                                    "after index register in `%s'"),
7132
                                  operand_string);
7133
                          return 0;
7134
                        }
7135
                    }
7136
                  else if (*base_string == REGISTER_PREFIX)
7137
                    {
7138
                      as_bad (_("bad register name `%s'"), base_string);
7139
                      return 0;
7140
                    }
7141
 
7142
                  /* Check for scale factor.  */
7143
                  if (*base_string != ')')
7144
                    {
7145
                      char *end_scale = i386_scale (base_string);
7146
 
7147
                      if (!end_scale)
7148
                        return 0;
7149
 
7150
                      base_string = end_scale;
7151
                      if (is_space_char (*base_string))
7152
                        ++base_string;
7153
                      if (*base_string != ')')
7154
                        {
7155
                          as_bad (_("expecting `)' "
7156
                                    "after scale factor in `%s'"),
7157
                                  operand_string);
7158
                          return 0;
7159
                        }
7160
                    }
7161
                  else if (!i.index_reg)
7162
                    {
7163
                      as_bad (_("expecting index register or scale factor "
7164
                                "after `,'; got '%c'"),
7165
                              *base_string);
7166
                      return 0;
7167
                    }
7168
                }
7169
              else if (*base_string != ')')
7170
                {
7171
                  as_bad (_("expecting `,' or `)' "
7172
                            "after base register in `%s'"),
7173
                          operand_string);
7174
                  return 0;
7175
                }
7176
            }
7177
          else if (*base_string == REGISTER_PREFIX)
7178
            {
7179
              as_bad (_("bad register name `%s'"), base_string);
7180
              return 0;
7181
            }
7182
        }
7183
 
7184
      /* If there's an expression beginning the operand, parse it,
7185
         assuming displacement_string_start and
7186
         displacement_string_end are meaningful.  */
7187
      if (displacement_string_start != displacement_string_end)
7188
        {
7189
          if (!i386_displacement (displacement_string_start,
7190
                                  displacement_string_end))
7191
            return 0;
7192
        }
7193
 
7194
      /* Special case for (%dx) while doing input/output op.  */
7195
      if (i.base_reg
7196
          && operand_type_equal (&i.base_reg->reg_type,
7197
                                 &reg16_inoutportreg)
7198
          && i.index_reg == 0
7199
          && i.log2_scale_factor == 0
7200
          && i.seg[i.mem_operands] == 0
7201
          && !operand_type_check (i.types[this_operand], disp))
7202
        {
7203
          i.types[this_operand] = inoutportreg;
7204
          return 1;
7205
        }
7206
 
7207
      if (i386_index_check (operand_string) == 0)
7208
        return 0;
7209
      i.types[this_operand].bitfield.mem = 1;
7210
      i.mem_operands++;
7211
    }
7212
  else
7213
    {
7214
      /* It's not a memory operand; argh!  */
7215
      as_bad (_("invalid char %s beginning operand %d `%s'"),
7216
              output_invalid (*op_string),
7217
              this_operand + 1,
7218
              op_string);
7219
      return 0;
7220
    }
7221
  return 1;                     /* Normal return.  */
7222
}
7223
 
7224
/* md_estimate_size_before_relax()
7225
 
7226
   Called just before relax() for rs_machine_dependent frags.  The x86
7227
   assembler uses these frags to handle variable size jump
7228
   instructions.
7229
 
7230
   Any symbol that is now undefined will not become defined.
7231
   Return the correct fr_subtype in the frag.
7232
   Return the initial "guess for variable size of frag" to caller.
7233
   The guess is actually the growth beyond the fixed part.  Whatever
7234
   we do to grow the fixed or variable part contributes to our
7235
   returned value.  */
7236
 
7237
int
7238
md_estimate_size_before_relax (fragP, segment)
7239
     fragS *fragP;
7240
     segT segment;
7241
{
7242
  /* We've already got fragP->fr_subtype right;  all we have to do is
7243
     check for un-relaxable symbols.  On an ELF system, we can't relax
7244
     an externally visible symbol, because it may be overridden by a
7245
     shared library.  */
7246
  if (S_GET_SEGMENT (fragP->fr_symbol) != segment
7247
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7248
      || (IS_ELF
7249
          && (S_IS_EXTERNAL (fragP->fr_symbol)
7250
              || S_IS_WEAK (fragP->fr_symbol)))
7251
#endif
7252
      )
7253
    {
7254
      /* Symbol is undefined in this segment, or we need to keep a
7255
         reloc so that weak symbols can be overridden.  */
7256
      int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
7257
      enum bfd_reloc_code_real reloc_type;
7258
      unsigned char *opcode;
7259
      int old_fr_fix;
7260
 
7261
      if (fragP->fr_var != NO_RELOC)
7262
        reloc_type = fragP->fr_var;
7263
      else if (size == 2)
7264
        reloc_type = BFD_RELOC_16_PCREL;
7265
      else
7266
        reloc_type = BFD_RELOC_32_PCREL;
7267
 
7268
      old_fr_fix = fragP->fr_fix;
7269
      opcode = (unsigned char *) fragP->fr_opcode;
7270
 
7271
      switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
7272
        {
7273
        case UNCOND_JUMP:
7274
          /* Make jmp (0xeb) a (d)word displacement jump.  */
7275
          opcode[0] = 0xe9;
7276
          fragP->fr_fix += size;
7277
          fix_new (fragP, old_fr_fix, size,
7278
                   fragP->fr_symbol,
7279
                   fragP->fr_offset, 1,
7280
                   reloc_type);
7281
          break;
7282
 
7283
        case COND_JUMP86:
7284
          if (size == 2
7285
              && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
7286
            {
7287
              /* Negate the condition, and branch past an
7288
                 unconditional jump.  */
7289
              opcode[0] ^= 1;
7290
              opcode[1] = 3;
7291
              /* Insert an unconditional jump.  */
7292
              opcode[2] = 0xe9;
7293
              /* We added two extra opcode bytes, and have a two byte
7294
                 offset.  */
7295
              fragP->fr_fix += 2 + 2;
7296
              fix_new (fragP, old_fr_fix + 2, 2,
7297
                       fragP->fr_symbol,
7298
                       fragP->fr_offset, 1,
7299
                       reloc_type);
7300
              break;
7301
            }
7302
          /* Fall through.  */
7303
 
7304
        case COND_JUMP:
7305
          if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7306
            {
7307
              fixS *fixP;
7308
 
7309
              fragP->fr_fix += 1;
7310
              fixP = fix_new (fragP, old_fr_fix, 1,
7311
                              fragP->fr_symbol,
7312
                              fragP->fr_offset, 1,
7313
                              BFD_RELOC_8_PCREL);
7314
              fixP->fx_signed = 1;
7315
              break;
7316
            }
7317
 
7318
          /* This changes the byte-displacement jump 0x7N
7319
             to the (d)word-displacement jump 0x0f,0x8N.  */
7320
          opcode[1] = opcode[0] + 0x10;
7321
          opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7322
          /* We've added an opcode byte.  */
7323
          fragP->fr_fix += 1 + size;
7324
          fix_new (fragP, old_fr_fix + 1, size,
7325
                   fragP->fr_symbol,
7326
                   fragP->fr_offset, 1,
7327
                   reloc_type);
7328
          break;
7329
 
7330
        default:
7331
          BAD_CASE (fragP->fr_subtype);
7332
          break;
7333
        }
7334
      frag_wane (fragP);
7335
      return fragP->fr_fix - old_fr_fix;
7336
    }
7337
 
7338
  /* Guess size depending on current relax state.  Initially the relax
7339
     state will correspond to a short jump and we return 1, because
7340
     the variable part of the frag (the branch offset) is one byte
7341
     long.  However, we can relax a section more than once and in that
7342
     case we must either set fr_subtype back to the unrelaxed state,
7343
     or return the value for the appropriate branch.  */
7344
  return md_relax_table[fragP->fr_subtype].rlx_length;
7345
}
7346
 
7347
/* Called after relax() is finished.
7348
 
7349
   In:  Address of frag.
7350
        fr_type == rs_machine_dependent.
7351
        fr_subtype is what the address relaxed to.
7352
 
7353
   Out: Any fixSs and constants are set up.
7354
        Caller will turn frag into a ".space 0".  */
7355
 
7356
void
7357
md_convert_frag (abfd, sec, fragP)
7358
     bfd *abfd ATTRIBUTE_UNUSED;
7359
     segT sec ATTRIBUTE_UNUSED;
7360
     fragS *fragP;
7361
{
7362
  unsigned char *opcode;
7363
  unsigned char *where_to_put_displacement = NULL;
7364
  offsetT target_address;
7365
  offsetT opcode_address;
7366
  unsigned int extension = 0;
7367
  offsetT displacement_from_opcode_start;
7368
 
7369
  opcode = (unsigned char *) fragP->fr_opcode;
7370
 
7371
  /* Address we want to reach in file space.  */
7372
  target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
7373
 
7374
  /* Address opcode resides at in file space.  */
7375
  opcode_address = fragP->fr_address + fragP->fr_fix;
7376
 
7377
  /* Displacement from opcode start to fill into instruction.  */
7378
  displacement_from_opcode_start = target_address - opcode_address;
7379
 
7380
  if ((fragP->fr_subtype & BIG) == 0)
7381
    {
7382
      /* Don't have to change opcode.  */
7383
      extension = 1;            /* 1 opcode + 1 displacement  */
7384
      where_to_put_displacement = &opcode[1];
7385
    }
7386
  else
7387
    {
7388
      if (no_cond_jump_promotion
7389
          && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
7390
        as_warn_where (fragP->fr_file, fragP->fr_line,
7391
                       _("long jump required"));
7392
 
7393
      switch (fragP->fr_subtype)
7394
        {
7395
        case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7396
          extension = 4;                /* 1 opcode + 4 displacement  */
7397
          opcode[0] = 0xe9;
7398
          where_to_put_displacement = &opcode[1];
7399
          break;
7400
 
7401
        case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7402
          extension = 2;                /* 1 opcode + 2 displacement  */
7403
          opcode[0] = 0xe9;
7404
          where_to_put_displacement = &opcode[1];
7405
          break;
7406
 
7407
        case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7408
        case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7409
          extension = 5;                /* 2 opcode + 4 displacement  */
7410
          opcode[1] = opcode[0] + 0x10;
7411
          opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7412
          where_to_put_displacement = &opcode[2];
7413
          break;
7414
 
7415
        case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7416
          extension = 3;                /* 2 opcode + 2 displacement  */
7417
          opcode[1] = opcode[0] + 0x10;
7418
          opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7419
          where_to_put_displacement = &opcode[2];
7420
          break;
7421
 
7422
        case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7423
          extension = 4;
7424
          opcode[0] ^= 1;
7425
          opcode[1] = 3;
7426
          opcode[2] = 0xe9;
7427
          where_to_put_displacement = &opcode[3];
7428
          break;
7429
 
7430
        default:
7431
          BAD_CASE (fragP->fr_subtype);
7432
          break;
7433
        }
7434
    }
7435
 
7436
  /* If size if less then four we are sure that the operand fits,
7437
     but if it's 4, then it could be that the displacement is larger
7438
     then -/+ 2GB.  */
7439
  if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7440
      && object_64bit
7441
      && ((addressT) (displacement_from_opcode_start - extension
7442
                      + ((addressT) 1 << 31))
7443
          > (((addressT) 2 << 31) - 1)))
7444
    {
7445
      as_bad_where (fragP->fr_file, fragP->fr_line,
7446
                    _("jump target out of range"));
7447
      /* Make us emit 0.  */
7448
      displacement_from_opcode_start = extension;
7449
    }
7450
  /* Now put displacement after opcode.  */
7451
  md_number_to_chars ((char *) where_to_put_displacement,
7452
                      (valueT) (displacement_from_opcode_start - extension),
7453
                      DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
7454
  fragP->fr_fix += extension;
7455
}
7456
 
7457
/* Apply a fixup (fixS) to segment data, once it has been determined
7458
   by our caller that we have all the info we need to fix it up.
7459
 
7460
   On the 386, immediates, displacements, and data pointers are all in
7461
   the same (little-endian) format, so we don't need to care about which
7462
   we are handling.  */
7463
 
7464
void
7465
md_apply_fix (fixP, valP, seg)
7466
     /* The fix we're to put in.  */
7467
     fixS *fixP;
7468
     /* Pointer to the value of the bits.  */
7469
     valueT *valP;
7470
     /* Segment fix is from.  */
7471
     segT seg ATTRIBUTE_UNUSED;
7472
{
7473
  char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
7474
  valueT value = *valP;
7475
 
7476
#if !defined (TE_Mach)
7477
  if (fixP->fx_pcrel)
7478
    {
7479
      switch (fixP->fx_r_type)
7480
        {
7481
        default:
7482
          break;
7483
 
7484
        case BFD_RELOC_64:
7485
          fixP->fx_r_type = BFD_RELOC_64_PCREL;
7486
          break;
7487
        case BFD_RELOC_32:
7488
        case BFD_RELOC_X86_64_32S:
7489
          fixP->fx_r_type = BFD_RELOC_32_PCREL;
7490
          break;
7491
        case BFD_RELOC_16:
7492
          fixP->fx_r_type = BFD_RELOC_16_PCREL;
7493
          break;
7494
        case BFD_RELOC_8:
7495
          fixP->fx_r_type = BFD_RELOC_8_PCREL;
7496
          break;
7497
        }
7498
    }
7499
 
7500
  if (fixP->fx_addsy != NULL
7501
      && (fixP->fx_r_type == BFD_RELOC_32_PCREL
7502
          || fixP->fx_r_type == BFD_RELOC_64_PCREL
7503
          || fixP->fx_r_type == BFD_RELOC_16_PCREL
7504
          || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7505
      && !use_rela_relocations)
7506
    {
7507
      /* This is a hack.  There should be a better way to handle this.
7508
         This covers for the fact that bfd_install_relocation will
7509
         subtract the current location (for partial_inplace, PC relative
7510
         relocations); see more below.  */
7511
#ifndef OBJ_AOUT
7512
      if (IS_ELF
7513
#ifdef TE_PE
7514
          || OUTPUT_FLAVOR == bfd_target_coff_flavour
7515
#endif
7516
          )
7517
        value += fixP->fx_where + fixP->fx_frag->fr_address;
7518
#endif
7519
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7520
      if (IS_ELF)
7521
        {
7522
          segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
7523
 
7524
          if ((sym_seg == seg
7525
               || (symbol_section_p (fixP->fx_addsy)
7526
                   && sym_seg != absolute_section))
7527
              && !generic_force_reloc (fixP))
7528
            {
7529
              /* Yes, we add the values in twice.  This is because
7530
                 bfd_install_relocation subtracts them out again.  I think
7531
                 bfd_install_relocation is broken, but I don't dare change
7532
                 it.  FIXME.  */
7533
              value += fixP->fx_where + fixP->fx_frag->fr_address;
7534
            }
7535
        }
7536
#endif
7537
#if defined (OBJ_COFF) && defined (TE_PE)
7538
      /* For some reason, the PE format does not store a
7539
         section address offset for a PC relative symbol.  */
7540
      if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7541
          || S_IS_WEAK (fixP->fx_addsy))
7542
        value += md_pcrel_from (fixP);
7543
#endif
7544
    }
7545
 
7546
  /* Fix a few things - the dynamic linker expects certain values here,
7547
     and we must not disappoint it.  */
7548
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7549
  if (IS_ELF && fixP->fx_addsy)
7550
    switch (fixP->fx_r_type)
7551
      {
7552
      case BFD_RELOC_386_PLT32:
7553
      case BFD_RELOC_X86_64_PLT32:
7554
        /* Make the jump instruction point to the address of the operand.  At
7555
           runtime we merely add the offset to the actual PLT entry.  */
7556
        value = -4;
7557
        break;
7558
 
7559
      case BFD_RELOC_386_TLS_GD:
7560
      case BFD_RELOC_386_TLS_LDM:
7561
      case BFD_RELOC_386_TLS_IE_32:
7562
      case BFD_RELOC_386_TLS_IE:
7563
      case BFD_RELOC_386_TLS_GOTIE:
7564
      case BFD_RELOC_386_TLS_GOTDESC:
7565
      case BFD_RELOC_X86_64_TLSGD:
7566
      case BFD_RELOC_X86_64_TLSLD:
7567
      case BFD_RELOC_X86_64_GOTTPOFF:
7568
      case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7569
        value = 0; /* Fully resolved at runtime.  No addend.  */
7570
        /* Fallthrough */
7571
      case BFD_RELOC_386_TLS_LE:
7572
      case BFD_RELOC_386_TLS_LDO_32:
7573
      case BFD_RELOC_386_TLS_LE_32:
7574
      case BFD_RELOC_X86_64_DTPOFF32:
7575
      case BFD_RELOC_X86_64_DTPOFF64:
7576
      case BFD_RELOC_X86_64_TPOFF32:
7577
      case BFD_RELOC_X86_64_TPOFF64:
7578
        S_SET_THREAD_LOCAL (fixP->fx_addsy);
7579
        break;
7580
 
7581
      case BFD_RELOC_386_TLS_DESC_CALL:
7582
      case BFD_RELOC_X86_64_TLSDESC_CALL:
7583
        value = 0; /* Fully resolved at runtime.  No addend.  */
7584
        S_SET_THREAD_LOCAL (fixP->fx_addsy);
7585
        fixP->fx_done = 0;
7586
        return;
7587
 
7588
      case BFD_RELOC_386_GOT32:
7589
      case BFD_RELOC_X86_64_GOT32:
7590
        value = 0; /* Fully resolved at runtime.  No addend.  */
7591
        break;
7592
 
7593
      case BFD_RELOC_VTABLE_INHERIT:
7594
      case BFD_RELOC_VTABLE_ENTRY:
7595
        fixP->fx_done = 0;
7596
        return;
7597
 
7598
      default:
7599
        break;
7600
      }
7601
#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)  */
7602
  *valP = value;
7603
#endif /* !defined (TE_Mach)  */
7604
 
7605
  /* Are we finished with this relocation now?  */
7606
  if (fixP->fx_addsy == NULL)
7607
    fixP->fx_done = 1;
7608
  else if (use_rela_relocations)
7609
    {
7610
      fixP->fx_no_overflow = 1;
7611
      /* Remember value for tc_gen_reloc.  */
7612
      fixP->fx_addnumber = value;
7613
      value = 0;
7614
    }
7615
 
7616
  md_number_to_chars (p, value, fixP->fx_size);
7617
}
7618
 
7619
char *
7620
md_atof (int type, char *litP, int *sizeP)
7621
{
7622
  /* This outputs the LITTLENUMs in REVERSE order;
7623
     in accord with the bigendian 386.  */
7624
  return ieee_md_atof (type, litP, sizeP, FALSE);
7625
}
7626
 
7627
static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
7628
 
7629
static char *
7630
output_invalid (int c)
7631
{
7632
  if (ISPRINT (c))
7633
    snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7634
              "'%c'", c);
7635
  else
7636
    snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7637
              "(0x%x)", (unsigned char) c);
7638
  return output_invalid_buf;
7639
}
7640
 
7641
/* REG_STRING starts *before* REGISTER_PREFIX.  */
7642
 
7643
static const reg_entry *
7644
parse_real_register (char *reg_string, char **end_op)
7645
{
7646
  char *s = reg_string;
7647
  char *p;
7648
  char reg_name_given[MAX_REG_NAME_SIZE + 1];
7649
  const reg_entry *r;
7650
 
7651
  /* Skip possible REGISTER_PREFIX and possible whitespace.  */
7652
  if (*s == REGISTER_PREFIX)
7653
    ++s;
7654
 
7655
  if (is_space_char (*s))
7656
    ++s;
7657
 
7658
  p = reg_name_given;
7659
  while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
7660
    {
7661
      if (p >= reg_name_given + MAX_REG_NAME_SIZE)
7662
        return (const reg_entry *) NULL;
7663
      s++;
7664
    }
7665
 
7666
  /* For naked regs, make sure that we are not dealing with an identifier.
7667
     This prevents confusing an identifier like `eax_var' with register
7668
     `eax'.  */
7669
  if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7670
    return (const reg_entry *) NULL;
7671
 
7672
  *end_op = s;
7673
 
7674
  r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7675
 
7676
  /* Handle floating point regs, allowing spaces in the (i) part.  */
7677
  if (r == i386_regtab /* %st is first entry of table  */)
7678
    {
7679
      if (is_space_char (*s))
7680
        ++s;
7681
      if (*s == '(')
7682
        {
7683
          ++s;
7684
          if (is_space_char (*s))
7685
            ++s;
7686
          if (*s >= '0' && *s <= '7')
7687
            {
7688
              int fpr = *s - '0';
7689
              ++s;
7690
              if (is_space_char (*s))
7691
                ++s;
7692
              if (*s == ')')
7693
                {
7694
                  *end_op = s + 1;
7695
                  r = hash_find (reg_hash, "st(0)");
7696
                  know (r);
7697
                  return r + fpr;
7698
                }
7699
            }
7700
          /* We have "%st(" then garbage.  */
7701
          return (const reg_entry *) NULL;
7702
        }
7703
    }
7704
 
7705
  if (r == NULL || allow_pseudo_reg)
7706
    return r;
7707
 
7708
  if (operand_type_all_zero (&r->reg_type))
7709
    return (const reg_entry *) NULL;
7710
 
7711
  if ((r->reg_type.bitfield.reg32
7712
       || r->reg_type.bitfield.sreg3
7713
       || r->reg_type.bitfield.control
7714
       || r->reg_type.bitfield.debug
7715
       || r->reg_type.bitfield.test)
7716
      && !cpu_arch_flags.bitfield.cpui386)
7717
    return (const reg_entry *) NULL;
7718
 
7719
  if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7720
    return (const reg_entry *) NULL;
7721
 
7722
  if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7723
    return (const reg_entry *) NULL;
7724
 
7725
  if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7726
    return (const reg_entry *) NULL;
7727
 
7728
  /* Don't allow fake index register unless allow_index_reg isn't 0. */
7729
  if (!allow_index_reg
7730
      && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7731
    return (const reg_entry *) NULL;
7732
 
7733
  if (((r->reg_flags & (RegRex64 | RegRex))
7734
       || r->reg_type.bitfield.reg64)
7735
      && (!cpu_arch_flags.bitfield.cpulm
7736
          || !operand_type_equal (&r->reg_type, &control))
7737
      && flag_code != CODE_64BIT)
7738
    return (const reg_entry *) NULL;
7739
 
7740
  if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7741
    return (const reg_entry *) NULL;
7742
 
7743
  return r;
7744
}
7745
 
7746
/* REG_STRING starts *before* REGISTER_PREFIX.  */
7747
 
7748
static const reg_entry *
7749
parse_register (char *reg_string, char **end_op)
7750
{
7751
  const reg_entry *r;
7752
 
7753
  if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7754
    r = parse_real_register (reg_string, end_op);
7755
  else
7756
    r = NULL;
7757
  if (!r)
7758
    {
7759
      char *save = input_line_pointer;
7760
      char c;
7761
      symbolS *symbolP;
7762
 
7763
      input_line_pointer = reg_string;
7764
      c = get_symbol_end ();
7765
      symbolP = symbol_find (reg_string);
7766
      if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7767
        {
7768
          const expressionS *e = symbol_get_value_expression (symbolP);
7769
 
7770
          know (e->X_op == O_register);
7771
          know (e->X_add_number >= 0
7772
                && (valueT) e->X_add_number < i386_regtab_size);
7773
          r = i386_regtab + e->X_add_number;
7774
          *end_op = input_line_pointer;
7775
        }
7776
      *input_line_pointer = c;
7777
      input_line_pointer = save;
7778
    }
7779
  return r;
7780
}
7781
 
7782
int
7783
i386_parse_name (char *name, expressionS *e, char *nextcharP)
7784
{
7785
  const reg_entry *r;
7786
  char *end = input_line_pointer;
7787
 
7788
  *end = *nextcharP;
7789
  r = parse_register (name, &input_line_pointer);
7790
  if (r && end <= input_line_pointer)
7791
    {
7792
      *nextcharP = *input_line_pointer;
7793
      *input_line_pointer = 0;
7794
      e->X_op = O_register;
7795
      e->X_add_number = r - i386_regtab;
7796
      return 1;
7797
    }
7798
  input_line_pointer = end;
7799
  *end = 0;
7800
  return 0;
7801
}
7802
 
7803
void
7804
md_operand (expressionS *e)
7805
{
7806
  if (*input_line_pointer == REGISTER_PREFIX)
7807
    {
7808
      char *end;
7809
      const reg_entry *r = parse_real_register (input_line_pointer, &end);
7810
 
7811
      if (r)
7812
        {
7813
          e->X_op = O_register;
7814
          e->X_add_number = r - i386_regtab;
7815
          input_line_pointer = end;
7816
        }
7817
    }
7818
}
7819
 
7820
 
7821
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7822
const char *md_shortopts = "kVQ:sqn";
7823
#else
7824
const char *md_shortopts = "qn";
7825
#endif
7826
 
7827
#define OPTION_32 (OPTION_MD_BASE + 0)
7828
#define OPTION_64 (OPTION_MD_BASE + 1)
7829
#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7830
#define OPTION_MARCH (OPTION_MD_BASE + 3)
7831
#define OPTION_MTUNE (OPTION_MD_BASE + 4)
7832
#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7833
#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7834
#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7835
#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7836
#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7837
#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7838
#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7839
 
7840
struct option md_longopts[] =
7841
{
7842
  {"32", no_argument, NULL, OPTION_32},
7843
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7844
  {"64", no_argument, NULL, OPTION_64},
7845
#endif
7846
  {"divide", no_argument, NULL, OPTION_DIVIDE},
7847
  {"march", required_argument, NULL, OPTION_MARCH},
7848
  {"mtune", required_argument, NULL, OPTION_MTUNE},
7849
  {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7850
  {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7851
  {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7852
  {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7853
  {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
7854
  {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
7855
  {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7856
  {NULL, no_argument, NULL, 0}
7857
};
7858
size_t md_longopts_size = sizeof (md_longopts);
7859
 
7860
int
7861
md_parse_option (int c, char *arg)
7862
{
7863
  unsigned int i;
7864
  char *arch, *next;
7865
 
7866
  switch (c)
7867
    {
7868
    case 'n':
7869
      optimize_align_code = 0;
7870
      break;
7871
 
7872
    case 'q':
7873
      quiet_warnings = 1;
7874
      break;
7875
 
7876
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7877
      /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7878
         should be emitted or not.  FIXME: Not implemented.  */
7879
    case 'Q':
7880
      break;
7881
 
7882
      /* -V: SVR4 argument to print version ID.  */
7883
    case 'V':
7884
      print_version_id ();
7885
      break;
7886
 
7887
      /* -k: Ignore for FreeBSD compatibility.  */
7888
    case 'k':
7889
      break;
7890
 
7891
    case 's':
7892
      /* -s: On i386 Solaris, this tells the native assembler to use
7893
         .stab instead of .stab.excl.  We always use .stab anyhow.  */
7894
      break;
7895
#endif
7896
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7897
    case OPTION_64:
7898
      {
7899
        const char **list, **l;
7900
 
7901
        list = bfd_target_list ();
7902
        for (l = list; *l != NULL; l++)
7903
          if (CONST_STRNEQ (*l, "elf64-x86-64")
7904
              || strcmp (*l, "coff-x86-64") == 0
7905
              || strcmp (*l, "pe-x86-64") == 0
7906
              || strcmp (*l, "pei-x86-64") == 0)
7907
            {
7908
              default_arch = "x86_64";
7909
              break;
7910
            }
7911
        if (*l == NULL)
7912
          as_fatal (_("No compiled in support for x86_64"));
7913
        free (list);
7914
      }
7915
      break;
7916
#endif
7917
 
7918
    case OPTION_32:
7919
      default_arch = "i386";
7920
      break;
7921
 
7922
    case OPTION_DIVIDE:
7923
#ifdef SVR4_COMMENT_CHARS
7924
      {
7925
        char *n, *t;
7926
        const char *s;
7927
 
7928
        n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7929
        t = n;
7930
        for (s = i386_comment_chars; *s != '\0'; s++)
7931
          if (*s != '/')
7932
            *t++ = *s;
7933
        *t = '\0';
7934
        i386_comment_chars = n;
7935
      }
7936
#endif
7937
      break;
7938
 
7939
    case OPTION_MARCH:
7940
      arch = xstrdup (arg);
7941
      do
7942
        {
7943
          if (*arch == '.')
7944
            as_fatal (_("Invalid -march= option: `%s'"), arg);
7945
          next = strchr (arch, '+');
7946
          if (next)
7947
            *next++ = '\0';
7948
          for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7949
            {
7950
              if (strcmp (arch, cpu_arch [i].name) == 0)
7951
                {
7952
                  /* Processor.  */
7953
                  cpu_arch_name = cpu_arch[i].name;
7954
                  cpu_sub_arch_name = NULL;
7955
                  cpu_arch_flags = cpu_arch[i].flags;
7956
                  cpu_arch_isa = cpu_arch[i].type;
7957
                  cpu_arch_isa_flags = cpu_arch[i].flags;
7958
                  if (!cpu_arch_tune_set)
7959
                    {
7960
                      cpu_arch_tune = cpu_arch_isa;
7961
                      cpu_arch_tune_flags = cpu_arch_isa_flags;
7962
                    }
7963
                  break;
7964
                }
7965
              else if (*cpu_arch [i].name == '.'
7966
                       && strcmp (arch, cpu_arch [i].name + 1) == 0)
7967
                {
7968
                  /* ISA entension.  */
7969
                  i386_cpu_flags flags;
7970
                  flags = cpu_flags_or (cpu_arch_flags,
7971
                                        cpu_arch[i].flags);
7972
                  if (!cpu_flags_equal (&flags, &cpu_arch_flags))
7973
                    {
7974
                      if (cpu_sub_arch_name)
7975
                        {
7976
                          char *name = cpu_sub_arch_name;
7977
                          cpu_sub_arch_name = concat (name,
7978
                                                      cpu_arch[i].name,
7979
                                                      (const char *) NULL);
7980
                          free (name);
7981
                        }
7982
                      else
7983
                        cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7984
                      cpu_arch_flags = flags;
7985
                    }
7986
                  break;
7987
                }
7988
            }
7989
 
7990
          if (i >= ARRAY_SIZE (cpu_arch))
7991
            as_fatal (_("Invalid -march= option: `%s'"), arg);
7992
 
7993
          arch = next;
7994
        }
7995
      while (next != NULL );
7996
      break;
7997
 
7998
    case OPTION_MTUNE:
7999
      if (*arg == '.')
8000
        as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8001
      for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8002
        {
8003
          if (strcmp (arg, cpu_arch [i].name) == 0)
8004
            {
8005
              cpu_arch_tune_set = 1;
8006
              cpu_arch_tune = cpu_arch [i].type;
8007
              cpu_arch_tune_flags = cpu_arch[i].flags;
8008
              break;
8009
            }
8010
        }
8011
      if (i >= ARRAY_SIZE (cpu_arch))
8012
        as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8013
      break;
8014
 
8015
    case OPTION_MMNEMONIC:
8016
      if (strcasecmp (arg, "att") == 0)
8017
        intel_mnemonic = 0;
8018
      else if (strcasecmp (arg, "intel") == 0)
8019
        intel_mnemonic = 1;
8020
      else
8021
        as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8022
      break;
8023
 
8024
    case OPTION_MSYNTAX:
8025
      if (strcasecmp (arg, "att") == 0)
8026
        intel_syntax = 0;
8027
      else if (strcasecmp (arg, "intel") == 0)
8028
        intel_syntax = 1;
8029
      else
8030
        as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8031
      break;
8032
 
8033
    case OPTION_MINDEX_REG:
8034
      allow_index_reg = 1;
8035
      break;
8036
 
8037
    case OPTION_MNAKED_REG:
8038
      allow_naked_reg = 1;
8039
      break;
8040
 
8041
    case OPTION_MOLD_GCC:
8042
      old_gcc = 1;
8043
      break;
8044
 
8045
    case OPTION_MSSE2AVX:
8046
      sse2avx = 1;
8047
      break;
8048
 
8049
    case OPTION_MSSE_CHECK:
8050
      if (strcasecmp (arg, "error") == 0)
8051
        sse_check = sse_check_error;
8052
      else if (strcasecmp (arg, "warning") == 0)
8053
        sse_check = sse_check_warning;
8054
      else if (strcasecmp (arg, "none") == 0)
8055
        sse_check = sse_check_none;
8056
      else
8057
        as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8058
      break;
8059
 
8060
    default:
8061
      return 0;
8062
    }
8063
  return 1;
8064
}
8065
 
8066
void
8067
md_show_usage (stream)
8068
     FILE *stream;
8069
{
8070
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8071
  fprintf (stream, _("\
8072
  -Q                      ignored\n\
8073
  -V                      print assembler version number\n\
8074
  -k                      ignored\n"));
8075
#endif
8076
  fprintf (stream, _("\
8077
  -n                      Do not optimize code alignment\n\
8078
  -q                      quieten some warnings\n"));
8079
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8080
  fprintf (stream, _("\
8081
  -s                      ignored\n"));
8082
#endif
8083
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8084
  fprintf (stream, _("\
8085
  --32/--64               generate 32bit/64bit code\n"));
8086
#endif
8087
#ifdef SVR4_COMMENT_CHARS
8088
  fprintf (stream, _("\
8089
  --divide                do not treat `/' as a comment character\n"));
8090
#else
8091
  fprintf (stream, _("\
8092
  --divide                ignored\n"));
8093
#endif
8094
  fprintf (stream, _("\
8095
  -march=CPU[,+EXTENSION...]\n\
8096
                          generate code for CPU and EXTENSION, CPU is one of:\n\
8097
                           i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8098
                           pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8099
                           core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8100
                           generic32, generic64\n\
8101
                          EXTENSION is combination of:\n\
8102
                           mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8103
                           avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8104
                           3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
8105
  fprintf (stream, _("\
8106
  -mtune=CPU              optimize for CPU, CPU is one of:\n\
8107
                           i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8108
                           pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8109
                           core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8110
                           generic32, generic64\n"));
8111
  fprintf (stream, _("\
8112
  -msse2avx               encode SSE instructions with VEX prefix\n"));
8113
  fprintf (stream, _("\
8114
  -msse-check=[none|error|warning]\n\
8115
                          check SSE instructions\n"));
8116
  fprintf (stream, _("\
8117
  -mmnemonic=[att|intel]  use AT&T/Intel mnemonic\n"));
8118
  fprintf (stream, _("\
8119
  -msyntax=[att|intel]    use AT&T/Intel syntax\n"));
8120
  fprintf (stream, _("\
8121
  -mindex-reg             support pseudo index registers\n"));
8122
  fprintf (stream, _("\
8123
  -mnaked-reg             don't require `%%' prefix for registers\n"));
8124
  fprintf (stream, _("\
8125
  -mold-gcc               support old (<= 2.8.1) versions of gcc\n"));
8126
}
8127
 
8128
#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8129
     || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8130
 
8131
/* Pick the target format to use.  */
8132
 
8133
const char *
8134
i386_target_format (void)
8135
{
8136
  if (!strcmp (default_arch, "x86_64"))
8137
    {
8138
      set_code_flag (CODE_64BIT);
8139
      if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8140
        {
8141
          cpu_arch_isa_flags.bitfield.cpui186 = 1;
8142
          cpu_arch_isa_flags.bitfield.cpui286 = 1;
8143
          cpu_arch_isa_flags.bitfield.cpui386 = 1;
8144
          cpu_arch_isa_flags.bitfield.cpui486 = 1;
8145
          cpu_arch_isa_flags.bitfield.cpui586 = 1;
8146
          cpu_arch_isa_flags.bitfield.cpui686 = 1;
8147
          cpu_arch_isa_flags.bitfield.cpup4 = 1;
8148
          cpu_arch_isa_flags.bitfield.cpummx= 1;
8149
          cpu_arch_isa_flags.bitfield.cpusse = 1;
8150
          cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8151
        }
8152
      if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8153
        {
8154
          cpu_arch_tune_flags.bitfield.cpui186 = 1;
8155
          cpu_arch_tune_flags.bitfield.cpui286 = 1;
8156
          cpu_arch_tune_flags.bitfield.cpui386 = 1;
8157
          cpu_arch_tune_flags.bitfield.cpui486 = 1;
8158
          cpu_arch_tune_flags.bitfield.cpui586 = 1;
8159
          cpu_arch_tune_flags.bitfield.cpui686 = 1;
8160
          cpu_arch_tune_flags.bitfield.cpup4 = 1;
8161
          cpu_arch_tune_flags.bitfield.cpummx= 1;
8162
          cpu_arch_tune_flags.bitfield.cpusse = 1;
8163
          cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8164
        }
8165
    }
8166
  else if (!strcmp (default_arch, "i386"))
8167
    {
8168
      set_code_flag (CODE_32BIT);
8169
      if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8170
        {
8171
          cpu_arch_isa_flags.bitfield.cpui186 = 1;
8172
          cpu_arch_isa_flags.bitfield.cpui286 = 1;
8173
          cpu_arch_isa_flags.bitfield.cpui386 = 1;
8174
        }
8175
      if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8176
        {
8177
          cpu_arch_tune_flags.bitfield.cpui186 = 1;
8178
          cpu_arch_tune_flags.bitfield.cpui286 = 1;
8179
          cpu_arch_tune_flags.bitfield.cpui386 = 1;
8180
        }
8181
    }
8182
  else
8183
    as_fatal (_("Unknown architecture"));
8184
  switch (OUTPUT_FLAVOR)
8185
    {
8186
#ifdef TE_PEP
8187
    case bfd_target_coff_flavour:
8188
      return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
8189
      break;
8190
#endif
8191
#ifdef OBJ_MAYBE_AOUT
8192
    case bfd_target_aout_flavour:
8193
      return AOUT_TARGET_FORMAT;
8194
#endif
8195
#ifdef OBJ_MAYBE_COFF
8196
    case bfd_target_coff_flavour:
8197
      return "coff-i386";
8198
#endif
8199
#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8200
    case bfd_target_elf_flavour:
8201
      {
8202
        if (flag_code == CODE_64BIT)
8203
          {
8204
            object_64bit = 1;
8205
            use_rela_relocations = 1;
8206
          }
8207
        return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
8208
      }
8209
#endif
8210
    default:
8211
      abort ();
8212
      return NULL;
8213
    }
8214
}
8215
 
8216
#endif /* OBJ_MAYBE_ more than one  */
8217
 
8218
#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8219
void
8220
i386_elf_emit_arch_note (void)
8221
{
8222
  if (IS_ELF && cpu_arch_name != NULL)
8223
    {
8224
      char *p;
8225
      asection *seg = now_seg;
8226
      subsegT subseg = now_subseg;
8227
      Elf_Internal_Note i_note;
8228
      Elf_External_Note e_note;
8229
      asection *note_secp;
8230
      int len;
8231
 
8232
      /* Create the .note section.  */
8233
      note_secp = subseg_new (".note", 0);
8234
      bfd_set_section_flags (stdoutput,
8235
                             note_secp,
8236
                             SEC_HAS_CONTENTS | SEC_READONLY);
8237
 
8238
      /* Process the arch string.  */
8239
      len = strlen (cpu_arch_name);
8240
 
8241
      i_note.namesz = len + 1;
8242
      i_note.descsz = 0;
8243
      i_note.type = NT_ARCH;
8244
      p = frag_more (sizeof (e_note.namesz));
8245
      md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8246
      p = frag_more (sizeof (e_note.descsz));
8247
      md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8248
      p = frag_more (sizeof (e_note.type));
8249
      md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8250
      p = frag_more (len + 1);
8251
      strcpy (p, cpu_arch_name);
8252
 
8253
      frag_align (2, 0, 0);
8254
 
8255
      subseg_set (seg, subseg);
8256
    }
8257
}
8258
#endif
8259
 
8260
symbolS *
8261
md_undefined_symbol (name)
8262
     char *name;
8263
{
8264
  if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8265
      && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8266
      && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8267
      && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
8268
    {
8269
      if (!GOT_symbol)
8270
        {
8271
          if (symbol_find (name))
8272
            as_bad (_("GOT already in symbol table"));
8273
          GOT_symbol = symbol_new (name, undefined_section,
8274
                                   (valueT) 0, &zero_address_frag);
8275
        };
8276
      return GOT_symbol;
8277
    }
8278
  return 0;
8279
}
8280
 
8281
/* Round up a section size to the appropriate boundary.  */
8282
 
8283
valueT
8284
md_section_align (segment, size)
8285
     segT segment ATTRIBUTE_UNUSED;
8286
     valueT size;
8287
{
8288
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8289
  if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8290
    {
8291
      /* For a.out, force the section size to be aligned.  If we don't do
8292
         this, BFD will align it for us, but it will not write out the
8293
         final bytes of the section.  This may be a bug in BFD, but it is
8294
         easier to fix it here since that is how the other a.out targets
8295
         work.  */
8296
      int align;
8297
 
8298
      align = bfd_get_section_alignment (stdoutput, segment);
8299
      size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8300
    }
8301
#endif
8302
 
8303
  return size;
8304
}
8305
 
8306
/* On the i386, PC-relative offsets are relative to the start of the
8307
   next instruction.  That is, the address of the offset, plus its
8308
   size, since the offset is always the last part of the insn.  */
8309
 
8310
long
8311
md_pcrel_from (fixS *fixP)
8312
{
8313
  return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8314
}
8315
 
8316
#ifndef I386COFF
8317
 
8318
static void
8319
s_bss (int ignore ATTRIBUTE_UNUSED)
8320
{
8321
  int temp;
8322
 
8323
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8324
  if (IS_ELF)
8325
    obj_elf_section_change_hook ();
8326
#endif
8327
  temp = get_absolute_expression ();
8328
  subseg_set (bss_section, (subsegT) temp);
8329
  demand_empty_rest_of_line ();
8330
}
8331
 
8332
#endif
8333
 
8334
void
8335
i386_validate_fix (fixS *fixp)
8336
{
8337
  if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8338
    {
8339
      if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8340
        {
8341
          if (!object_64bit)
8342
            abort ();
8343
          fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8344
        }
8345
      else
8346
        {
8347
          if (!object_64bit)
8348
            fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8349
          else
8350
            fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
8351
        }
8352
      fixp->fx_subsy = 0;
8353
    }
8354
}
8355
 
8356
arelent *
8357
tc_gen_reloc (section, fixp)
8358
     asection *section ATTRIBUTE_UNUSED;
8359
     fixS *fixp;
8360
{
8361
  arelent *rel;
8362
  bfd_reloc_code_real_type code;
8363
 
8364
  switch (fixp->fx_r_type)
8365
    {
8366
    case BFD_RELOC_X86_64_PLT32:
8367
    case BFD_RELOC_X86_64_GOT32:
8368
    case BFD_RELOC_X86_64_GOTPCREL:
8369
    case BFD_RELOC_386_PLT32:
8370
    case BFD_RELOC_386_GOT32:
8371
    case BFD_RELOC_386_GOTOFF:
8372
    case BFD_RELOC_386_GOTPC:
8373
    case BFD_RELOC_386_TLS_GD:
8374
    case BFD_RELOC_386_TLS_LDM:
8375
    case BFD_RELOC_386_TLS_LDO_32:
8376
    case BFD_RELOC_386_TLS_IE_32:
8377
    case BFD_RELOC_386_TLS_IE:
8378
    case BFD_RELOC_386_TLS_GOTIE:
8379
    case BFD_RELOC_386_TLS_LE_32:
8380
    case BFD_RELOC_386_TLS_LE:
8381
    case BFD_RELOC_386_TLS_GOTDESC:
8382
    case BFD_RELOC_386_TLS_DESC_CALL:
8383
    case BFD_RELOC_X86_64_TLSGD:
8384
    case BFD_RELOC_X86_64_TLSLD:
8385
    case BFD_RELOC_X86_64_DTPOFF32:
8386
    case BFD_RELOC_X86_64_DTPOFF64:
8387
    case BFD_RELOC_X86_64_GOTTPOFF:
8388
    case BFD_RELOC_X86_64_TPOFF32:
8389
    case BFD_RELOC_X86_64_TPOFF64:
8390
    case BFD_RELOC_X86_64_GOTOFF64:
8391
    case BFD_RELOC_X86_64_GOTPC32:
8392
    case BFD_RELOC_X86_64_GOT64:
8393
    case BFD_RELOC_X86_64_GOTPCREL64:
8394
    case BFD_RELOC_X86_64_GOTPC64:
8395
    case BFD_RELOC_X86_64_GOTPLT64:
8396
    case BFD_RELOC_X86_64_PLTOFF64:
8397
    case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8398
    case BFD_RELOC_X86_64_TLSDESC_CALL:
8399
    case BFD_RELOC_RVA:
8400
    case BFD_RELOC_VTABLE_ENTRY:
8401
    case BFD_RELOC_VTABLE_INHERIT:
8402
#ifdef TE_PE
8403
    case BFD_RELOC_32_SECREL:
8404
#endif
8405
      code = fixp->fx_r_type;
8406
      break;
8407
    case BFD_RELOC_X86_64_32S:
8408
      if (!fixp->fx_pcrel)
8409
        {
8410
          /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32.  */
8411
          code = fixp->fx_r_type;
8412
          break;
8413
        }
8414
    default:
8415
      if (fixp->fx_pcrel)
8416
        {
8417
          switch (fixp->fx_size)
8418
            {
8419
            default:
8420
              as_bad_where (fixp->fx_file, fixp->fx_line,
8421
                            _("can not do %d byte pc-relative relocation"),
8422
                            fixp->fx_size);
8423
              code = BFD_RELOC_32_PCREL;
8424
              break;
8425
            case 1: code = BFD_RELOC_8_PCREL;  break;
8426
            case 2: code = BFD_RELOC_16_PCREL; break;
8427
            case 4: code = BFD_RELOC_32_PCREL; break;
8428
#ifdef BFD64
8429
            case 8: code = BFD_RELOC_64_PCREL; break;
8430
#endif
8431
            }
8432
        }
8433
      else
8434
        {
8435
          switch (fixp->fx_size)
8436
            {
8437
            default:
8438
              as_bad_where (fixp->fx_file, fixp->fx_line,
8439
                            _("can not do %d byte relocation"),
8440
                            fixp->fx_size);
8441
              code = BFD_RELOC_32;
8442
              break;
8443
            case 1: code = BFD_RELOC_8;  break;
8444
            case 2: code = BFD_RELOC_16; break;
8445
            case 4: code = BFD_RELOC_32; break;
8446
#ifdef BFD64
8447
            case 8: code = BFD_RELOC_64; break;
8448
#endif
8449
            }
8450
        }
8451
      break;
8452
    }
8453
 
8454
  if ((code == BFD_RELOC_32
8455
       || code == BFD_RELOC_32_PCREL
8456
       || code == BFD_RELOC_X86_64_32S)
8457
      && GOT_symbol
8458
      && fixp->fx_addsy == GOT_symbol)
8459
    {
8460
      if (!object_64bit)
8461
        code = BFD_RELOC_386_GOTPC;
8462
      else
8463
        code = BFD_RELOC_X86_64_GOTPC32;
8464
    }
8465
  if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8466
      && GOT_symbol
8467
      && fixp->fx_addsy == GOT_symbol)
8468
    {
8469
      code = BFD_RELOC_X86_64_GOTPC64;
8470
    }
8471
 
8472
  rel = (arelent *) xmalloc (sizeof (arelent));
8473
  rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8474
  *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
8475
 
8476
  rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
8477
 
8478
  if (!use_rela_relocations)
8479
    {
8480
      /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8481
         vtable entry to be used in the relocation's section offset.  */
8482
      if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8483
        rel->address = fixp->fx_offset;
8484
 
8485
      rel->addend = 0;
8486
    }
8487
  /* Use the rela in 64bit mode.  */
8488
  else
8489
    {
8490
      if (!fixp->fx_pcrel)
8491
        rel->addend = fixp->fx_offset;
8492
      else
8493
        switch (code)
8494
          {
8495
          case BFD_RELOC_X86_64_PLT32:
8496
          case BFD_RELOC_X86_64_GOT32:
8497
          case BFD_RELOC_X86_64_GOTPCREL:
8498
          case BFD_RELOC_X86_64_TLSGD:
8499
          case BFD_RELOC_X86_64_TLSLD:
8500
          case BFD_RELOC_X86_64_GOTTPOFF:
8501
          case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8502
          case BFD_RELOC_X86_64_TLSDESC_CALL:
8503
            rel->addend = fixp->fx_offset - fixp->fx_size;
8504
            break;
8505
          default:
8506
            rel->addend = (section->vma
8507
                           - fixp->fx_size
8508
                           + fixp->fx_addnumber
8509
                           + md_pcrel_from (fixp));
8510
            break;
8511
          }
8512
    }
8513
 
8514
  rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8515
  if (rel->howto == NULL)
8516
    {
8517
      as_bad_where (fixp->fx_file, fixp->fx_line,
8518
                    _("cannot represent relocation type %s"),
8519
                    bfd_get_reloc_code_name (code));
8520
      /* Set howto to a garbage value so that we can keep going.  */
8521
      rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8522
      assert (rel->howto != NULL);
8523
    }
8524
 
8525
  return rel;
8526
}
8527
 
8528
 
8529
/* Parse operands using Intel syntax. This implements a recursive descent
8530
   parser based on the BNF grammar published in Appendix B of the MASM 6.1
8531
   Programmer's Guide.
8532
 
8533
   FIXME: We do not recognize the full operand grammar defined in the MASM
8534
          documentation.  In particular, all the structure/union and
8535
          high-level macro operands are missing.
8536
 
8537
   Uppercase words are terminals, lower case words are non-terminals.
8538
   Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8539
   bars '|' denote choices. Most grammar productions are implemented in
8540
   functions called 'intel_<production>'.
8541
 
8542
   Initial production is 'expr'.
8543
 
8544
    addOp               + | -
8545
 
8546
    alpha               [a-zA-Z]
8547
 
8548
    binOp               & | AND | \| | OR | ^ | XOR
8549
 
8550
    byteRegister        AL | AH | BL | BH | CL | CH | DL | DH
8551
 
8552
    constant            digits [[ radixOverride ]]
8553
 
8554
    dataType            BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8555
 
8556
    digits              decdigit
8557
                        | digits decdigit
8558
                        | digits hexdigit
8559
 
8560
    decdigit            [0-9]
8561
 
8562
    e04                 e04 addOp e05
8563
                        | e05
8564
 
8565
    e05                 e05 binOp e06
8566
                        | e06
8567
 
8568
    e06                 e06 mulOp e09
8569
                        | e09
8570
 
8571
    e09                 OFFSET e10
8572
                        | SHORT e10
8573
                        | + e10
8574
                        | - e10
8575
                        | ~ e10
8576
                        | NOT e10
8577
                        | e09 PTR e10
8578
                        | e09 : e10
8579
                        | e10
8580
 
8581
    e10                 e10 [ expr ]
8582
                        | e11
8583
 
8584
    e11                 ( expr )
8585
                        | [ expr ]
8586
                        | constant
8587
                        | dataType
8588
                        | id
8589
                        | $
8590
                        | register
8591
 
8592
 => expr                expr cmpOp e04
8593
                        | e04
8594
 
8595
    gpRegister          AX | EAX | BX | EBX | CX | ECX | DX | EDX
8596
                        | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8597
 
8598
    hexdigit            a | b | c | d | e | f
8599
                        | A | B | C | D | E | F
8600
 
8601
    id                  alpha
8602
                        | id alpha
8603
                        | id decdigit
8604
 
8605
    mulOp               * | / | % | MOD | << | SHL | >> | SHR
8606
 
8607
    quote               " | '
8608
 
8609
    register            specialRegister
8610
                        | gpRegister
8611
                        | byteRegister
8612
 
8613
    segmentRegister     CS | DS | ES | FS | GS | SS
8614
 
8615
    specialRegister     CR0 | CR2 | CR3 | CR4
8616
                        | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8617
                        | TR3 | TR4 | TR5 | TR6 | TR7
8618
 
8619
    We simplify the grammar in obvious places (e.g., register parsing is
8620
    done by calling parse_register) and eliminate immediate left recursion
8621
    to implement a recursive-descent parser.
8622
 
8623
    expr        e04 expr'
8624
 
8625
    expr'       cmpOp e04 expr'
8626
                | Empty
8627
 
8628
    e04         e05 e04'
8629
 
8630
    e04'        addOp e05 e04'
8631
                | Empty
8632
 
8633
    e05         e06 e05'
8634
 
8635
    e05'        binOp e06 e05'
8636
                | Empty
8637
 
8638
    e06         e09 e06'
8639
 
8640
    e06'        mulOp e09 e06'
8641
                | Empty
8642
 
8643
    e09         OFFSET e10 e09'
8644
                | SHORT e10'
8645
                | + e10'
8646
                | - e10'
8647
                | ~ e10'
8648
                | NOT e10'
8649
                | e10 e09'
8650
 
8651
    e09'        PTR e10 e09'
8652
                | : e10 e09'
8653
                | Empty
8654
 
8655
    e10         e11 e10'
8656
 
8657
    e10'        [ expr ] e10'
8658
                | Empty
8659
 
8660
    e11         ( expr )
8661
                | [ expr ]
8662
                | BYTE
8663
                | WORD
8664
                | DWORD
8665
                | FWORD
8666
                | QWORD
8667
                | TBYTE
8668
                | OWORD
8669
                | XMMWORD
8670
                | YMMWORD
8671
                | .
8672
                | $
8673
                | register
8674
                | id
8675
                | constant  */
8676
 
8677
/* Parsing structure for the intel syntax parser. Used to implement the
8678
   semantic actions for the operand grammar.  */
8679
struct intel_parser_s
8680
  {
8681
    char *op_string;            /* The string being parsed.  */
8682
    int got_a_float;            /* Whether the operand is a float.  */
8683
    int op_modifier;            /* Operand modifier.  */
8684
    int is_mem;                 /* 1 if operand is memory reference.  */
8685
    int in_offset;              /* >=1 if parsing operand of offset.  */
8686
    int in_bracket;             /* >=1 if parsing operand in brackets.  */
8687
    const reg_entry *reg;       /* Last register reference found.  */
8688
    char *disp;                 /* Displacement string being built.  */
8689
    char *next_operand;         /* Resume point when splitting operands.  */
8690
  };
8691
 
8692
static struct intel_parser_s intel_parser;
8693
 
8694
/* Token structure for parsing intel syntax.  */
8695
struct intel_token
8696
  {
8697
    int code;                   /* Token code.  */
8698
    const reg_entry *reg;       /* Register entry for register tokens.  */
8699
    char *str;                  /* String representation.  */
8700
  };
8701
 
8702
static struct intel_token cur_token, prev_token;
8703
 
8704
/* Token codes for the intel parser. Since T_SHORT is already used
8705
   by COFF, undefine it first to prevent a warning.  */
8706
#define T_NIL           -1
8707
#define T_CONST         1
8708
#define T_REG           2
8709
#define T_BYTE          3
8710
#define T_WORD          4
8711
#define T_DWORD         5
8712
#define T_FWORD         6
8713
#define T_QWORD         7
8714
#define T_TBYTE         8
8715
#define T_XMMWORD       9
8716
#undef  T_SHORT
8717
#define T_SHORT         10
8718
#define T_OFFSET        11
8719
#define T_PTR           12
8720
#define T_ID            13
8721
#define T_SHL           14
8722
#define T_SHR           15
8723
#define T_YMMWORD       16
8724
 
8725
/* Prototypes for intel parser functions.  */
8726
static int intel_match_token (int);
8727
static void intel_putback_token (void);
8728
static void intel_get_token (void);
8729
static int intel_expr (void);
8730
static int intel_e04 (void);
8731
static int intel_e05 (void);
8732
static int intel_e06 (void);
8733
static int intel_e09 (void);
8734
static int intel_e10 (void);
8735
static int intel_e11 (void);
8736
 
8737
static int
8738
i386_intel_operand (char *operand_string, int got_a_float)
8739
{
8740
  int ret;
8741
  char *p;
8742
 
8743
  p = intel_parser.op_string = xstrdup (operand_string);
8744
  intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8745
 
8746
  for (;;)
8747
    {
8748
      /* Initialize token holders.  */
8749
      cur_token.code = prev_token.code = T_NIL;
8750
      cur_token.reg = prev_token.reg = NULL;
8751
      cur_token.str = prev_token.str = NULL;
8752
 
8753
      /* Initialize parser structure.  */
8754
      intel_parser.got_a_float = got_a_float;
8755
      intel_parser.op_modifier = 0;
8756
      intel_parser.is_mem = 0;
8757
      intel_parser.in_offset = 0;
8758
      intel_parser.in_bracket = 0;
8759
      intel_parser.reg = NULL;
8760
      intel_parser.disp[0] = '\0';
8761
      intel_parser.next_operand = NULL;
8762
 
8763
      /* Read the first token and start the parser.  */
8764
      intel_get_token ();
8765
      ret = intel_expr ();
8766
 
8767
      if (!ret)
8768
        break;
8769
 
8770
      if (cur_token.code != T_NIL)
8771
        {
8772
          as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8773
                  current_templates->start->name, cur_token.str);
8774
          ret = 0;
8775
        }
8776
      /* If we found a memory reference, hand it over to i386_displacement
8777
         to fill in the rest of the operand fields.  */
8778
      else if (intel_parser.is_mem)
8779
        {
8780
          if ((i.mem_operands == 1
8781
               && !current_templates->start->opcode_modifier.isstring)
8782
              || i.mem_operands == 2)
8783
            {
8784
              as_bad (_("too many memory references for '%s'"),
8785
                      current_templates->start->name);
8786
              ret = 0;
8787
            }
8788
          else
8789
            {
8790
              char *s = intel_parser.disp;
8791
              i.types[this_operand].bitfield.mem = 1;
8792
              i.mem_operands++;
8793
 
8794
              if (!quiet_warnings && intel_parser.is_mem < 0)
8795
                /* See the comments in intel_bracket_expr.  */
8796
                as_warn (_("Treating `%s' as memory reference"), operand_string);
8797
 
8798
              /* Add the displacement expression.  */
8799
              if (*s != '\0')
8800
                ret = i386_displacement (s, s + strlen (s));
8801
              if (ret)
8802
                {
8803
                  /* Swap base and index in 16-bit memory operands like
8804
                     [si+bx]. Since i386_index_check is also used in AT&T
8805
                     mode we have to do that here.  */
8806
                  if (i.base_reg
8807
                      && i.index_reg
8808
                      && i.base_reg->reg_type.bitfield.reg16
8809
                      && i.index_reg->reg_type.bitfield.reg16
8810
                      && i.base_reg->reg_num >= 6
8811
                      && i.index_reg->reg_num < 6)
8812
                    {
8813
                      const reg_entry *base = i.index_reg;
8814
 
8815
                      i.index_reg = i.base_reg;
8816
                      i.base_reg = base;
8817
                    }
8818
                  ret = i386_index_check (operand_string);
8819
                }
8820
            }
8821
        }
8822
 
8823
      /* Constant and OFFSET expressions are handled by i386_immediate.  */
8824
      else if ((intel_parser.op_modifier & (1 << T_OFFSET))
8825
               || intel_parser.reg == NULL)
8826
        {
8827
          if (i.mem_operands < 2 && i.seg[i.mem_operands])
8828
            {
8829
              if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8830
                as_warn (_("Segment override ignored"));
8831
              i.seg[i.mem_operands] = NULL;
8832
            }
8833
          ret = i386_immediate (intel_parser.disp);
8834
        }
8835
 
8836
      if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
8837
        ret = 0;
8838
      if (!ret || !intel_parser.next_operand)
8839
        break;
8840
      intel_parser.op_string = intel_parser.next_operand;
8841
      this_operand = i.operands++;
8842
      i.types[this_operand].bitfield.unspecified = 1;
8843
    }
8844
 
8845
  free (p);
8846
  free (intel_parser.disp);
8847
 
8848
  return ret;
8849
}
8850
 
8851
#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8852
 
8853
/* expr e04 expr'
8854
 
8855
   expr'  cmpOp e04 expr'
8856
        | Empty  */
8857
static int
8858
intel_expr (void)
8859
{
8860
  /* XXX Implement the comparison operators.  */
8861
  return intel_e04 ();
8862
}
8863
 
8864
/* e04  e05 e04'
8865
 
8866
   e04' addOp e05 e04'
8867
        | Empty  */
8868
static int
8869
intel_e04 (void)
8870
{
8871
  int nregs = -1;
8872
 
8873
  for (;;)
8874
    {
8875
      if (!intel_e05())
8876
        return 0;
8877
 
8878
      if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8879
        i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
8880
 
8881
      if (cur_token.code == '+')
8882
        nregs = -1;
8883
      else if (cur_token.code == '-')
8884
        nregs = NUM_ADDRESS_REGS;
8885
      else
8886
        return 1;
8887
 
8888
      strcat (intel_parser.disp, cur_token.str);
8889
      intel_match_token (cur_token.code);
8890
    }
8891
}
8892
 
8893
/* e05  e06 e05'
8894
 
8895
   e05' binOp e06 e05'
8896
        | Empty  */
8897
static int
8898
intel_e05 (void)
8899
{
8900
  int nregs = ~NUM_ADDRESS_REGS;
8901
 
8902
  for (;;)
8903
    {
8904
      if (!intel_e06())
8905
        return 0;
8906
 
8907
      if (cur_token.code == '&'
8908
          || cur_token.code == '|'
8909
          || cur_token.code == '^')
8910
        {
8911
          char str[2];
8912
 
8913
          str[0] = cur_token.code;
8914
          str[1] = 0;
8915
          strcat (intel_parser.disp, str);
8916
        }
8917
      else
8918
        break;
8919
 
8920
      intel_match_token (cur_token.code);
8921
 
8922
      if (nregs < 0)
8923
        nregs = ~nregs;
8924
    }
8925
  if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8926
    i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8927
  return 1;
8928
}
8929
 
8930
/* e06  e09 e06'
8931
 
8932
   e06' mulOp e09 e06'
8933
        | Empty  */
8934
static int
8935
intel_e06 (void)
8936
{
8937
  int nregs = ~NUM_ADDRESS_REGS;
8938
 
8939
  for (;;)
8940
    {
8941
      if (!intel_e09())
8942
        return 0;
8943
 
8944
      if (cur_token.code == '*'
8945
          || cur_token.code == '/'
8946
          || cur_token.code == '%')
8947
        {
8948
          char str[2];
8949
 
8950
          str[0] = cur_token.code;
8951
          str[1] = 0;
8952
          strcat (intel_parser.disp, str);
8953
        }
8954
      else if (cur_token.code == T_SHL)
8955
        strcat (intel_parser.disp, "<<");
8956
      else if (cur_token.code == T_SHR)
8957
        strcat (intel_parser.disp, ">>");
8958
      else
8959
        break;
8960
 
8961
      intel_match_token (cur_token.code);
8962
 
8963
      if (nregs < 0)
8964
        nregs = ~nregs;
8965
    }
8966
  if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8967
    i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8968
  return 1;
8969
}
8970
 
8971
/* e09  OFFSET e09
8972
        | SHORT e09
8973
        | + e09
8974
        | - e09
8975
        | ~ e09
8976
        | NOT e09
8977
        | e10 e09'
8978
 
8979
   e09' PTR e10 e09'
8980
        | : e10 e09'
8981
        | Empty */
8982
static int
8983
intel_e09 (void)
8984
{
8985
  int nregs = ~NUM_ADDRESS_REGS;
8986
  int in_offset = 0;
8987
 
8988
  for (;;)
8989
    {
8990
      /* Don't consume constants here.  */
8991
      if (cur_token.code == '+' || cur_token.code == '-')
8992
        {
8993
          /* Need to look one token ahead - if the next token
8994
             is a constant, the current token is its sign.  */
8995
          int next_code;
8996
 
8997
          intel_match_token (cur_token.code);
8998
          next_code = cur_token.code;
8999
          intel_putback_token ();
9000
          if (next_code == T_CONST)
9001
            break;
9002
        }
9003
 
9004
      /* e09  OFFSET e09  */
9005
      if (cur_token.code == T_OFFSET)
9006
        {
9007
          if (!in_offset++)
9008
            ++intel_parser.in_offset;
9009
        }
9010
 
9011
      /* e09  SHORT e09  */
9012
      else if (cur_token.code == T_SHORT)
9013
        intel_parser.op_modifier |= 1 << T_SHORT;
9014
 
9015
      /* e09  + e09  */
9016
      else if (cur_token.code == '+')
9017
        strcat (intel_parser.disp, "+");
9018
 
9019
      /* e09  - e09
9020
              | ~ e09
9021
              | NOT e09  */
9022
      else if (cur_token.code == '-' || cur_token.code == '~')
9023
        {
9024
          char str[2];
9025
 
9026
          if (nregs < 0)
9027
            nregs = ~nregs;
9028
          str[0] = cur_token.code;
9029
          str[1] = 0;
9030
          strcat (intel_parser.disp, str);
9031
        }
9032
 
9033
      /* e09  e10 e09'  */
9034
      else
9035
        break;
9036
 
9037
      intel_match_token (cur_token.code);
9038
    }
9039
 
9040
  for (;;)
9041
    {
9042
      if (!intel_e10 ())
9043
        return 0;
9044
 
9045
      /* e09'  PTR e10 e09' */
9046
      if (cur_token.code == T_PTR)
9047
        {
9048
          char suffix;
9049
 
9050
          if (prev_token.code == T_BYTE)
9051
            {
9052
              suffix = BYTE_MNEM_SUFFIX;
9053
              i.types[this_operand].bitfield.byte = 1;
9054
            }
9055
 
9056
          else if (prev_token.code == T_WORD)
9057
            {
9058
              if ((current_templates->start->name[0] == 'l'
9059
                   && current_templates->start->name[2] == 's'
9060
                   && current_templates->start->name[3] == 0)
9061
                  || current_templates->start->base_opcode == 0x62 /* bound */)
9062
                suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9063
              else if (intel_parser.got_a_float == 2)   /* "fi..." */
9064
                suffix = SHORT_MNEM_SUFFIX;
9065
              else
9066
                suffix = WORD_MNEM_SUFFIX;
9067
              i.types[this_operand].bitfield.word = 1;
9068
            }
9069
 
9070
          else if (prev_token.code == T_DWORD)
9071
            {
9072
              if ((current_templates->start->name[0] == 'l'
9073
                   && current_templates->start->name[2] == 's'
9074
                   && current_templates->start->name[3] == 0)
9075
                  || current_templates->start->base_opcode == 0x62 /* bound */)
9076
                suffix = WORD_MNEM_SUFFIX;
9077
              else if (flag_code == CODE_16BIT
9078
                       && (current_templates->start->opcode_modifier.jump
9079
                           || current_templates->start->opcode_modifier.jumpdword))
9080
                suffix = LONG_DOUBLE_MNEM_SUFFIX;
9081
              else if (intel_parser.got_a_float == 1)   /* "f..." */
9082
                suffix = SHORT_MNEM_SUFFIX;
9083
              else
9084
                suffix = LONG_MNEM_SUFFIX;
9085
              i.types[this_operand].bitfield.dword = 1;
9086
            }
9087
 
9088
          else if (prev_token.code == T_FWORD)
9089
            {
9090
              if (current_templates->start->name[0] == 'l'
9091
                  && current_templates->start->name[2] == 's'
9092
                  && current_templates->start->name[3] == 0)
9093
                suffix = LONG_MNEM_SUFFIX;
9094
              else if (!intel_parser.got_a_float)
9095
                {
9096
                  if (flag_code == CODE_16BIT)
9097
                    add_prefix (DATA_PREFIX_OPCODE);
9098
                  suffix = LONG_DOUBLE_MNEM_SUFFIX;
9099
                }
9100
              else
9101
                suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9102
              i.types[this_operand].bitfield.fword = 1;
9103
            }
9104
 
9105
          else if (prev_token.code == T_QWORD)
9106
            {
9107
              if (current_templates->start->base_opcode == 0x62 /* bound */
9108
                  || intel_parser.got_a_float == 1)     /* "f..." */
9109
                suffix = LONG_MNEM_SUFFIX;
9110
              else
9111
                suffix = QWORD_MNEM_SUFFIX;
9112
              i.types[this_operand].bitfield.qword = 1;
9113
            }
9114
 
9115
          else if (prev_token.code == T_TBYTE)
9116
            {
9117
              if (intel_parser.got_a_float == 1)
9118
                suffix = LONG_DOUBLE_MNEM_SUFFIX;
9119
              else
9120
                suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9121
            }
9122
 
9123
          else if (prev_token.code == T_XMMWORD)
9124
            {
9125
              suffix = XMMWORD_MNEM_SUFFIX;
9126
              i.types[this_operand].bitfield.xmmword = 1;
9127
            }
9128
 
9129
          else if (prev_token.code == T_YMMWORD)
9130
            {
9131
              suffix = YMMWORD_MNEM_SUFFIX;
9132
              i.types[this_operand].bitfield.ymmword = 1;
9133
            }
9134
 
9135
          else
9136
            {
9137
              as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
9138
              return 0;
9139
            }
9140
 
9141
          i.types[this_operand].bitfield.unspecified = 0;
9142
 
9143
          /* Operands for jump/call using 'ptr' notation denote absolute
9144
             addresses.  */
9145
          if (current_templates->start->opcode_modifier.jump
9146
              || current_templates->start->opcode_modifier.jumpdword)
9147
            i.types[this_operand].bitfield.jumpabsolute = 1;
9148
 
9149
          if (current_templates->start->base_opcode == 0x8d /* lea */)
9150
            ;
9151
          else if (!i.suffix)
9152
            i.suffix = suffix;
9153
          else if (i.suffix != suffix)
9154
            {
9155
              as_bad (_("Conflicting operand modifiers"));
9156
              return 0;
9157
            }
9158
 
9159
        }
9160
 
9161
      /* e09'  : e10 e09'  */
9162
      else if (cur_token.code == ':')
9163
        {
9164
          if (prev_token.code != T_REG)
9165
            {
9166
              /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9167
                 segment/group identifier (which we don't have), using comma
9168
                 as the operand separator there is even less consistent, since
9169
                 there all branches only have a single operand.  */
9170
              if (this_operand != 0
9171
                  || intel_parser.in_offset
9172
                  || intel_parser.in_bracket
9173
                  || (!current_templates->start->opcode_modifier.jump
9174
                      && !current_templates->start->opcode_modifier.jumpdword
9175
                      && !current_templates->start->opcode_modifier.jumpintersegment
9176
                      && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
9177
                return intel_match_token (T_NIL);
9178
              /* Remember the start of the 2nd operand and terminate 1st
9179
                 operand here.
9180
                 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9181
                 another expression), but it gets at least the simplest case
9182
                 (a plain number or symbol on the left side) right.  */
9183
              intel_parser.next_operand = intel_parser.op_string;
9184
              *--intel_parser.op_string = '\0';
9185
              return intel_match_token (':');
9186
            }
9187
        }
9188
 
9189
      /* e09'  Empty  */
9190
      else
9191
        break;
9192
 
9193
      intel_match_token (cur_token.code);
9194
 
9195
    }
9196
 
9197
  if (in_offset)
9198
    {
9199
      --intel_parser.in_offset;
9200
      if (nregs < 0)
9201
        nregs = ~nregs;
9202
      if (NUM_ADDRESS_REGS > nregs)
9203
        {
9204
          as_bad (_("Invalid operand to `OFFSET'"));
9205
          return 0;
9206
        }
9207
      intel_parser.op_modifier |= 1 << T_OFFSET;
9208
    }
9209
 
9210
  if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9211
    i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
9212
  return 1;
9213
}
9214
 
9215
static int
9216
intel_bracket_expr (void)
9217
{
9218
  int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
9219
  const char *start = intel_parser.op_string;
9220
  int len;
9221
 
9222
  if (i.op[this_operand].regs)
9223
    return intel_match_token (T_NIL);
9224
 
9225
  intel_match_token ('[');
9226
 
9227
  /* Mark as a memory operand only if it's not already known to be an
9228
     offset expression.  If it's an offset expression, we need to keep
9229
     the brace in.  */
9230
  if (!intel_parser.in_offset)
9231
    {
9232
      ++intel_parser.in_bracket;
9233
 
9234
      /* Operands for jump/call inside brackets denote absolute addresses.  */
9235
      if (current_templates->start->opcode_modifier.jump
9236
          || current_templates->start->opcode_modifier.jumpdword)
9237
        i.types[this_operand].bitfield.jumpabsolute = 1;
9238
 
9239
      /* Unfortunately gas always diverged from MASM in a respect that can't
9240
         be easily fixed without risking to break code sequences likely to be
9241
         encountered (the testsuite even check for this): MASM doesn't consider
9242
         an expression inside brackets unconditionally as a memory reference.
9243
         When that is e.g. a constant, an offset expression, or the sum of the
9244
         two, this is still taken as a constant load. gas, however, always
9245
         treated these as memory references. As a compromise, we'll try to make
9246
         offset expressions inside brackets work the MASM way (since that's
9247
         less likely to be found in real world code), but make constants alone
9248
         continue to work the traditional gas way. In either case, issue a
9249
         warning.  */
9250
      intel_parser.op_modifier &= ~was_offset;
9251
    }
9252
  else
9253
    strcat (intel_parser.disp, "[");
9254
 
9255
  /* Add a '+' to the displacement string if necessary.  */
9256
  if (*intel_parser.disp != '\0'
9257
      && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
9258
    strcat (intel_parser.disp, "+");
9259
 
9260
  if (intel_expr ()
9261
      && (len = intel_parser.op_string - start - 1,
9262
          intel_match_token (']')))
9263
    {
9264
      /* Preserve brackets when the operand is an offset expression.  */
9265
      if (intel_parser.in_offset)
9266
        strcat (intel_parser.disp, "]");
9267
      else
9268
        {
9269
          --intel_parser.in_bracket;
9270
          if (i.base_reg || i.index_reg)
9271
            intel_parser.is_mem = 1;
9272
          if (!intel_parser.is_mem)
9273
            {
9274
              if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
9275
                /* Defer the warning until all of the operand was parsed.  */
9276
                intel_parser.is_mem = -1;
9277
              else if (!quiet_warnings)
9278
                as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9279
                         len, start, len, start);
9280
            }
9281
        }
9282
      intel_parser.op_modifier |= was_offset;
9283
 
9284
      return 1;
9285
    }
9286
  return 0;
9287
}
9288
 
9289
/* e10  e11 e10'
9290
 
9291
   e10' [ expr ] e10'
9292
        | Empty  */
9293
static int
9294
intel_e10 (void)
9295
{
9296
  if (!intel_e11 ())
9297
    return 0;
9298
 
9299
  while (cur_token.code == '[')
9300
    {
9301
      if (!intel_bracket_expr ())
9302
        return 0;
9303
    }
9304
 
9305
  return 1;
9306
}
9307
 
9308
/* e11  ( expr )
9309
        | [ expr ]
9310
        | BYTE
9311
        | WORD
9312
        | DWORD
9313
        | FWORD
9314
        | QWORD
9315
        | TBYTE
9316
        | OWORD
9317
        | XMMWORD
9318
        | YMMWORD
9319
        | $
9320
        | .
9321
        | register
9322
        | id
9323
        | constant  */
9324
static int
9325
intel_e11 (void)
9326
{
9327
  switch (cur_token.code)
9328
    {
9329
    /* e11  ( expr ) */
9330
    case '(':
9331
      intel_match_token ('(');
9332
      strcat (intel_parser.disp, "(");
9333
 
9334
      if (intel_expr () && intel_match_token (')'))
9335
        {
9336
          strcat (intel_parser.disp, ")");
9337
          return 1;
9338
        }
9339
      return 0;
9340
 
9341
    /* e11  [ expr ] */
9342
    case '[':
9343
      return intel_bracket_expr ();
9344
 
9345
    /* e11  $
9346
            | .  */
9347
    case '.':
9348
      strcat (intel_parser.disp, cur_token.str);
9349
      intel_match_token (cur_token.code);
9350
 
9351
      /* Mark as a memory operand only if it's not already known to be an
9352
         offset expression.  */
9353
      if (!intel_parser.in_offset)
9354
        intel_parser.is_mem = 1;
9355
 
9356
      return 1;
9357
 
9358
    /* e11  register  */
9359
    case T_REG:
9360
      {
9361
        const reg_entry *reg = intel_parser.reg = cur_token.reg;
9362
 
9363
        intel_match_token (T_REG);
9364
 
9365
        /* Check for segment change.  */
9366
        if (cur_token.code == ':')
9367
          {
9368
            if (!reg->reg_type.bitfield.sreg2
9369
                && !reg->reg_type.bitfield.sreg3)
9370
              {
9371
                as_bad (_("`%s' is not a valid segment register"),
9372
                        reg->reg_name);
9373
                return 0;
9374
              }
9375
            else if (i.mem_operands >= 2)
9376
              as_warn (_("Segment override ignored"));
9377
            else if (i.seg[i.mem_operands])
9378
              as_warn (_("Extra segment override ignored"));
9379
            else
9380
              {
9381
                if (!intel_parser.in_offset)
9382
                  intel_parser.is_mem = 1;
9383
                switch (reg->reg_num)
9384
                  {
9385
                  case 0:
9386
                    i.seg[i.mem_operands] = &es;
9387
                    break;
9388
                  case 1:
9389
                    i.seg[i.mem_operands] = &cs;
9390
                    break;
9391
                  case 2:
9392
                    i.seg[i.mem_operands] = &ss;
9393
                    break;
9394
                  case 3:
9395
                    i.seg[i.mem_operands] = &ds;
9396
                    break;
9397
                  case 4:
9398
                    i.seg[i.mem_operands] = &fs;
9399
                    break;
9400
                  case 5:
9401
                    i.seg[i.mem_operands] = &gs;
9402
                    break;
9403
                  }
9404
              }
9405
          }
9406
 
9407
        else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
9408
          {
9409
            as_bad (_("cannot use `FLAT' here"));
9410
            return 0;
9411
          }
9412
 
9413
        /* Not a segment register. Check for register scaling.  */
9414
        else if (cur_token.code == '*')
9415
          {
9416
            if (!intel_parser.in_bracket)
9417
              {
9418
                as_bad (_("Register scaling only allowed in memory operands"));
9419
                return 0;
9420
              }
9421
 
9422
            if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
9423
              reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
9424
            else if (i.index_reg)
9425
              reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
9426
 
9427
            /* What follows must be a valid scale.  */
9428
            intel_match_token ('*');
9429
            i.index_reg = reg;
9430
            i.types[this_operand].bitfield.baseindex = 1;
9431
 
9432
            /* Set the scale after setting the register (otherwise,
9433
               i386_scale will complain)  */
9434
            if (cur_token.code == '+' || cur_token.code == '-')
9435
              {
9436
                char *str, sign = cur_token.code;
9437
                intel_match_token (cur_token.code);
9438
                if (cur_token.code != T_CONST)
9439
                  {
9440
                    as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9441
                            cur_token.str);
9442
                    return 0;
9443
                  }
9444
                str = (char *) xmalloc (strlen (cur_token.str) + 2);
9445
                strcpy (str + 1, cur_token.str);
9446
                *str = sign;
9447
                if (!i386_scale (str))
9448
                  return 0;
9449
                free (str);
9450
              }
9451
            else if (!i386_scale (cur_token.str))
9452
              return 0;
9453
            intel_match_token (cur_token.code);
9454
          }
9455
 
9456
        /* No scaling. If this is a memory operand, the register is either a
9457
           base register (first occurrence) or an index register (second
9458
           occurrence).  */
9459
        else if (intel_parser.in_bracket)
9460
          {
9461
 
9462
            if (!i.base_reg)
9463
              i.base_reg = reg;
9464
            else if (!i.index_reg)
9465
              i.index_reg = reg;
9466
            else
9467
              {
9468
                as_bad (_("Too many register references in memory operand"));
9469
                return 0;
9470
              }
9471
 
9472
            i.types[this_operand].bitfield.baseindex = 1;
9473
          }
9474
 
9475
        /* It's neither base nor index.  */
9476
        else if (!intel_parser.in_offset && !intel_parser.is_mem)
9477
          {
9478
            i386_operand_type temp = reg->reg_type;
9479
            temp.bitfield.baseindex = 0;
9480
            i.types[this_operand] = operand_type_or (i.types[this_operand],
9481
                                                     temp);
9482
            i.types[this_operand].bitfield.unspecified = 0;
9483
            i.op[this_operand].regs = reg;
9484
            i.reg_operands++;
9485
          }
9486
        else
9487
          {
9488
            as_bad (_("Invalid use of register"));
9489
            return 0;
9490
          }
9491
 
9492
        /* Since registers are not part of the displacement string (except
9493
           when we're parsing offset operands), we may need to remove any
9494
           preceding '+' from the displacement string.  */
9495
        if (*intel_parser.disp != '\0'
9496
            && !intel_parser.in_offset)
9497
          {
9498
            char *s = intel_parser.disp;
9499
            s += strlen (s) - 1;
9500
            if (*s == '+')
9501
              *s = '\0';
9502
          }
9503
 
9504
        return 1;
9505
      }
9506
 
9507
    /* e11  BYTE
9508
            | WORD
9509
            | DWORD
9510
            | FWORD
9511
            | QWORD
9512
            | TBYTE
9513
            | OWORD
9514
            | XMMWORD
9515
            | YMMWORD  */
9516
    case T_BYTE:
9517
    case T_WORD:
9518
    case T_DWORD:
9519
    case T_FWORD:
9520
    case T_QWORD:
9521
    case T_TBYTE:
9522
    case T_XMMWORD:
9523
    case T_YMMWORD:
9524
      intel_match_token (cur_token.code);
9525
 
9526
      if (cur_token.code == T_PTR)
9527
        return 1;
9528
 
9529
      /* It must have been an identifier.  */
9530
      intel_putback_token ();
9531
      cur_token.code = T_ID;
9532
      /* FALLTHRU */
9533
 
9534
    /* e11  id
9535
            | constant  */
9536
    case T_ID:
9537
      if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9538
        {
9539
          symbolS *symbolP;
9540
 
9541
          /* The identifier represents a memory reference only if it's not
9542
             preceded by an offset modifier and if it's not an equate.  */
9543
          symbolP = symbol_find(cur_token.str);
9544
          if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
9545
            intel_parser.is_mem = 1;
9546
        }
9547
        /* FALLTHRU */
9548
 
9549
    case T_CONST:
9550
    case '-':
9551
    case '+':
9552
      {
9553
        char *save_str, sign = 0;
9554
 
9555
        /* Allow constants that start with `+' or `-'.  */
9556
        if (cur_token.code == '-' || cur_token.code == '+')
9557
          {
9558
            sign = cur_token.code;
9559
            intel_match_token (cur_token.code);
9560
            if (cur_token.code != T_CONST)
9561
              {
9562
                as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9563
                        cur_token.str);
9564
                return 0;
9565
              }
9566
          }
9567
 
9568
        save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
9569
        strcpy (save_str + !!sign, cur_token.str);
9570
        if (sign)
9571
          *save_str = sign;
9572
 
9573
        /* Get the next token to check for register scaling.  */
9574
        intel_match_token (cur_token.code);
9575
 
9576
        /* Check if this constant is a scaling factor for an
9577
           index register.  */
9578
        if (cur_token.code == '*')
9579
          {
9580
            if (intel_match_token ('*') && cur_token.code == T_REG)
9581
              {
9582
                const reg_entry *reg = cur_token.reg;
9583
 
9584
                if (!intel_parser.in_bracket)
9585
                  {
9586
                    as_bad (_("Register scaling only allowed "
9587
                              "in memory operands"));
9588
                    return 0;
9589
                  }
9590
 
9591
                 /* Disallow things like [1*si].
9592
                    sp and esp are invalid as index.  */
9593
                if (reg->reg_type.bitfield.reg16)
9594
                  reg = i386_regtab + REGNAM_AX + 4;
9595
                else if (i.index_reg)
9596
                  reg = i386_regtab + REGNAM_EAX + 4;
9597
 
9598
                /* The constant is followed by `* reg', so it must be
9599
                   a valid scale.  */
9600
                i.index_reg = reg;
9601
                i.types[this_operand].bitfield.baseindex = 1;
9602
 
9603
                /* Set the scale after setting the register (otherwise,
9604
                   i386_scale will complain)  */
9605
                if (!i386_scale (save_str))
9606
                  return 0;
9607
                intel_match_token (T_REG);
9608
 
9609
                /* Since registers are not part of the displacement
9610
                   string, we may need to remove any preceding '+' from
9611
                   the displacement string.  */
9612
                if (*intel_parser.disp != '\0')
9613
                  {
9614
                    char *s = intel_parser.disp;
9615
                    s += strlen (s) - 1;
9616
                    if (*s == '+')
9617
                      *s = '\0';
9618
                  }
9619
 
9620
                free (save_str);
9621
 
9622
                return 1;
9623
              }
9624
 
9625
            /* The constant was not used for register scaling. Since we have
9626
               already consumed the token following `*' we now need to put it
9627
               back in the stream.  */
9628
            intel_putback_token ();
9629
          }
9630
 
9631
        /* Add the constant to the displacement string.  */
9632
        strcat (intel_parser.disp, save_str);
9633
        free (save_str);
9634
 
9635
        return 1;
9636
      }
9637
    }
9638
 
9639
  as_bad (_("Unrecognized token '%s'"), cur_token.str);
9640
  return 0;
9641
}
9642
 
9643
/* Match the given token against cur_token. If they match, read the next
9644
   token from the operand string.  */
9645
static int
9646
intel_match_token (int code)
9647
{
9648
  if (cur_token.code == code)
9649
    {
9650
      intel_get_token ();
9651
      return 1;
9652
    }
9653
  else
9654
    {
9655
      as_bad (_("Unexpected token `%s'"), cur_token.str);
9656
      return 0;
9657
    }
9658
}
9659
 
9660
/* Read a new token from intel_parser.op_string and store it in cur_token.  */
9661
static void
9662
intel_get_token (void)
9663
{
9664
  char *end_op;
9665
  const reg_entry *reg;
9666
  struct intel_token new_token;
9667
 
9668
  new_token.code = T_NIL;
9669
  new_token.reg = NULL;
9670
  new_token.str = NULL;
9671
 
9672
  /* Free the memory allocated to the previous token and move
9673
     cur_token to prev_token.  */
9674
  if (prev_token.str)
9675
    free (prev_token.str);
9676
 
9677
  prev_token = cur_token;
9678
 
9679
  /* Skip whitespace.  */
9680
  while (is_space_char (*intel_parser.op_string))
9681
    intel_parser.op_string++;
9682
 
9683
  /* Return an empty token if we find nothing else on the line.  */
9684
  if (*intel_parser.op_string == '\0')
9685
    {
9686
      cur_token = new_token;
9687
      return;
9688
    }
9689
 
9690
  /* The new token cannot be larger than the remainder of the operand
9691
     string.  */
9692
  new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
9693
  new_token.str[0] = '\0';
9694
 
9695
  if (strchr ("0123456789", *intel_parser.op_string))
9696
    {
9697
      char *p = new_token.str;
9698
      char *q = intel_parser.op_string;
9699
      new_token.code = T_CONST;
9700
 
9701
      /* Allow any kind of identifier char to encompass floating point and
9702
         hexadecimal numbers.  */
9703
      while (is_identifier_char (*q))
9704
        *p++ = *q++;
9705
      *p = '\0';
9706
 
9707
      /* Recognize special symbol names [0-9][bf].  */
9708
      if (strlen (intel_parser.op_string) == 2
9709
          && (intel_parser.op_string[1] == 'b'
9710
              || intel_parser.op_string[1] == 'f'))
9711
        new_token.code = T_ID;
9712
    }
9713
 
9714
  else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
9715
    {
9716
      size_t len = end_op - intel_parser.op_string;
9717
 
9718
      new_token.code = T_REG;
9719
      new_token.reg = reg;
9720
 
9721
      memcpy (new_token.str, intel_parser.op_string, len);
9722
      new_token.str[len] = '\0';
9723
    }
9724
 
9725
  else if (is_identifier_char (*intel_parser.op_string))
9726
    {
9727
      char *p = new_token.str;
9728
      char *q = intel_parser.op_string;
9729
 
9730
      /* A '.' or '$' followed by an identifier char is an identifier.
9731
         Otherwise, it's operator '.' followed by an expression.  */
9732
      if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9733
        {
9734
          new_token.code = '.';
9735
          new_token.str[0] = '.';
9736
          new_token.str[1] = '\0';
9737
        }
9738
      else
9739
        {
9740
          while (is_identifier_char (*q) || *q == '@')
9741
            *p++ = *q++;
9742
          *p = '\0';
9743
 
9744
          if (strcasecmp (new_token.str, "NOT") == 0)
9745
            new_token.code = '~';
9746
 
9747
          else if (strcasecmp (new_token.str, "MOD") == 0)
9748
            new_token.code = '%';
9749
 
9750
          else if (strcasecmp (new_token.str, "AND") == 0)
9751
            new_token.code = '&';
9752
 
9753
          else if (strcasecmp (new_token.str, "OR") == 0)
9754
            new_token.code = '|';
9755
 
9756
          else if (strcasecmp (new_token.str, "XOR") == 0)
9757
            new_token.code = '^';
9758
 
9759
          else if (strcasecmp (new_token.str, "SHL") == 0)
9760
            new_token.code = T_SHL;
9761
 
9762
          else if (strcasecmp (new_token.str, "SHR") == 0)
9763
            new_token.code = T_SHR;
9764
 
9765
          else if (strcasecmp (new_token.str, "BYTE") == 0)
9766
            new_token.code = T_BYTE;
9767
 
9768
          else if (strcasecmp (new_token.str, "WORD") == 0)
9769
            new_token.code = T_WORD;
9770
 
9771
          else if (strcasecmp (new_token.str, "DWORD") == 0)
9772
            new_token.code = T_DWORD;
9773
 
9774
          else if (strcasecmp (new_token.str, "FWORD") == 0)
9775
            new_token.code = T_FWORD;
9776
 
9777
          else if (strcasecmp (new_token.str, "QWORD") == 0)
9778
            new_token.code = T_QWORD;
9779
 
9780
          else if (strcasecmp (new_token.str, "TBYTE") == 0
9781
                   /* XXX remove (gcc still uses it) */
9782
                   || strcasecmp (new_token.str, "XWORD") == 0)
9783
            new_token.code = T_TBYTE;
9784
 
9785
          else if (strcasecmp (new_token.str, "XMMWORD") == 0
9786
                   || strcasecmp (new_token.str, "OWORD") == 0)
9787
            new_token.code = T_XMMWORD;
9788
 
9789
          else if (strcasecmp (new_token.str, "YMMWORD") == 0)
9790
            new_token.code = T_YMMWORD;
9791
 
9792
          else if (strcasecmp (new_token.str, "PTR") == 0)
9793
            new_token.code = T_PTR;
9794
 
9795
          else if (strcasecmp (new_token.str, "SHORT") == 0)
9796
            new_token.code = T_SHORT;
9797
 
9798
          else if (strcasecmp (new_token.str, "OFFSET") == 0)
9799
            {
9800
              new_token.code = T_OFFSET;
9801
 
9802
              /* ??? This is not mentioned in the MASM grammar but gcc
9803
                     makes use of it with -mintel-syntax.  OFFSET may be
9804
                     followed by FLAT:  */
9805
              if (strncasecmp (q, " FLAT:", 6) == 0)
9806
                strcat (new_token.str, " FLAT:");
9807
            }
9808
 
9809
          else
9810
            new_token.code = T_ID;
9811
        }
9812
    }
9813
 
9814
  else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9815
    {
9816
      new_token.code = *intel_parser.op_string;
9817
      new_token.str[0] = *intel_parser.op_string;
9818
      new_token.str[1] = '\0';
9819
    }
9820
 
9821
  else if (strchr ("<>", *intel_parser.op_string)
9822
           && *intel_parser.op_string == *(intel_parser.op_string + 1))
9823
    {
9824
      new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9825
      new_token.str[0] = *intel_parser.op_string;
9826
      new_token.str[1] = *intel_parser.op_string;
9827
      new_token.str[2] = '\0';
9828
    }
9829
 
9830
  else
9831
    as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
9832
 
9833
  intel_parser.op_string += strlen (new_token.str);
9834
  cur_token = new_token;
9835
}
9836
 
9837
/* Put cur_token back into the token stream and make cur_token point to
9838
   prev_token.  */
9839
static void
9840
intel_putback_token (void)
9841
{
9842
  if (cur_token.code != T_NIL)
9843
    {
9844
      intel_parser.op_string -= strlen (cur_token.str);
9845
      free (cur_token.str);
9846
    }
9847
  cur_token = prev_token;
9848
 
9849
  /* Forget prev_token.  */
9850
  prev_token.code = T_NIL;
9851
  prev_token.reg = NULL;
9852
  prev_token.str = NULL;
9853
}
9854
 
9855
void
9856
tc_x86_parse_to_dw2regnum (expressionS *exp)
9857
{
9858
  int saved_naked_reg;
9859
  char saved_register_dot;
9860
 
9861
  saved_naked_reg = allow_naked_reg;
9862
  allow_naked_reg = 1;
9863
  saved_register_dot = register_chars['.'];
9864
  register_chars['.'] = '.';
9865
  allow_pseudo_reg = 1;
9866
  expression_and_evaluate (exp);
9867
  allow_pseudo_reg = 0;
9868
  register_chars['.'] = saved_register_dot;
9869
  allow_naked_reg = saved_naked_reg;
9870
 
9871
  if (exp->X_op == O_register && exp->X_add_number >= 0)
9872
    {
9873
      if ((addressT) exp->X_add_number < i386_regtab_size)
9874
        {
9875
          exp->X_op = O_constant;
9876
          exp->X_add_number = i386_regtab[exp->X_add_number]
9877
                              .dw2_regnum[flag_code >> 1];
9878
        }
9879
      else
9880
        exp->X_op = O_illegal;
9881
    }
9882
}
9883
 
9884
void
9885
tc_x86_frame_initial_instructions (void)
9886
{
9887
  static unsigned int sp_regno[2];
9888
 
9889
  if (!sp_regno[flag_code >> 1])
9890
    {
9891
      char *saved_input = input_line_pointer;
9892
      char sp[][4] = {"esp", "rsp"};
9893
      expressionS exp;
9894
 
9895
      input_line_pointer = sp[flag_code >> 1];
9896
      tc_x86_parse_to_dw2regnum (&exp);
9897
      assert (exp.X_op == O_constant);
9898
      sp_regno[flag_code >> 1] = exp.X_add_number;
9899
      input_line_pointer = saved_input;
9900
    }
9901
 
9902
  cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9903
  cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
9904
}
9905
 
9906
int
9907
i386_elf_section_type (const char *str, size_t len)
9908
{
9909
  if (flag_code == CODE_64BIT
9910
      && len == sizeof ("unwind") - 1
9911
      && strncmp (str, "unwind", 6) == 0)
9912
    return SHT_X86_64_UNWIND;
9913
 
9914
  return -1;
9915
}
9916
 
9917
#ifdef TE_PE
9918
void
9919
tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9920
{
9921
  expressionS expr;
9922
 
9923
  expr.X_op = O_secrel;
9924
  expr.X_add_symbol = symbol;
9925
  expr.X_add_number = 0;
9926
  emit_expr (&expr, size);
9927
}
9928
#endif
9929
 
9930
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9931
/* For ELF on x86-64, add support for SHF_X86_64_LARGE.  */
9932
 
9933
int
9934
x86_64_section_letter (int letter, char **ptr_msg)
9935
{
9936
  if (flag_code == CODE_64BIT)
9937
    {
9938
      if (letter == 'l')
9939
        return SHF_X86_64_LARGE;
9940
 
9941
      *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9942
    }
9943
  else
9944
    *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
9945
  return -1;
9946
}
9947
 
9948
int
9949
x86_64_section_word (char *str, size_t len)
9950
{
9951
  if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
9952
    return SHF_X86_64_LARGE;
9953
 
9954
  return -1;
9955
}
9956
 
9957
static void
9958
handle_large_common (int small ATTRIBUTE_UNUSED)
9959
{
9960
  if (flag_code != CODE_64BIT)
9961
    {
9962
      s_comm_internal (0, elf_common_parse);
9963
      as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9964
    }
9965
  else
9966
    {
9967
      static segT lbss_section;
9968
      asection *saved_com_section_ptr = elf_com_section_ptr;
9969
      asection *saved_bss_section = bss_section;
9970
 
9971
      if (lbss_section == NULL)
9972
        {
9973
          flagword applicable;
9974
          segT seg = now_seg;
9975
          subsegT subseg = now_subseg;
9976
 
9977
          /* The .lbss section is for local .largecomm symbols.  */
9978
          lbss_section = subseg_new (".lbss", 0);
9979
          applicable = bfd_applicable_section_flags (stdoutput);
9980
          bfd_set_section_flags (stdoutput, lbss_section,
9981
                                 applicable & SEC_ALLOC);
9982
          seg_info (lbss_section)->bss = 1;
9983
 
9984
          subseg_set (seg, subseg);
9985
        }
9986
 
9987
      elf_com_section_ptr = &_bfd_elf_large_com_section;
9988
      bss_section = lbss_section;
9989
 
9990
      s_comm_internal (0, elf_common_parse);
9991
 
9992
      elf_com_section_ptr = saved_com_section_ptr;
9993
      bss_section = saved_bss_section;
9994
    }
9995
}
9996
#endif /* OBJ_ELF || OBJ_MAYBE_ELF */

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