OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [config/] [tc-i960.c] - Blame information for rev 825

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
/* tc-i960.c - All the i80960-specific stuff
2
   Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3
   1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007
4
   Free Software Foundation, Inc.
5
 
6
   This file is part of GAS.
7
 
8
   GAS is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3, or (at your option)
11
   any later version.
12
 
13
   GAS is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with GAS; see the file COPYING.  If not, write to the Free
20
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21
   02110-1301, USA.  */
22
 
23
/* See comment on md_parse_option for 80960-specific invocation options.  */
24
 
25
/* There are 4 different lengths of (potentially) symbol-based displacements
26
   in the 80960 instruction set, each of which could require address fix-ups
27
   and (in the case of external symbols) emission of relocation directives:
28
 
29
   32-bit (MEMB)
30
        This is a standard length for the base assembler and requires no
31
        special action.
32
 
33
   13-bit (COBR)
34
        This is a non-standard length, but the base assembler has a
35
        hook for bit field address fixups: the fixS structure can
36
        point to a descriptor of the field, in which case our
37
        md_number_to_field() routine gets called to process it.
38
 
39
        I made the hook a little cleaner by having fix_new() (in the base
40
        assembler) return a pointer to the fixS in question.  And I made it a
41
        little simpler by storing the field size (in this case 13) instead of
42
        of a pointer to another structure:  80960 displacements are ALWAYS
43
        stored in the low-order bits of a 4-byte word.
44
 
45
        Since the target of a COBR cannot be external, no relocation
46
        directives for this size displacement have to be generated.
47
        But the base assembler had to be modified to issue error
48
        messages if the symbol did turn out to be external.
49
 
50
   24-bit (CTRL)
51
        Fixups are handled as for the 13-bit case (except that 24 is stored
52
        in the fixS).
53
 
54
        The relocation directive generated is the same as that for the 32-bit
55
        displacement, except that it's PC-relative (the 32-bit displacement
56
        never is).   The i80960 version of the linker needs a mod to
57
        distinguish and handle the 24-bit case.
58
 
59
   12-bit (MEMA)
60
        MEMA formats are always promoted to MEMB (32-bit) if the displacement
61
        is based on a symbol, because it could be relocated at link time.
62
        The only time we use the 12-bit format is if an absolute value of
63
        less than 4096 is specified, in which case we need neither a fixup nor
64
        a relocation directive.  */
65
 
66
#include "as.h"
67
 
68
#include "safe-ctype.h"
69
#include "obstack.h"
70
 
71
#include "opcode/i960.h"
72
 
73
#if defined (OBJ_AOUT) || defined (OBJ_BOUT)
74
 
75
#define TC_S_IS_SYSPROC(s)      ((1 <= S_GET_OTHER (s)) && (S_GET_OTHER (s) <= 32))
76
#define TC_S_IS_BALNAME(s)      (S_GET_OTHER (s) == N_BALNAME)
77
#define TC_S_IS_CALLNAME(s)     (S_GET_OTHER (s) == N_CALLNAME)
78
#define TC_S_IS_BADPROC(s)      ((S_GET_OTHER (s) != 0) && !TC_S_IS_CALLNAME (s) && !TC_S_IS_BALNAME (s) && !TC_S_IS_SYSPROC (s))
79
 
80
#define TC_S_SET_SYSPROC(s, p)  (S_SET_OTHER ((s), (p) + 1))
81
#define TC_S_GET_SYSPROC(s)     (S_GET_OTHER (s) - 1)
82
 
83
#define TC_S_FORCE_TO_BALNAME(s)        (S_SET_OTHER ((s), N_BALNAME))
84
#define TC_S_FORCE_TO_CALLNAME(s)       (S_SET_OTHER ((s), N_CALLNAME))
85
#define TC_S_FORCE_TO_SYSPROC(s)        {;}
86
 
87
#else /* ! OBJ_A/BOUT */
88
#ifdef OBJ_COFF
89
 
90
#define TC_S_IS_SYSPROC(s)      (S_GET_STORAGE_CLASS (s) == C_SCALL)
91
#define TC_S_IS_BALNAME(s)      (SF_GET_BALNAME (s))
92
#define TC_S_IS_CALLNAME(s)     (SF_GET_CALLNAME (s))
93
#define TC_S_IS_BADPROC(s)      (TC_S_IS_SYSPROC (s) && TC_S_GET_SYSPROC (s) < 0 && 31 < TC_S_GET_SYSPROC (s))
94
 
95
#define TC_S_SET_SYSPROC(s, p)  ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
96
#define TC_S_GET_SYSPROC(s)     ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
97
 
98
#define TC_S_FORCE_TO_BALNAME(s)        (SF_SET_BALNAME (s))
99
#define TC_S_FORCE_TO_CALLNAME(s)       (SF_SET_CALLNAME (s))
100
#define TC_S_FORCE_TO_SYSPROC(s)        (S_SET_STORAGE_CLASS ((s), C_SCALL))
101
 
102
#else /* ! OBJ_COFF */
103
#ifdef OBJ_ELF
104
#define TC_S_IS_SYSPROC(s)      0
105
 
106
#define TC_S_IS_BALNAME(s)      0
107
#define TC_S_IS_CALLNAME(s)     0
108
#define TC_S_IS_BADPROC(s)      0
109
 
110
#define TC_S_SET_SYSPROC(s, p)
111
#define TC_S_GET_SYSPROC(s)     0
112
 
113
#define TC_S_FORCE_TO_BALNAME(s)
114
#define TC_S_FORCE_TO_CALLNAME(s)
115
#define TC_S_FORCE_TO_SYSPROC(s)
116
#else
117
 #error COFF, a.out, b.out, and ELF are the only supported formats.
118
#endif /* ! OBJ_ELF */
119
#endif /* ! OBJ_COFF */
120
#endif /* ! OBJ_A/BOUT */
121
 
122
extern char *input_line_pointer;
123
 
124
/* Local i80960 routines.  */
125
struct memS;
126
struct regop;
127
 
128
/* See md_parse_option() for meanings of these options.  */
129
static char norelax;                    /* True if -norelax switch seen.  */
130
static char instrument_branches;        /* True if -b switch seen.  */
131
 
132
/* Characters that always start a comment.
133
   If the pre-processor is disabled, these aren't very useful.  */
134
const char comment_chars[] = "#";
135
 
136
/* Characters that only start a comment at the beginning of
137
   a line.  If the line seems to have the form '# 123 filename'
138
   .line and .file directives will appear in the pre-processed output.
139
 
140
   Note that input_file.c hand checks for '#' at the beginning of the
141
   first line of the input file.  This is because the compiler outputs
142
   #NO_APP at the beginning of its output.  */
143
 
144
/* Also note that comments started like this one will always work.  */
145
 
146
const char line_comment_chars[]   = "#";
147
const char line_separator_chars[] = ";";
148
 
149
/* Chars that can be used to separate mant from exp in floating point nums.  */
150
const char EXP_CHARS[] = "eE";
151
 
152
/* Chars that mean this number is a floating point constant,
153
   as in 0f12.456 or 0d1.2345e12.  */
154
const char FLT_CHARS[] = "fFdDtT";
155
 
156
/* Table used by base assembler to relax addresses based on varying length
157
   instructions.  The fields are:
158
     1) most positive reach of this state,
159
     2) most negative reach of this state,
160
     3) how many bytes this mode will add to the size of the current frag
161
     4) which index into the table to try if we can't fit into this one.
162
 
163
   For i80960, the only application is the (de-)optimization of cobr
164
   instructions into separate compare and branch instructions when a 13-bit
165
   displacement won't hack it.  */
166
const relax_typeS md_relax_table[] =
167
{
168
  {0, 0, 0, 0},                             /* State 0 => no more relaxation possible.  */
169
  {4088, -4096, 0, 2},                   /* State 1: conditional branch (cobr).  */
170
  {0x800000 - 8, -0x800000, 4, 0},       /* State 2: compare (reg) & branch (ctrl).  */
171
};
172
 
173
/* These are the machine dependent pseudo-ops.
174
 
175
   This table describes all the machine specific pseudo-ops the assembler
176
   has to support.  The fields are:
177
        pseudo-op name without dot
178
        function to call to execute this pseudo-op
179
        integer arg to pass to the function.  */
180
#define S_LEAFPROC      1
181
#define S_SYSPROC       2
182
 
183
/* Macros to extract info from an 'expressionS' structure 'e'.  */
184
#define adds(e) e.X_add_symbol
185
#define offs(e) e.X_add_number
186
 
187
/* Branch-prediction bits for CTRL/COBR format opcodes.  */
188
#define BP_MASK         0x00000002      /* Mask for branch-prediction bit.  */
189
#define BP_TAKEN        0x00000000      /* Value to OR in to predict branch.  */
190
#define BP_NOT_TAKEN    0x00000002      /* Value to OR in to predict no branch.  */
191
 
192
/* Some instruction opcodes that we need explicitly.  */
193
#define BE      0x12000000
194
#define BG      0x11000000
195
#define BGE     0x13000000
196
#define BL      0x14000000
197
#define BLE     0x16000000
198
#define BNE     0x15000000
199
#define BNO     0x10000000
200
#define BO      0x17000000
201
#define CHKBIT  0x5a002700
202
#define CMPI    0x5a002080
203
#define CMPO    0x5a002000
204
 
205
#define B       0x08000000
206
#define BAL     0x0b000000
207
#define CALL    0x09000000
208
#define CALLS   0x66003800
209
#define RET     0x0a000000
210
 
211
/* These masks are used to build up a set of MEMB mode bits.  */
212
#define A_BIT           0x0400
213
#define I_BIT           0x0800
214
#define MEMB_BIT        0x1000
215
#define D_BIT           0x2000
216
 
217
/* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
218
   used).  */
219
#define MEMA_ABASE      0x2000
220
 
221
/* Info from which a MEMA or MEMB format instruction can be generated.  */
222
typedef struct memS
223
  {
224
    /* (First) 32 bits of instruction.  */
225
    long opcode;
226
    /* 0-(none), 12- or, 32-bit displacement needed.  */
227
    int disp;
228
    /* The expression in the source instruction from which the
229
       displacement should be determined.  */
230
    char *e;
231
  }
232
memS;
233
 
234
/* The two pieces of info we need to generate a register operand.  */
235
struct regop
236
  {
237
    int mode;                   /* 0 =>local/global/spec reg; 1=> literal or fp reg.  */
238
    int special;                /* 0 =>not a sfr;  1=> is a sfr (not valid w/mode=0).  */
239
    int n;                      /* Register number or literal value.  */
240
  };
241
 
242
/* Number and assembler mnemonic for all registers that can appear in
243
   operands.  */
244
static const struct
245
  {
246
    char *reg_name;
247
    int reg_num;
248
  }
249
regnames[] =
250
{
251
  { "pfp", 0 },
252
  { "sp", 1 },
253
  { "rip", 2 },
254
  { "r3", 3 },
255
  { "r4", 4 },
256
  { "r5", 5 },
257
  { "r6", 6 },
258
  { "r7", 7 },
259
  { "r8", 8 },
260
  { "r9", 9 },
261
  { "r10", 10 },
262
  { "r11", 11 },
263
  { "r12", 12 },
264
  { "r13", 13 },
265
  { "r14", 14 },
266
  { "r15", 15 },
267
  { "g0", 16 },
268
  { "g1", 17 },
269
  { "g2", 18 },
270
  { "g3", 19 },
271
  { "g4", 20 },
272
  { "g5", 21 },
273
  { "g6", 22 },
274
  { "g7", 23 },
275
  { "g8", 24 },
276
  { "g9", 25 },
277
  { "g10", 26 },
278
  { "g11", 27 },
279
  { "g12", 28 },
280
  { "g13", 29 },
281
  { "g14", 30 },
282
  { "fp", 31 },
283
 
284
  /* Numbers for special-function registers are for assembler internal
285
     use only: they are scaled back to range [0-31] for binary output.  */
286
#define SF0     32
287
 
288
  { "sf0", 32 },
289
  { "sf1", 33 },
290
  { "sf2", 34 },
291
  { "sf3", 35 },
292
  { "sf4", 36 },
293
  { "sf5", 37 },
294
  { "sf6", 38 },
295
  { "sf7", 39 },
296
  { "sf8", 40 },
297
  { "sf9", 41 },
298
  { "sf10", 42 },
299
  { "sf11", 43 },
300
  { "sf12", 44 },
301
  { "sf13", 45 },
302
  { "sf14", 46 },
303
  { "sf15", 47 },
304
  { "sf16", 48 },
305
  { "sf17", 49 },
306
  { "sf18", 50 },
307
  { "sf19", 51 },
308
  { "sf20", 52 },
309
  { "sf21", 53 },
310
  { "sf22", 54 },
311
  { "sf23", 55 },
312
  { "sf24", 56 },
313
  { "sf25", 57 },
314
  { "sf26", 58 },
315
  { "sf27", 59 },
316
  { "sf28", 60 },
317
  { "sf29", 61 },
318
  { "sf30", 62 },
319
  { "sf31", 63 },
320
 
321
  /* Numbers for floating point registers are for assembler internal
322
     use only: they are scaled back to [0-3] for binary output.  */
323
#define FP0     64
324
 
325
  { "fp0", 64 },
326
  { "fp1", 65 },
327
  { "fp2", 66 },
328
  { "fp3", 67 },
329
 
330
  { NULL, 0 },                           /* END OF LIST */
331
};
332
 
333
#define IS_RG_REG(n)    ((0 <= (n)) && ((n) < SF0))
334
#define IS_SF_REG(n)    ((SF0 <= (n)) && ((n) < FP0))
335
#define IS_FP_REG(n)    ((n) >= FP0)
336
 
337
/* Number and assembler mnemonic for all registers that can appear as
338
   'abase' (indirect addressing) registers.  */
339
static const struct
340
{
341
  char *areg_name;
342
  int areg_num;
343
}
344
aregs[] =
345
{
346
  { "(pfp)", 0 },
347
  { "(sp)", 1 },
348
  { "(rip)", 2 },
349
  { "(r3)", 3 },
350
  { "(r4)", 4 },
351
  { "(r5)", 5 },
352
  { "(r6)", 6 },
353
  { "(r7)", 7 },
354
  { "(r8)", 8 },
355
  { "(r9)", 9 },
356
  { "(r10)", 10 },
357
  { "(r11)", 11 },
358
  { "(r12)", 12 },
359
  { "(r13)", 13 },
360
  { "(r14)", 14 },
361
  { "(r15)", 15 },
362
  { "(g0)", 16 },
363
  { "(g1)", 17 },
364
  { "(g2)", 18 },
365
  { "(g3)", 19 },
366
  { "(g4)", 20 },
367
  { "(g5)", 21 },
368
  { "(g6)", 22 },
369
  { "(g7)", 23 },
370
  { "(g8)", 24 },
371
  { "(g9)", 25 },
372
  { "(g10)", 26 },
373
  { "(g11)", 27 },
374
  { "(g12)", 28 },
375
  { "(g13)", 29 },
376
  { "(g14)", 30 },
377
  { "(fp)", 31 },
378
 
379
#define IPREL   32
380
  /* For assembler internal use only: this number never appears in binary
381
     output.  */
382
  { "(ip)", IPREL },
383
 
384
  { NULL, 0 },                           /* END OF LIST */
385
};
386
 
387
/* Hash tables.  */
388
static struct hash_control *op_hash;    /* Opcode mnemonics.  */
389
static struct hash_control *reg_hash;   /* Register name hash table.  */
390
static struct hash_control *areg_hash;  /* Abase register hash table.  */
391
 
392
/* Architecture for which we are assembling.  */
393
#define ARCH_ANY        0        /* Default: no architecture checking done.  */
394
#define ARCH_KA         1
395
#define ARCH_KB         2
396
#define ARCH_MC         3
397
#define ARCH_CA         4
398
#define ARCH_JX         5
399
#define ARCH_HX         6
400
int architecture = ARCH_ANY;    /* Architecture requested on invocation line.  */
401
int iclasses_seen;              /* OR of instruction classes (I_* constants)
402
                                      for which we've actually assembled
403
                                        instructions.  */
404
 
405
/* BRANCH-PREDICTION INSTRUMENTATION
406
 
407
        The following supports generation of branch-prediction instrumentation
408
        (turned on by -b switch).  The instrumentation collects counts
409
        of branches taken/not-taken for later input to a utility that will
410
        set the branch prediction bits of the instructions in accordance with
411
        the behavior observed.  (Note that the KX series does not have
412
        brach-prediction.)
413
 
414
        The instrumentation consists of:
415
 
416
        (1) before and after each conditional branch, a call to an external
417
            routine that increments and steps over an inline counter.  The
418
            counter itself, initialized to 0, immediately follows the call
419
            instruction.  For each branch, the counter following the branch
420
            is the number of times the branch was not taken, and the difference
421
            between the counters is the number of times it was taken.  An
422
            example of an instrumented conditional branch:
423
 
424
                                call    BR_CNT_FUNC
425
                                .word   0
426
                LBRANCH23:      be      label
427
                                call    BR_CNT_FUNC
428
                                .word   0
429
 
430
        (2) a table of pointers to the instrumented branches, so that an
431
            external postprocessing routine can locate all of the counters.
432
            the table begins with a 2-word header: a pointer to the next in
433
            a linked list of such tables (initialized to 0);  and a count
434
            of the number of entries in the table (exclusive of the header.
435
 
436
            Note that input source code is expected to already contain calls
437
            an external routine that will link the branch local table into a
438
            list of such tables.  */
439
 
440
/* Number of branches instrumented so far.  Also used to generate
441
   unique local labels for each instrumented branch.  */
442
static int br_cnt;
443
 
444
#define BR_LABEL_BASE   "LBRANCH"
445
/* Basename of local labels on instrumented branches, to avoid
446
   conflict with compiler- generated local labels.  */
447
 
448
#define BR_CNT_FUNC     "__inc_branch"
449
/* Name of the external routine that will increment (and step over) an
450
   inline counter.  */
451
 
452
#define BR_TAB_NAME     "__BRANCH_TABLE__"
453
/* Name of the table of pointers to branches.  A local (i.e.,
454
   non-external) symbol.  */
455
 
456
static void ctrl_fmt (char *, long, int);
457
 
458
 
459
void
460
md_begin (void)
461
{
462
  int i;                        /* Loop counter.  */
463
  const struct i960_opcode *oP; /* Pointer into opcode table.  */
464
  const char *retval;           /* Value returned by hash functions.  */
465
 
466
  op_hash = hash_new ();
467
  reg_hash = hash_new ();
468
  areg_hash = hash_new ();
469
 
470
  /* For some reason, the base assembler uses an empty string for "no
471
     error message", instead of a NULL pointer.  */
472
  retval = 0;
473
 
474
  for (oP = i960_opcodes; oP->name && !retval; oP++)
475
    retval = hash_insert (op_hash, oP->name, (void *) oP);
476
 
477
  for (i = 0; regnames[i].reg_name && !retval; i++)
478
    retval = hash_insert (reg_hash, regnames[i].reg_name,
479
                          (char *) &regnames[i].reg_num);
480
 
481
  for (i = 0; aregs[i].areg_name && !retval; i++)
482
    retval = hash_insert (areg_hash, aregs[i].areg_name,
483
                          (char *) &aregs[i].areg_num);
484
 
485
  if (retval)
486
    as_fatal (_("Hashing returned \"%s\"."), retval);
487
}
488
 
489
/* parse_expr:          parse an expression
490
 
491
   Use base assembler's expression parser to parse an expression.
492
   It, unfortunately, runs off a global which we have to save/restore
493
   in order to make it work for us.
494
 
495
   An empty expression string is treated as an absolute 0.
496
 
497
   Sets O_illegal regardless of expression evaluation if entire input
498
   string is not consumed in the evaluation -- tolerate no dangling junk!  */
499
 
500
static void
501
parse_expr (char *textP,                /* Text of expression to be parsed.  */
502
            expressionS *expP)          /* Where to put the results of parsing.  */
503
{
504
  char *save_in;                /* Save global here.  */
505
  symbolS *symP;
506
 
507
  know (textP);
508
 
509
  if (*textP == '\0')
510
    {
511
      /* Treat empty string as absolute 0.  */
512
      expP->X_add_symbol = expP->X_op_symbol = NULL;
513
      expP->X_add_number = 0;
514
      expP->X_op = O_constant;
515
    }
516
  else
517
    {
518
      save_in = input_line_pointer;     /* Save global.  */
519
      input_line_pointer = textP;       /* Make parser work for us.  */
520
 
521
      (void) expression (expP);
522
      if ((size_t) (input_line_pointer - textP) != strlen (textP))
523
        /* Did not consume all of the input.  */
524
        expP->X_op = O_illegal;
525
 
526
      symP = expP->X_add_symbol;
527
      if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
528
        /* Register name in an expression.  */
529
        /* FIXME: this isn't much of a check any more.  */
530
        expP->X_op = O_illegal;
531
 
532
      input_line_pointer = save_in;     /* Restore global.  */
533
    }
534
}
535
 
536
/* emit:        output instruction binary
537
 
538
   Output instruction binary, in target byte order, 4 bytes at a time.
539
   Return pointer to where it was placed.  */
540
 
541
static char *
542
emit (long instr)               /* Word to be output, host byte order.  */
543
{
544
  char *toP;                    /* Where to output it.  */
545
 
546
  toP = frag_more (4);          /* Allocate storage.  */
547
  md_number_to_chars (toP, instr, 4);   /* Convert to target byte order.  */
548
  return toP;
549
}
550
 
551
/* get_cdisp:   handle displacement for a COBR or CTRL instruction.
552
 
553
   Parse displacement for a COBR or CTRL instruction.
554
 
555
   If successful, output the instruction opcode and set up for it,
556
   depending on the arg 'var_frag', either:
557
            o an address fixup to be done when all symbol values are known, or
558
            o a varying length code fragment, with address fixup info.  This
559
                will be done for cobr instructions that may have to be relaxed
560
                in to compare/branch instructions (8 bytes) if the final
561
                address displacement is greater than 13 bits.  */
562
 
563
static void
564
get_cdisp (char *dispP, /* Displacement as specified in source instruction.  */
565
           char *ifmtP, /* "COBR" or "CTRL" (for use in error message).  */
566
           long instr,  /* Instruction needing the displacement.  */
567
           int numbits, /* # bits of displacement (13 for COBR, 24 for CTRL).  */
568
           int var_frag,/* 1 if varying length code fragment should be emitted;
569
 
570
           int callj)   /* 1 if callj relocation should be done; else 0.  */
571
{
572
  expressionS e;                /* Parsed expression.  */
573
  fixS *fixP;                   /* Structure describing needed address fix.  */
574
  char *outP;                   /* Where instruction binary is output to.  */
575
 
576
  fixP = NULL;
577
 
578
  parse_expr (dispP, &e);
579
  switch (e.X_op)
580
    {
581
    case O_illegal:
582
      as_bad (_("expression syntax error"));
583
 
584
    case O_symbol:
585
      if (S_GET_SEGMENT (e.X_add_symbol) == now_seg
586
          || S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
587
        {
588
          if (var_frag)
589
            {
590
              outP = frag_more (8);     /* Allocate worst-case storage.  */
591
              md_number_to_chars (outP, instr, 4);
592
              frag_variant (rs_machine_dependent, 4, 4, 1,
593
                            adds (e), offs (e), outP);
594
            }
595
          else
596
            {
597
              /* Set up a new fix structure, so address can be updated
598
                 when all symbol values are known.  */
599
              outP = emit (instr);
600
              fixP = fix_new (frag_now,
601
                              outP - frag_now->fr_literal,
602
                              4,
603
                              adds (e),
604
                              offs (e),
605
                              1,
606
                              NO_RELOC);
607
 
608
              fixP->fx_tcbit = callj;
609
 
610
              /* We want to modify a bit field when the address is
611
                 known.  But we don't need all the garbage in the
612
                 bit_fix structure.  So we're going to lie and store
613
                 the number of bits affected instead of a pointer.  */
614
              fixP->fx_bit_fixP = (bit_fixS *) (size_t) numbits;
615
            }
616
        }
617
      else
618
        as_bad (_("attempt to branch into different segment"));
619
      break;
620
 
621
    default:
622
      as_bad (_("target of %s instruction must be a label"), ifmtP);
623
      break;
624
    }
625
}
626
 
627
static int
628
md_chars_to_number (char * val,         /* Value in target byte order.  */
629
                    int n)              /* Number of bytes in the input.  */
630
{
631
  int retval;
632
 
633
  for (retval = 0; n--;)
634
    {
635
      retval <<= 8;
636
      retval |= (unsigned char) val[n];
637
    }
638
  return retval;
639
}
640
 
641
/* mema_to_memb:        convert a MEMA-format opcode to a MEMB-format opcode.
642
 
643
   There are 2 possible MEMA formats:
644
        - displacement only
645
        - displacement + abase
646
 
647
   They are distinguished by the setting of the MEMA_ABASE bit.  */
648
 
649
static void
650
mema_to_memb (char * opcodeP)   /* Where to find the opcode, in target byte order.  */
651
{
652
  long opcode;                  /* Opcode in host byte order.  */
653
  long mode;                    /* Mode bits for MEMB instruction.  */
654
 
655
  opcode = md_chars_to_number (opcodeP, 4);
656
  know (!(opcode & MEMB_BIT));
657
 
658
  mode = MEMB_BIT | D_BIT;
659
  if (opcode & MEMA_ABASE)
660
    mode |= A_BIT;
661
 
662
  opcode &= 0xffffc000;         /* Clear MEMA offset and mode bits.  */
663
  opcode |= mode;               /* Set MEMB mode bits.  */
664
 
665
  md_number_to_chars (opcodeP, opcode, 4);
666
}
667
 
668
/* targ_has_sfr:
669
 
670
   Return TRUE iff the target architecture supports the specified
671
   special-function register (sfr).  */
672
 
673
static int
674
targ_has_sfr (int n)            /* Number (0-31) of sfr.  */
675
{
676
  switch (architecture)
677
    {
678
    case ARCH_KA:
679
    case ARCH_KB:
680
    case ARCH_MC:
681
    case ARCH_JX:
682
      return 0;
683
    case ARCH_HX:
684
      return ((0 <= n) && (n <= 4));
685
    case ARCH_CA:
686
    default:
687
      return ((0 <= n) && (n <= 2));
688
    }
689
}
690
 
691
/* Look up a (suspected) register name in the register table and return the
692
   associated register number (or -1 if not found).  */
693
 
694
static int
695
get_regnum (char *regname)      /* Suspected register name.  */
696
{
697
  int *rP;
698
 
699
  rP = (int *) hash_find (reg_hash, regname);
700
  return (rP == NULL) ? -1 : *rP;
701
}
702
 
703
/* syntax: Issue a syntax error.  */
704
 
705
static void
706
syntax (void)
707
{
708
  as_bad (_("syntax error"));
709
}
710
 
711
/* parse_regop: parse a register operand.
712
 
713
   In case of illegal operand, issue a message and return some valid
714
   information so instruction processing can continue.  */
715
 
716
static void
717
parse_regop (struct regop *regopP,      /* Where to put description of register operand.  */
718
             char *optext,              /* Text of operand.  */
719
             char opdesc)               /* Descriptor byte:  what's legal for this operand.  */
720
{
721
  int n;                        /* Register number.  */
722
  expressionS e;                /* Parsed expression.  */
723
 
724
  /* See if operand is a register.  */
725
  n = get_regnum (optext);
726
  if (n >= 0)
727
    {
728
      if (IS_RG_REG (n))
729
        {
730
          /* Global or local register.  */
731
          if (!REG_ALIGN (opdesc, n))
732
            as_bad (_("unaligned register"));
733
 
734
          regopP->n = n;
735
          regopP->mode = 0;
736
          regopP->special = 0;
737
          return;
738
        }
739
      else if (IS_FP_REG (n) && FP_OK (opdesc))
740
        {
741
          /* Floating point register, and it's allowed.  */
742
          regopP->n = n - FP0;
743
          regopP->mode = 1;
744
          regopP->special = 0;
745
          return;
746
        }
747
      else if (IS_SF_REG (n) && SFR_OK (opdesc))
748
        {
749
          /* Special-function register, and it's allowed.  */
750
          regopP->n = n - SF0;
751
          regopP->mode = 0;
752
          regopP->special = 1;
753
          if (!targ_has_sfr (regopP->n))
754
            as_bad (_("no such sfr in this architecture"));
755
 
756
          return;
757
        }
758
    }
759
  else if (LIT_OK (opdesc))
760
    {
761
      /* How about a literal?  */
762
      regopP->mode = 1;
763
      regopP->special = 0;
764
      if (FP_OK (opdesc))
765
        {
766
          /* Floating point literal acceptable.  */
767
          /* Skip over 0f, 0d, or 0e prefix.  */
768
          if ((optext[0] == '0')
769
              && (optext[1] >= 'd')
770
              && (optext[1] <= 'f'))
771
            optext += 2;
772
 
773
          if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
774
            {
775
              regopP->n = 0x10;
776
              return;
777
            }
778
 
779
          if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
780
            {
781
              regopP->n = 0x16;
782
              return;
783
            }
784
        }
785
      else
786
        {
787
          /* Fixed point literal acceptable.  */
788
          parse_expr (optext, &e);
789
          if (e.X_op != O_constant
790
              || (offs (e) < 0) || (offs (e) > 31))
791
            {
792
              as_bad (_("illegal literal"));
793
              offs (e) = 0;
794
            }
795
          regopP->n = offs (e);
796
          return;
797
        }
798
    }
799
 
800
  /* Nothing worked.  */
801
  syntax ();
802
  regopP->mode = 0;              /* Register r0 is always a good one.  */
803
  regopP->n = 0;
804
  regopP->special = 0;
805
}
806
 
807
/* get_ispec:   parse a memory operand for an index specification
808
 
809
   Here, an "index specification" is taken to be anything surrounded
810
   by square brackets and NOT followed by anything else.
811
 
812
   If it's found, detach it from the input string, remove the surrounding
813
   square brackets, and return a pointer to it.  Otherwise, return NULL.  */
814
 
815
static char *
816
get_ispec (char *textP)  /* Pointer to memory operand from source instruction, no white space.  */
817
 
818
{
819
  /* Points to start of index specification.  */
820
  char *start;
821
  /* Points to end of index specification.  */
822
  char *end;
823
 
824
  /* Find opening square bracket, if any.  */
825
  start = strchr (textP, '[');
826
 
827
  if (start != NULL)
828
    {
829
      /* Eliminate '[', detach from rest of operand.  */
830
      *start++ = '\0';
831
 
832
      end = strchr (start, ']');
833
 
834
      if (end == NULL)
835
        as_bad (_("unmatched '['"));
836
      else
837
        {
838
          /* Eliminate ']' and make sure it was the last thing
839
             in the string.  */
840
          *end = '\0';
841
          if (*(end + 1) != '\0')
842
            as_bad (_("garbage after index spec ignored"));
843
        }
844
    }
845
  return start;
846
}
847
 
848
/* parse_memop: parse a memory operand
849
 
850
        This routine is based on the observation that the 4 mode bits of the
851
        MEMB format, taken individually, have fairly consistent meaning:
852
 
853
                 M3 (bit 13): 1 if displacement is present (D_BIT)
854
                 M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
855
                 M1 (bit 11): 1 if index is present (I_BIT)
856
                 M0 (bit 10): 1 if abase is present (A_BIT)
857
 
858
        So we parse the memory operand and set bits in the mode as we find
859
        things.  Then at the end, if we go to MEMB format, we need only set
860
        the MEMB bit (M2) and our mode is built for us.
861
 
862
        Unfortunately, I said "fairly consistent".  The exceptions:
863
 
864
                 DBIA
865
                 0100   Would seem illegal, but means "abase-only".
866
 
867
                 0101   Would seem to mean "abase-only" -- it means IP-relative.
868
                        Must be converted to 0100.
869
 
870
                 0110   Would seem to mean "index-only", but is reserved.
871
                        We turn on the D bit and provide a 0 displacement.
872
 
873
        The other thing to observe is that we parse from the right, peeling
874
        things * off as we go:  first any index spec, then any abase, then
875
        the displacement.  */
876
 
877
static void
878
parse_memop (memS *memP,        /* Where to put the results.  */
879
             char *argP,        /* Text of the operand to be parsed.  */
880
             int optype)        /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16.  */
881
{
882
  char *indexP;                 /* Pointer to index specification with "[]" removed.  */
883
  char *p;                      /* Temp char pointer.  */
884
  char iprel_flag;              /* True if this is an IP-relative operand.  */
885
  int regnum;                   /* Register number.  */
886
  /* Scale factor: 1,2,4,8, or 16.  Later converted to internal format
887
     (0,1,2,3,4 respectively).  */
888
  int scale;
889
  int mode;                     /* MEMB mode bits.  */
890
  int *intP;                    /* Pointer to register number.  */
891
 
892
  /* The following table contains the default scale factors for each
893
     type of memory instruction.  It is accessed using (optype-MEM1)
894
     as an index -- thus it assumes the 'optype' constants are
895
     assigned consecutive values, in the order they appear in this
896
     table.  */
897
  static const int def_scale[] =
898
  {
899
    1,                          /* MEM1 */
900
    2,                          /* MEM2 */
901
    4,                          /* MEM4 */
902
    8,                          /* MEM8 */
903
    -1,                         /* MEM12 -- no valid default */
904
    16                          /* MEM16 */
905
  };
906
 
907
  iprel_flag = mode = 0;
908
 
909
  /* Any index present? */
910
  indexP = get_ispec (argP);
911
  if (indexP)
912
    {
913
      p = strchr (indexP, '*');
914
      if (p == NULL)
915
        {
916
          /* No explicit scale -- use default for this instruction
917
             type and assembler mode.  */
918
          if (flag_mri)
919
            scale = 1;
920
          else
921
            /* GNU960 compatibility */
922
            scale = def_scale[optype - MEM1];
923
        }
924
      else
925
        {
926
          *p++ = '\0';          /* Eliminate '*' */
927
 
928
          /* Now indexP->a '\0'-terminated register name,
929
             and p->a scale factor.  */
930
 
931
          if (!strcmp (p, "16"))
932
            scale = 16;
933
          else if (strchr ("1248", *p) && (p[1] == '\0'))
934
            scale = *p - '0';
935
          else
936
            scale = -1;
937
        }
938
 
939
      regnum = get_regnum (indexP);     /* Get index reg. # */
940
      if (!IS_RG_REG (regnum))
941
        {
942
          as_bad (_("invalid index register"));
943
          return;
944
        }
945
 
946
      /* Convert scale to its binary encoding.  */
947
      switch (scale)
948
        {
949
        case 1:
950
          scale = 0 << 7;
951
          break;
952
        case 2:
953
          scale = 1 << 7;
954
          break;
955
        case 4:
956
          scale = 2 << 7;
957
          break;
958
        case 8:
959
          scale = 3 << 7;
960
          break;
961
        case 16:
962
          scale = 4 << 7;
963
          break;
964
        default:
965
          as_bad (_("invalid scale factor"));
966
          return;
967
        };
968
 
969
      memP->opcode |= scale | regnum;   /* Set index bits in opcode.  */
970
      mode |= I_BIT;                    /* Found a valid index spec.  */
971
    }
972
 
973
  /* Any abase (Register Indirect) specification present?  */
974
  if ((p = strrchr (argP, '(')) != NULL)
975
    {
976
      /* "(" is there -- does it start a legal abase spec?  If not, it
977
         could be part of a displacement expression.  */
978
      intP = (int *) hash_find (areg_hash, p);
979
      if (intP != NULL)
980
        {
981
          /* Got an abase here.  */
982
          regnum = *intP;
983
          *p = '\0';            /* Discard register spec.  */
984
          if (regnum == IPREL)
985
            /* We have to specialcase ip-rel mode.  */
986
            iprel_flag = 1;
987
          else
988
            {
989
              memP->opcode |= regnum << 14;
990
              mode |= A_BIT;
991
            }
992
        }
993
    }
994
 
995
  /* Any expression present?  */
996
  memP->e = argP;
997
  if (*argP != '\0')
998
    mode |= D_BIT;
999
 
1000
  /* Special-case ip-relative addressing.  */
1001
  if (iprel_flag)
1002
    {
1003
      if (mode & I_BIT)
1004
        syntax ();
1005
      else
1006
        {
1007
          memP->opcode |= 5 << 10;      /* IP-relative mode.  */
1008
          memP->disp = 32;
1009
        }
1010
      return;
1011
    }
1012
 
1013
  /* Handle all other modes.  */
1014
  switch (mode)
1015
    {
1016
    case D_BIT | A_BIT:
1017
      /* Go with MEMA instruction format for now (grow to MEMB later
1018
         if 12 bits is not enough for the displacement).  MEMA format
1019
         has a single mode bit: set it to indicate that abase is
1020
         present.  */
1021
      memP->opcode |= MEMA_ABASE;
1022
      memP->disp = 12;
1023
      break;
1024
 
1025
    case D_BIT:
1026
      /* Go with MEMA instruction format for now (grow to MEMB later
1027
         if 12 bits is not enough for the displacement).  */
1028
      memP->disp = 12;
1029
      break;
1030
 
1031
    case A_BIT:
1032
      /* For some reason, the bit string for this mode is not
1033
         consistent: it should be 0 (exclusive of the MEMB bit), so we
1034
         set it "by hand" here.  */
1035
      memP->opcode |= MEMB_BIT;
1036
      break;
1037
 
1038
    case A_BIT | I_BIT:
1039
      /* set MEMB bit in mode, and OR in mode bits.  */
1040
      memP->opcode |= mode | MEMB_BIT;
1041
      break;
1042
 
1043
    case I_BIT:
1044
      /* Treat missing displacement as displacement of 0.  */
1045
      mode |= D_BIT;
1046
      /* Fall into next case.  */
1047
    case D_BIT | A_BIT | I_BIT:
1048
    case D_BIT | I_BIT:
1049
      /* Set MEMB bit in mode, and OR in mode bits.  */
1050
      memP->opcode |= mode | MEMB_BIT;
1051
      memP->disp = 32;
1052
      break;
1053
 
1054
    default:
1055
      syntax ();
1056
      break;
1057
    }
1058
}
1059
 
1060
/* Generate a MEMA- or MEMB-format instruction.  */
1061
 
1062
static void
1063
mem_fmt (char *args[],          /* args[0]->opcode mnemonic, args[1-3]->operands.  */
1064
         struct i960_opcode *oP,/* Pointer to description of instruction.  */
1065
         int callx)             /* Is this a callx opcode.  */
1066
{
1067
  int i;                        /* Loop counter.  */
1068
  struct regop regop;           /* Description of register operand.  */
1069
  char opdesc;                  /* Operand descriptor byte.  */
1070
  memS instr;                   /* Description of binary to be output.  */
1071
  char *outP;                   /* Where the binary was output to.  */
1072
  expressionS expr;             /* Parsed expression.  */
1073
  /* ->description of deferred address fixup.  */
1074
  fixS *fixP;
1075
 
1076
#ifdef OBJ_COFF
1077
  /* COFF support isn't in place yet for callx relaxing.  */
1078
  callx = 0;
1079
#endif
1080
 
1081
  memset (&instr, '\0', sizeof (memS));
1082
  instr.opcode = oP->opcode;
1083
 
1084
  /* Process operands.  */
1085
  for (i = 1; i <= oP->num_ops; i++)
1086
    {
1087
      opdesc = oP->operand[i - 1];
1088
 
1089
      if (MEMOP (opdesc))
1090
        parse_memop (&instr, args[i], oP->format);
1091
      else
1092
        {
1093
          parse_regop (&regop, args[i], opdesc);
1094
          instr.opcode |= regop.n << 19;
1095
        }
1096
    }
1097
 
1098
  /* Parse the displacement; this must be done before emitting the
1099
     opcode, in case it is an expression using `.'.  */
1100
  parse_expr (instr.e, &expr);
1101
 
1102
  /* Output opcode.  */
1103
  outP = emit (instr.opcode);
1104
 
1105
  if (instr.disp == 0)
1106
    return;
1107
 
1108
  /* Process the displacement.  */
1109
  switch (expr.X_op)
1110
    {
1111
    case O_illegal:
1112
      as_bad (_("expression syntax error"));
1113
      break;
1114
 
1115
    case O_constant:
1116
      if (instr.disp == 32)
1117
        (void) emit (offs (expr));      /* Output displacement.  */
1118
      else
1119
        {
1120
          /* 12-bit displacement.  */
1121
          if (offs (expr) & ~0xfff)
1122
            {
1123
              /* Won't fit in 12 bits: convert already-output
1124
                 instruction to MEMB format, output
1125
                 displacement.  */
1126
              mema_to_memb (outP);
1127
              (void) emit (offs (expr));
1128
            }
1129
          else
1130
            {
1131
              /* WILL fit in 12 bits:  OR into opcode and
1132
                 overwrite the binary we already put out.  */
1133
              instr.opcode |= offs (expr);
1134
              md_number_to_chars (outP, instr.opcode, 4);
1135
            }
1136
        }
1137
      break;
1138
 
1139
    default:
1140
      if (instr.disp == 12)
1141
        /* Displacement is dependent on a symbol, whose value
1142
           may change at link time.  We HAVE to reserve 32 bits.
1143
           Convert already-output opcode to MEMB format.  */
1144
        mema_to_memb (outP);
1145
 
1146
      /* Output 0 displacement and set up address fixup for when
1147
         this symbol's value becomes known.  */
1148
      outP = emit ((long) 0);
1149
      fixP = fix_new_exp (frag_now,
1150
                          outP - frag_now->fr_literal,
1151
                          4, & expr, 0, NO_RELOC);
1152
      /* Steve's linker relaxing hack.  Mark this 32-bit relocation as
1153
         being in the instruction stream, specifically as part of a callx
1154
         instruction.  */
1155
      fixP->fx_bsr = callx;
1156
      break;
1157
    }
1158
}
1159
 
1160
/* targ_has_iclass:
1161
 
1162
   Return TRUE iff the target architecture supports the indicated
1163
   class of instructions.  */
1164
 
1165
static int
1166
targ_has_iclass (int ic) /* Instruction class;  one of:
1167
                            I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2.  */
1168
{
1169
  iclasses_seen |= ic;
1170
 
1171
  switch (architecture)
1172
    {
1173
    case ARCH_KA:
1174
      return ic & (I_BASE | I_KX);
1175
    case ARCH_KB:
1176
      return ic & (I_BASE | I_KX | I_FP | I_DEC);
1177
    case ARCH_MC:
1178
      return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
1179
    case ARCH_CA:
1180
      return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
1181
    case ARCH_JX:
1182
      return ic & (I_BASE | I_CX2 | I_JX);
1183
    case ARCH_HX:
1184
      return ic & (I_BASE | I_CX2 | I_JX | I_HX);
1185
    default:
1186
      if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
1187
          && (iclasses_seen & (I_CX | I_CX2)))
1188
        {
1189
          as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
1190
          iclasses_seen &= ~ic;
1191
        }
1192
      return 1;
1193
    }
1194
}
1195
 
1196
/* shift_ok:
1197
   Determine if a "shlo" instruction can be used to implement a "ldconst".
1198
   This means that some number X < 32 can be shifted left to produce the
1199
   constant of interest.
1200
 
1201
   Return the shift count, or 0 if we can't do it.
1202
   Caller calculates X by shifting original constant right 'shift' places.  */
1203
 
1204
static int
1205
shift_ok (int n)                /* The constant of interest.  */
1206
{
1207
  int shift;                    /* The shift count.  */
1208
 
1209
  if (n <= 0)
1210
    /* Can't do it for negative numbers.  */
1211
    return 0;
1212
 
1213
  /* Shift 'n' right until a 1 is about to be lost.  */
1214
  for (shift = 0; (n & 1) == 0; shift++)
1215
    n >>= 1;
1216
 
1217
  if (n >= 32)
1218
    return 0;
1219
 
1220
  return shift;
1221
}
1222
 
1223
/* parse_ldcont:
1224
   Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1225
   i80960 instruction.
1226
 
1227
   Assumes the input consists of:
1228
                arg[0]  opcode mnemonic ('ldconst')
1229
                arg[1]  first operand (constant)
1230
                arg[2]  name of register to be loaded
1231
 
1232
   Replaces opcode and/or operands as appropriate.
1233
 
1234
   Returns the new number of arguments, or -1 on failure.  */
1235
 
1236
static int
1237
parse_ldconst (char *arg[])     /* See above.  */
1238
{
1239
  int n;                        /* Constant to be loaded.  */
1240
  int shift;                    /* Shift count for "shlo" instruction.  */
1241
  static char buf[5];           /* Literal for first operand.  */
1242
  static char buf2[5];          /* Literal for second operand.  */
1243
  expressionS e;                /* Parsed expression.  */
1244
 
1245
  arg[3] = NULL;                /* So we can tell at the end if it got used or not.  */
1246
 
1247
  parse_expr (arg[1], &e);
1248
  switch (e.X_op)
1249
    {
1250
    default:
1251
      /* We're dependent on one or more symbols -- use "lda".  */
1252
      arg[0] = "lda";
1253
      break;
1254
 
1255
    case O_constant:
1256
      /* Try the following mappings:
1257
              ldconst   0,<reg>  -> mov  0,<reg>
1258
              ldconst  31,<reg>  -> mov  31,<reg>
1259
              ldconst  32,<reg>  -> addo 1,31,<reg>
1260
              ldconst  62,<reg>  -> addo 31,31,<reg>
1261
              ldconst  64,<reg>  -> shlo 8,3,<reg>
1262
              ldconst  -1,<reg>  -> subo 1,0,<reg>
1263
              ldconst -31,<reg>  -> subo 31,0,<reg>
1264
 
1265
         Anything else becomes:
1266
                lda xxx,<reg>.  */
1267
      n = offs (e);
1268
      if ((0 <= n) && (n <= 31))
1269
        arg[0] = "mov";
1270
      else if ((-31 <= n) && (n <= -1))
1271
        {
1272
          arg[0] = "subo";
1273
          arg[3] = arg[2];
1274
          sprintf (buf, "%d", -n);
1275
          arg[1] = buf;
1276
          arg[2] = "0";
1277
        }
1278
      else if ((32 <= n) && (n <= 62))
1279
        {
1280
          arg[0] = "addo";
1281
          arg[3] = arg[2];
1282
          arg[1] = "31";
1283
          sprintf (buf, "%d", n - 31);
1284
          arg[2] = buf;
1285
        }
1286
      else if ((shift = shift_ok (n)) != 0)
1287
        {
1288
          arg[0] = "shlo";
1289
          arg[3] = arg[2];
1290
          sprintf (buf, "%d", shift);
1291
          arg[1] = buf;
1292
          sprintf (buf2, "%d", n >> shift);
1293
          arg[2] = buf2;
1294
        }
1295
      else
1296
        arg[0] = "lda";
1297
      break;
1298
 
1299
    case O_illegal:
1300
      as_bad (_("invalid constant"));
1301
      return -1;
1302
      break;
1303
    }
1304
  return (arg[3] == 0) ? 2 : 3;
1305
}
1306
 
1307
/* reg_fmt:     generate a REG-format instruction.  */
1308
 
1309
static void
1310
reg_fmt (char *args[],          /* args[0]->opcode mnemonic, args[1-3]->operands.  */
1311
         struct i960_opcode *oP)/* Pointer to description of instruction.  */
1312
{
1313
  long instr;                   /* Binary to be output.  */
1314
  struct regop regop;           /* Description of register operand.  */
1315
  int n_ops;                    /* Number of operands.  */
1316
 
1317
  instr = oP->opcode;
1318
  n_ops = oP->num_ops;
1319
 
1320
  if (n_ops >= 1)
1321
    {
1322
      parse_regop (&regop, args[1], oP->operand[0]);
1323
 
1324
      if ((n_ops == 1) && !(instr & M3))
1325
        {
1326
          /* 1-operand instruction in which the dst field should
1327
             be used (instead of src1).  */
1328
          regop.n <<= 19;
1329
          if (regop.special)
1330
            regop.mode = regop.special;
1331
          regop.mode <<= 13;
1332
          regop.special = 0;
1333
        }
1334
      else
1335
        {
1336
          /* regop.n goes in bit 0, needs no shifting.  */
1337
          regop.mode <<= 11;
1338
          regop.special <<= 5;
1339
        }
1340
      instr |= regop.n | regop.mode | regop.special;
1341
    }
1342
 
1343
  if (n_ops >= 2)
1344
    {
1345
      parse_regop (&regop, args[2], oP->operand[1]);
1346
 
1347
      if ((n_ops == 2) && !(instr & M3))
1348
        {
1349
          /* 2-operand instruction in which the dst field should
1350
             be used instead of src2).  */
1351
          regop.n <<= 19;
1352
          if (regop.special)
1353
            regop.mode = regop.special;
1354
          regop.mode <<= 13;
1355
          regop.special = 0;
1356
        }
1357
      else
1358
        {
1359
          regop.n <<= 14;
1360
          regop.mode <<= 12;
1361
          regop.special <<= 6;
1362
        }
1363
      instr |= regop.n | regop.mode | regop.special;
1364
    }
1365
  if (n_ops == 3)
1366
    {
1367
      parse_regop (&regop, args[3], oP->operand[2]);
1368
      if (regop.special)
1369
        regop.mode = regop.special;
1370
      instr |= (regop.n <<= 19) | (regop.mode <<= 13);
1371
    }
1372
  emit (instr);
1373
}
1374
 
1375
/* get_args:    break individual arguments out of comma-separated list
1376
 
1377
   Input assumptions:
1378
        - all comments and labels have been removed
1379
        - all strings of whitespace have been collapsed to a single blank.
1380
        - all character constants ('x') have been replaced with decimal
1381
 
1382
   Output:
1383
        args[0] is untouched. args[1] points to first operand, etc. All args:
1384
        - are NULL-terminated
1385
        - contain no whitespace
1386
 
1387
   Return value:
1388
   Number of operands (0,1,2, or 3) or -1 on error.  */
1389
 
1390
static int
1391
get_args (char *p,      /* Pointer to comma-separated operands; Mucked by us.  */
1392
          char *args[]) /* Output arg: pointers to operands placed in args[1-3].
1393
                           Must accommodate 4 entries (args[0-3]).  */
1394
 
1395
{
1396
  int n;                /* Number of operands.  */
1397
  char *to;
1398
 
1399
  /* Skip lead white space.  */
1400
  while (*p == ' ')
1401
    p++;
1402
 
1403
  if (*p == '\0')
1404
    return 0;
1405
 
1406
  n = 1;
1407
  args[1] = p;
1408
 
1409
  /* Squeze blanks out by moving non-blanks toward start of string.
1410
     Isolate operands, whenever comma is found.  */
1411
  to = p;
1412
  while (*p != '\0')
1413
    {
1414
      if (*p == ' '
1415
          && (! ISALNUM (p[1])
1416
              || ! ISALNUM (p[-1])))
1417
        p++;
1418
      else if (*p == ',')
1419
        {
1420
          /* Start of operand.  */
1421
          if (n == 3)
1422
            {
1423
              as_bad (_("too many operands"));
1424
              return -1;
1425
            }
1426
          *to++ = '\0';         /* Terminate argument.  */
1427
          args[++n] = to;       /* Start next argument.  */
1428
          p++;
1429
        }
1430
      else
1431
        *to++ = *p++;
1432
    }
1433
  *to = '\0';
1434
  return n;
1435
}
1436
 
1437
/* i_scan:      perform lexical scan of ascii assembler instruction.
1438
 
1439
   Input assumptions:
1440
        - input string is an i80960 instruction (not a pseudo-op)
1441
        - all comments and labels have been removed
1442
        - all strings of whitespace have been collapsed to a single blank.
1443
 
1444
   Output:
1445
        args[0] points to opcode, other entries point to operands. All strings:
1446
        - are NULL-terminated
1447
        - contain no whitespace
1448
        - have character constants ('x') replaced with a decimal number
1449
 
1450
   Return value:
1451
     Number of operands (0,1,2, or 3) or -1 on error.  */
1452
 
1453
static int
1454
i_scan (char *iP,     /* Pointer to ascii instruction;  Mucked by us.  */
1455
        char *args[]) /* Output arg: pointers to opcode and operands placed here.
1456
                         Must accommodate 4 entries.  */
1457
{
1458
  /* Isolate opcode.  */
1459
  if (*(iP) == ' ')
1460
    iP++;
1461
 
1462
  args[0] = iP;
1463
  for (; *iP != ' '; iP++)
1464
    {
1465
      if (*iP == '\0')
1466
        {
1467
          /* There are no operands.  */
1468
          if (args[0] == iP)
1469
            {
1470
              /* We never moved: there was no opcode either!  */
1471
              as_bad (_("missing opcode"));
1472
              return -1;
1473
            }
1474
          return 0;
1475
        }
1476
    }
1477
  *iP++ = '\0';
1478
  return (get_args (iP, args));
1479
}
1480
 
1481
static void
1482
brcnt_emit (void)
1483
{
1484
  /* Emit call to "increment" routine.  */
1485
  ctrl_fmt (BR_CNT_FUNC, CALL, 1);
1486
  /* Emit inline counter to be incremented.  */
1487
  emit (0);
1488
}
1489
 
1490
static char *
1491
brlab_next (void)
1492
{
1493
  static char buf[20];
1494
 
1495
  sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1496
  return buf;
1497
}
1498
 
1499
static void
1500
ctrl_fmt (char *targP,          /* Pointer to text of lone operand (if any).  */
1501
          long opcode,          /* Template of instruction.  */
1502
          int num_ops)          /* Number of operands.  */
1503
{
1504
  int instrument;               /* TRUE iff we should add instrumentation to track
1505
                                   how often the branch is taken.  */
1506
 
1507
  if (num_ops == 0)
1508
    emit (opcode);              /* Output opcode.  */
1509
  else
1510
    {
1511
      instrument = instrument_branches && (opcode != CALL)
1512
        && (opcode != B) && (opcode != RET) && (opcode != BAL);
1513
 
1514
      if (instrument)
1515
        {
1516
          brcnt_emit ();
1517
          colon (brlab_next ());
1518
        }
1519
 
1520
      /* The operand MUST be an ip-relative displacement. Parse it
1521
         and set up address fix for the instruction we just output.  */
1522
      get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
1523
 
1524
      if (instrument)
1525
        brcnt_emit ();
1526
    }
1527
}
1528
 
1529
static void
1530
cobr_fmt (/* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1531
          char *arg[],
1532
          /* Opcode, with branch-prediction bits already set if necessary.  */
1533
          long opcode,
1534
          /* Pointer to description of instruction.  */
1535
          struct i960_opcode *oP)
1536
{
1537
  long instr;                   /* 32-bit instruction.  */
1538
  struct regop regop;           /* Description of register operand.  */
1539
  int n;                        /* Number of operands.  */
1540
  int var_frag;                 /* 1 if varying length code fragment should
1541
                                     be emitted;  0 if an address fix
1542
                                        should be emitted.  */
1543
 
1544
  instr = opcode;
1545
  n = oP->num_ops;
1546
 
1547
  if (n >= 1)
1548
    {
1549
      /* First operand (if any) of a COBR is always a register
1550
         operand.  Parse it.  */
1551
      parse_regop (&regop, arg[1], oP->operand[0]);
1552
      instr |= (regop.n << 19) | (regop.mode << 13);
1553
    }
1554
 
1555
  if (n >= 2)
1556
    {
1557
      /* Second operand (if any) of a COBR is always a register
1558
         operand.  Parse it.  */
1559
      parse_regop (&regop, arg[2], oP->operand[1]);
1560
      instr |= (regop.n << 14) | regop.special;
1561
    }
1562
 
1563
  if (n < 3)
1564
    emit (instr);
1565
  else
1566
    {
1567
      if (instrument_branches)
1568
        {
1569
          brcnt_emit ();
1570
          colon (brlab_next ());
1571
        }
1572
 
1573
      /* A third operand to a COBR is always a displacement.  Parse
1574
         it; if it's relaxable (a cobr "j" directive, or any cobr
1575
         other than bbs/bbc when the "-norelax" option is not in use)
1576
         set up a variable code fragment; otherwise set up an address
1577
         fix.  */
1578
      var_frag = !norelax || (oP->format == COJ);       /* TRUE or FALSE */
1579
      get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
1580
 
1581
      if (instrument_branches)
1582
        brcnt_emit ();
1583
    }
1584
}
1585
 
1586
/* Assumptions about the passed-in text:
1587
        - all comments, labels removed
1588
        - text is an instruction
1589
        - all white space compressed to single blanks
1590
        - all character constants have been replaced with decimal.  */
1591
 
1592
void
1593
md_assemble (char *textP)
1594
{
1595
  /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
1596
     mnemonic arg[1-3]->operands, with char constants replaced by
1597
     decimal numbers.  */
1598
  char *args[4];
1599
  /* Number of instruction operands.  */
1600
  int n_ops;
1601
  /* Pointer to instruction description.  */
1602
  struct i960_opcode *oP;
1603
  /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
1604
     or ".t").  */
1605
  int branch_predict;
1606
  /* Setting of branch-prediction bit(s) to be OR'd into instruction
1607
     opcode of CTRL/COBR format instructions.  */
1608
  long bp_bits;
1609
  /* Offset of last character in opcode mnemonic.  */
1610
  int n;
1611
  const char *bp_error_msg = _("branch prediction invalid on this opcode");
1612
 
1613
  /* Parse instruction into opcode and operands.  */
1614
  memset (args, '\0', sizeof (args));
1615
 
1616
  n_ops = i_scan (textP, args);
1617
 
1618
  if (n_ops == -1)
1619
    return;                     /* Error message already issued.  */
1620
 
1621
  /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction.  */
1622
  if (!strcmp (args[0], "ldconst"))
1623
    {
1624
      n_ops = parse_ldconst (args);
1625
      if (n_ops == -1)
1626
        return;
1627
    }
1628
 
1629
  /* Check for branch-prediction suffix on opcode mnemonic, strip it off.  */
1630
  n = strlen (args[0]) - 1;
1631
  branch_predict = 0;
1632
  bp_bits = 0;
1633
 
1634
  if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
1635
    {
1636
      /* We could check here to see if the target architecture
1637
         supports branch prediction, but why bother?  The bit will
1638
         just be ignored by processors that don't use it.  */
1639
      branch_predict = 1;
1640
      bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
1641
      args[0][n - 1] = '\0';     /* Strip suffix from opcode mnemonic */
1642
    }
1643
 
1644
  /* Look up opcode mnemonic in table and check number of operands.
1645
     Check that opcode is legal for the target architecture.  If all
1646
     looks good, assemble instruction.  */
1647
  oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
1648
  if (!oP || !targ_has_iclass (oP->iclass))
1649
    as_bad (_("invalid opcode, \"%s\"."), args[0]);
1650
  else if (n_ops != oP->num_ops)
1651
    as_bad (_("improper number of operands.  expecting %d, got %d"),
1652
            oP->num_ops, n_ops);
1653
  else
1654
    {
1655
      switch (oP->format)
1656
        {
1657
        case FBRA:
1658
        case CTRL:
1659
          ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
1660
          if (oP->format == FBRA)
1661
            /* Now generate a 'bno' to same arg */
1662
            ctrl_fmt (args[1], BNO | bp_bits, 1);
1663
          break;
1664
        case COBR:
1665
        case COJ:
1666
          cobr_fmt (args, oP->opcode | bp_bits, oP);
1667
          break;
1668
        case REG:
1669
          if (branch_predict)
1670
            as_warn (bp_error_msg);
1671
          reg_fmt (args, oP);
1672
          break;
1673
        case MEM1:
1674
          if (args[0][0] == 'c' && args[0][1] == 'a')
1675
            {
1676
              if (branch_predict)
1677
                as_warn (bp_error_msg);
1678
              mem_fmt (args, oP, 1);
1679
              break;
1680
            }
1681
        case MEM2:
1682
        case MEM4:
1683
        case MEM8:
1684
        case MEM12:
1685
        case MEM16:
1686
          if (branch_predict)
1687
            as_warn (bp_error_msg);
1688
          mem_fmt (args, oP, 0);
1689
          break;
1690
        case CALLJ:
1691
          if (branch_predict)
1692
            as_warn (bp_error_msg);
1693
          /* Output opcode & set up "fixup" (relocation); flag
1694
             relocation as 'callj' type.  */
1695
          know (oP->num_ops == 1);
1696
          get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
1697
          break;
1698
        default:
1699
          BAD_CASE (oP->format);
1700
          break;
1701
        }
1702
    }
1703
}
1704
 
1705
void
1706
md_number_to_chars (char *buf,
1707
                    valueT value,
1708
                    int n)
1709
{
1710
  number_to_chars_littleendian (buf, value, n);
1711
}
1712
 
1713
char *
1714
md_atof (int type, char *litP, int *sizeP)
1715
{
1716
  return ieee_md_atof (type, litP, sizeP, FALSE);
1717
}
1718
 
1719
static void
1720
md_number_to_imm (char *buf, long val, int n)
1721
{
1722
  md_number_to_chars (buf, val, n);
1723
}
1724
 
1725
static void
1726
md_number_to_field (char *instrP,               /* Pointer to instruction to be fixed.  */
1727
                    long val,                   /* Address fixup value.  */
1728
                    bit_fixS *bfixP)            /* Description of bit field to be fixed up.  */
1729
{
1730
  int numbits;                  /* Length of bit field to be fixed.  */
1731
  long instr;                   /* 32-bit instruction to be fixed-up.  */
1732
  long sign;                    /* 0 or -1, according to sign bit of 'val'.  */
1733
 
1734
  /* Convert instruction back to host byte order.  */
1735
  instr = md_chars_to_number (instrP, 4);
1736
 
1737
  /* Surprise! -- we stored the number of bits to be modified rather
1738
     than a pointer to a structure.  */
1739
  numbits = (int) (size_t) bfixP;
1740
  if (numbits == 1)
1741
    /* This is a no-op, stuck here by reloc_callj().  */
1742
    return;
1743
 
1744
  know ((numbits == 13) || (numbits == 24));
1745
 
1746
  /* Propagate sign bit of 'val' for the given number of bits.  Result
1747
     should be all 0 or all 1.  */
1748
  sign = val >> ((int) numbits - 1);
1749
  if (((val < 0) && (sign != -1))
1750
      || ((val > 0) && (sign != 0)))
1751
    as_bad (_("Fixup of %ld too large for field width of %d"),
1752
            val, numbits);
1753
  else
1754
    {
1755
      /* Put bit field into instruction and write back in target
1756
         * byte order.  */
1757
      val &= ~(-1 << (int) numbits);    /* Clear unused sign bits.  */
1758
      instr |= val;
1759
      md_number_to_chars (instrP, instr, 4);
1760
    }
1761
}
1762
 
1763
 
1764
/* md_parse_option
1765
        Invocation line includes a switch not recognized by the base assembler.
1766
        See if it's a processor-specific option.  For the 960, these are:
1767
 
1768
        -norelax:
1769
                Conditional branch instructions that require displacements
1770
                greater than 13 bits (or that have external targets) should
1771
                generate errors.  The default is to replace each such
1772
                instruction with the corresponding compare (or chkbit) and
1773
                branch instructions.  Note that the Intel "j" cobr directives
1774
                are ALWAYS "de-optimized" in this way when necessary,
1775
                regardless of the setting of this option.
1776
 
1777
        -b:
1778
                Add code to collect information about branches taken, for
1779
                later optimization of branch prediction bits by a separate
1780
                tool.  COBR and CNTL format instructions have branch
1781
                prediction bits (in the CX architecture);  if "BR" represents
1782
                an instruction in one of these classes, the following rep-
1783
                resents the code generated by the assembler:
1784
 
1785
                        call    <increment routine>
1786
                        .word   0        # pre-counter
1787
                Label:  BR
1788
                        call    <increment routine>
1789
                        .word   0        # post-counter
1790
 
1791
                A table of all such "Labels" is also generated.
1792
 
1793
        -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
1794
                Select the 80960 architecture.  Instructions or features not
1795
                supported by the selected architecture cause fatal errors.
1796
                The default is to generate code for any instruction or feature
1797
                that is supported by SOME version of the 960 (even if this
1798
                means mixing architectures!).  */
1799
 
1800
const char *md_shortopts = "A:b";
1801
struct option md_longopts[] =
1802
{
1803
#define OPTION_LINKRELAX (OPTION_MD_BASE)
1804
  {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
1805
  {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
1806
#define OPTION_NORELAX (OPTION_MD_BASE + 1)
1807
  {"norelax", no_argument, NULL, OPTION_NORELAX},
1808
  {"no-relax", no_argument, NULL, OPTION_NORELAX},
1809
  {NULL, no_argument, NULL, 0}
1810
};
1811
size_t md_longopts_size = sizeof (md_longopts);
1812
 
1813
struct tabentry
1814
{
1815
  char *flag;
1816
  int arch;
1817
};
1818
static const struct tabentry arch_tab[] =
1819
{
1820
  {"KA", ARCH_KA},
1821
  {"KB", ARCH_KB},
1822
  {"SA", ARCH_KA},              /* Synonym for KA.  */
1823
  {"SB", ARCH_KB},              /* Synonym for KB.  */
1824
  {"KC", ARCH_MC},              /* Synonym for MC.  */
1825
  {"MC", ARCH_MC},
1826
  {"CA", ARCH_CA},
1827
  {"JX", ARCH_JX},
1828
  {"HX", ARCH_HX},
1829
  {NULL, 0}
1830
};
1831
 
1832
int
1833
md_parse_option (int c, char *arg)
1834
{
1835
  switch (c)
1836
    {
1837
    case OPTION_LINKRELAX:
1838
      linkrelax = 1;
1839
      flag_keep_locals = 1;
1840
      break;
1841
 
1842
    case OPTION_NORELAX:
1843
      norelax = 1;
1844
      break;
1845
 
1846
    case 'b':
1847
      instrument_branches = 1;
1848
      break;
1849
 
1850
    case 'A':
1851
      {
1852
        const struct tabentry *tp;
1853
        char *p = arg;
1854
 
1855
        for (tp = arch_tab; tp->flag != NULL; tp++)
1856
          if (!strcmp (p, tp->flag))
1857
            break;
1858
 
1859
        if (tp->flag == NULL)
1860
          {
1861
            as_bad (_("invalid architecture %s"), p);
1862
            return 0;
1863
          }
1864
        else
1865
          architecture = tp->arch;
1866
      }
1867
      break;
1868
 
1869
    default:
1870
      return 0;
1871
    }
1872
 
1873
  return 1;
1874
}
1875
 
1876
void
1877
md_show_usage (FILE *stream)
1878
{
1879
  int i;
1880
 
1881
  fprintf (stream, _("I960 options:\n"));
1882
  for (i = 0; arch_tab[i].flag; i++)
1883
    fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
1884
  fprintf (stream, _("\n\
1885
                        specify variant of 960 architecture\n\
1886
-b                      add code to collect statistics about branches taken\n\
1887
-link-relax             preserve individual alignment directives so linker\n\
1888
                        can do relaxing (b.out format only)\n\
1889
-no-relax               don't alter compare-and-branch instructions for\n\
1890
                        long displacements\n"));
1891
}
1892
 
1893
/* relax_cobr:
1894
   Replace cobr instruction in a code fragment with equivalent branch and
1895
   compare instructions, so it can reach beyond a 13-bit displacement.
1896
   Set up an address fix/relocation for the new branch instruction.  */
1897
 
1898
/* This "conditional jump" table maps cobr instructions into
1899
   equivalent compare and branch opcodes.  */
1900
 
1901
static const
1902
struct
1903
{
1904
  long compare;
1905
  long branch;
1906
}
1907
 
1908
coj[] =
1909
{                               /* COBR OPCODE: */
1910
  { CHKBIT, BNO },              /*      0x30 - bbc */
1911
  { CMPO, BG },                 /*      0x31 - cmpobg */
1912
  { CMPO, BE },                 /*      0x32 - cmpobe */
1913
  { CMPO, BGE },                /*      0x33 - cmpobge */
1914
  { CMPO, BL },                 /*      0x34 - cmpobl */
1915
  { CMPO, BNE },                /*      0x35 - cmpobne */
1916
  { CMPO, BLE },                /*      0x36 - cmpoble */
1917
  { CHKBIT, BO },               /*      0x37 - bbs */
1918
  { CMPI, BNO },                /*      0x38 - cmpibno */
1919
  { CMPI, BG },                 /*      0x39 - cmpibg */
1920
  { CMPI, BE },                 /*      0x3a - cmpibe */
1921
  { CMPI, BGE },                /*      0x3b - cmpibge */
1922
  { CMPI, BL },                 /*      0x3c - cmpibl */
1923
  { CMPI, BNE },                /*      0x3d - cmpibne */
1924
  { CMPI, BLE },                /*      0x3e - cmpible */
1925
  { CMPI, BO },                 /*      0x3f - cmpibo */
1926
};
1927
 
1928
static void
1929
relax_cobr (fragS *fragP)       /* fragP->fr_opcode is assumed to point to
1930
                                   the cobr instruction, which comes at the
1931
                                   end of the code fragment.  */
1932
{
1933
  int opcode, src1, src2, m1, s2;
1934
  /* Bit fields from cobr instruction.  */
1935
  long bp_bits;                 /* Branch prediction bits from cobr instruction.  */
1936
  long instr;                   /* A single i960 instruction.  */
1937
  /* ->instruction to be replaced.  */
1938
  char *iP;
1939
  fixS *fixP;                   /* Relocation that can be done at assembly time.  */
1940
 
1941
  /* Pick up & parse cobr instruction.  */
1942
  iP = fragP->fr_opcode;
1943
  instr = md_chars_to_number (iP, 4);
1944
  opcode = ((instr >> 24) & 0xff) - 0x30;       /* "-0x30" for table index.  */
1945
  src1 = (instr >> 19) & 0x1f;
1946
  m1 = (instr >> 13) & 1;
1947
  s2 = instr & 1;
1948
  src2 = (instr >> 14) & 0x1f;
1949
  bp_bits = instr & BP_MASK;
1950
 
1951
  /* Generate and output compare instruction.  */
1952
  instr = coj[opcode].compare
1953
    | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
1954
  md_number_to_chars (iP, instr, 4);
1955
 
1956
  /* Output branch instruction.  */
1957
  md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
1958
 
1959
  /* Set up address fixup/relocation.  */
1960
  fixP = fix_new (fragP,
1961
                  iP + 4 - fragP->fr_literal,
1962
                  4,
1963
                  fragP->fr_symbol,
1964
                  fragP->fr_offset,
1965
                  1,
1966
                  NO_RELOC);
1967
 
1968
  fixP->fx_bit_fixP = (bit_fixS *) 24;  /* Store size of bit field.  */
1969
 
1970
  fragP->fr_fix += 4;
1971
  frag_wane (fragP);
1972
}
1973
 
1974
/* md_convert_frag:
1975
 
1976
   Called by base assembler after address relaxation is finished:  modify
1977
   variable fragments according to how much relaxation was done.
1978
 
1979
   If the fragment substate is still 1, a 13-bit displacement was enough
1980
   to reach the symbol in question.  Set up an address fixup, but otherwise
1981
   leave the cobr instruction alone.
1982
 
1983
   If the fragment substate is 2, a 13-bit displacement was not enough.
1984
   Replace the cobr with a two instructions (a compare and a branch).  */
1985
 
1986
void
1987
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
1988
                 segT sec ATTRIBUTE_UNUSED,
1989
                 fragS *fragP)
1990
{
1991
  /* Structure describing needed address fix.  */
1992
  fixS *fixP;
1993
 
1994
  switch (fragP->fr_subtype)
1995
    {
1996
    case 1:
1997
      /* Leave single cobr instruction.  */
1998
      fixP = fix_new (fragP,
1999
                      fragP->fr_opcode - fragP->fr_literal,
2000
                      4,
2001
                      fragP->fr_symbol,
2002
                      fragP->fr_offset,
2003
                      1,
2004
                      NO_RELOC);
2005
 
2006
      fixP->fx_bit_fixP = (bit_fixS *) 13;      /* Size of bit field.  */
2007
      break;
2008
    case 2:
2009
      /* Replace cobr with compare/branch instructions.  */
2010
      relax_cobr (fragP);
2011
      break;
2012
    default:
2013
      BAD_CASE (fragP->fr_subtype);
2014
      break;
2015
    }
2016
}
2017
 
2018
/* md_estimate_size_before_relax:  How much does it look like *fragP will grow?
2019
 
2020
   Called by base assembler just before address relaxation.
2021
   Return the amount by which the fragment will grow.
2022
 
2023
   Any symbol that is now undefined will not become defined; cobr's
2024
   based on undefined symbols will have to be replaced with a compare
2025
   instruction and a branch instruction, and the code fragment will grow
2026
   by 4 bytes.  */
2027
 
2028
int
2029
md_estimate_size_before_relax (fragS *fragP, segT segment_type)
2030
{
2031
  /* If symbol is undefined in this segment, go to "relaxed" state
2032
     (compare and branch instructions instead of cobr) right now.  */
2033
  if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
2034
    {
2035
      relax_cobr (fragP);
2036
      return 4;
2037
    }
2038
 
2039
  return md_relax_table[fragP->fr_subtype].rlx_length;
2040
}
2041
 
2042
#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2043
 
2044
/* md_ri_to_chars:
2045
   This routine exists in order to overcome machine byte-order problems
2046
   when dealing with bit-field entries in the relocation_info struct.
2047
 
2048
   But relocation info will be used on the host machine only (only
2049
   executable code is actually downloaded to the i80960).  Therefore,
2050
   we leave it in host byte order.  */
2051
 
2052
static void
2053
md_ri_to_chars (char *where, struct relocation_info *ri)
2054
{
2055
  host_number_to_chars (where, ri->r_address, 4);
2056
  host_number_to_chars (where + 4, ri->r_index, 3);
2057
#if WORDS_BIGENDIAN
2058
  where[7] = (ri->r_pcrel << 7
2059
              | ri->r_length << 5
2060
              | ri->r_extern << 4
2061
              | ri->r_bsr << 3
2062
              | ri->r_disp << 2
2063
              | ri->r_callj << 1
2064
              | ri->nuthin << 0);
2065
#else
2066
  where[7] = (ri->r_pcrel << 0
2067
              | ri->r_length << 1
2068
              | ri->r_extern << 3
2069
              | ri->r_bsr << 4
2070
              | ri->r_disp << 5
2071
              | ri->r_callj << 6
2072
              | ri->nuthin << 7);
2073
#endif
2074
}
2075
 
2076
#endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */
2077
 
2078
 
2079
/* brtab_emit:  generate the fetch-prediction branch table.
2080
 
2081
   See the comments above the declaration of 'br_cnt' for details on
2082
   branch-prediction instrumentation.
2083
 
2084
   The code emitted here would be functionally equivalent to the following
2085
   example assembler source.
2086
 
2087
                        .data
2088
                        .align  2
2089
           BR_TAB_NAME:
2090
                        .word   0                # link to next table
2091
                        .word   3               # length of table
2092
                        .word   LBRANCH0        # 1st entry in table proper
2093
                        .word   LBRANCH1
2094
                        .word   LBRANCH2  */
2095
 
2096
void
2097
brtab_emit (void)
2098
{
2099
  int i;
2100
  char buf[20];
2101
  /* Where the binary was output to.  */
2102
  char *p;
2103
  /* Pointer to description of deferred address fixup.  */
2104
  fixS *fixP;
2105
 
2106
  if (!instrument_branches)
2107
    return;
2108
 
2109
  subseg_set (data_section, 0);  /*      .data */
2110
  frag_align (2, 0, 0);           /*      .align 2 */
2111
  record_alignment (now_seg, 2);
2112
  colon (BR_TAB_NAME);          /* BR_TAB_NAME: */
2113
  emit (0);                      /*      .word 0 #link to next table */
2114
  emit (br_cnt);                /*      .word n #length of table */
2115
 
2116
  for (i = 0; i < br_cnt; i++)
2117
    {
2118
      sprintf (buf, "%s%d", BR_LABEL_BASE, i);
2119
      p = emit (0);
2120
      fixP = fix_new (frag_now,
2121
                      p - frag_now->fr_literal,
2122
                      4, symbol_find (buf), 0, 0, NO_RELOC);
2123
    }
2124
}
2125
 
2126
/* s_leafproc:  process .leafproc pseudo-op
2127
 
2128
        .leafproc takes two arguments, the second one is optional:
2129
                arg[1]: name of 'call' entry point to leaf procedure
2130
                arg[2]: name of 'bal' entry point to leaf procedure
2131
 
2132
        If the two arguments are identical, or if the second one is missing,
2133
        the first argument is taken to be the 'bal' entry point.
2134
 
2135
        If there are 2 distinct arguments, we must make sure that the 'bal'
2136
        entry point immediately follows the 'call' entry point in the linked
2137
        list of symbols.  */
2138
 
2139
static void
2140
s_leafproc (int n_ops,          /* Number of operands.  */
2141
            char *args[])       /* args[1]->1st operand, args[2]->2nd operand.  */
2142
{
2143
  symbolS *callP;               /* Pointer to leafproc 'call' entry point symbol.  */
2144
  symbolS *balP;                /* Pointer to leafproc 'bal' entry point symbol.  */
2145
 
2146
  if ((n_ops != 1) && (n_ops != 2))
2147
    {
2148
      as_bad (_("should have 1 or 2 operands"));
2149
      return;
2150
    }
2151
 
2152
  /* Find or create symbol for 'call' entry point.  */
2153
  callP = symbol_find_or_make (args[1]);
2154
 
2155
  if (TC_S_IS_CALLNAME (callP))
2156
    as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
2157
 
2158
  /* If that was the only argument, use it as the 'bal' entry point.
2159
     Otherwise, mark it as the 'call' entry point and find or create
2160
     another symbol for the 'bal' entry point.  */
2161
  if ((n_ops == 1) || !strcmp (args[1], args[2]))
2162
    {
2163
      TC_S_FORCE_TO_BALNAME (callP);
2164
    }
2165
  else
2166
    {
2167
      TC_S_FORCE_TO_CALLNAME (callP);
2168
 
2169
      balP = symbol_find_or_make (args[2]);
2170
      if (TC_S_IS_CALLNAME (balP))
2171
        as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
2172
 
2173
      TC_S_FORCE_TO_BALNAME (balP);
2174
 
2175
#ifndef OBJ_ELF
2176
      tc_set_bal_of_call (callP, balP);
2177
#endif
2178
    }
2179
}
2180
 
2181
/* s_sysproc: process .sysproc pseudo-op
2182
 
2183
   .sysproc takes two arguments:
2184
     arg[1]: name of entry point to system procedure
2185
     arg[2]: 'entry_num' (index) of system procedure in the range
2186
     [0,31] inclusive.
2187
 
2188
   For [ab].out, we store the 'entrynum' in the 'n_other' field of
2189
   the symbol.  Since that entry is normally 0, we bias 'entrynum'
2190
   by adding 1 to it.  It must be unbiased before it is used.  */
2191
 
2192
static void
2193
s_sysproc (int n_ops,           /* Number of operands.  */
2194
           char *args[])        /* args[1]->1st operand, args[2]->2nd operand.  */
2195
{
2196
  expressionS exp;
2197
  symbolS *symP;
2198
 
2199
  if (n_ops != 2)
2200
    {
2201
      as_bad (_("should have two operands"));
2202
      return;
2203
    }
2204
 
2205
  /* Parse "entry_num" argument and check it for validity.  */
2206
  parse_expr (args[2], &exp);
2207
  if (exp.X_op != O_constant
2208
      || (offs (exp) < 0)
2209
      || (offs (exp) > 31))
2210
    {
2211
      as_bad (_("'entry_num' must be absolute number in [0,31]"));
2212
      return;
2213
    }
2214
 
2215
  /* Find/make symbol and stick entry number (biased by +1) into it.  */
2216
  symP = symbol_find_or_make (args[1]);
2217
 
2218
  if (TC_S_IS_SYSPROC (symP))
2219
    as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
2220
 
2221
  TC_S_SET_SYSPROC (symP, offs (exp));  /* Encode entry number.  */
2222
  TC_S_FORCE_TO_SYSPROC (symP);
2223
}
2224
 
2225
/* parse_po:    parse machine-dependent pseudo-op
2226
 
2227
   This is a top-level routine for machine-dependent pseudo-ops.  It slurps
2228
   up the rest of the input line, breaks out the individual arguments,
2229
   and dispatches them to the correct handler.  */
2230
 
2231
static void
2232
parse_po (int po_num)   /* Pseudo-op number:  currently S_LEAFPROC or S_SYSPROC.  */
2233
{
2234
  /* Pointers operands, with no embedded whitespace.
2235
     arg[0] unused, arg[1-3]->operands.  */
2236
  char *args[4];
2237
  int n_ops;                    /* Number of operands.  */
2238
  char *p;                      /* Pointer to beginning of unparsed argument string.  */
2239
  char eol;                     /* Character that indicated end of line.  */
2240
 
2241
  extern char is_end_of_line[];
2242
 
2243
  /* Advance input pointer to end of line.  */
2244
  p = input_line_pointer;
2245
  while (!is_end_of_line[(unsigned char) *input_line_pointer])
2246
    input_line_pointer++;
2247
 
2248
  eol = *input_line_pointer;    /* Save end-of-line char.  */
2249
  *input_line_pointer = '\0';   /* Terminate argument list.  */
2250
 
2251
  /* Parse out operands.  */
2252
  n_ops = get_args (p, args);
2253
  if (n_ops == -1)
2254
    return;
2255
 
2256
  /* Dispatch to correct handler.  */
2257
  switch (po_num)
2258
    {
2259
    case S_SYSPROC:
2260
      s_sysproc (n_ops, args);
2261
      break;
2262
    case S_LEAFPROC:
2263
      s_leafproc (n_ops, args);
2264
      break;
2265
    default:
2266
      BAD_CASE (po_num);
2267
      break;
2268
    }
2269
 
2270
  /* Restore eol, so line numbers get updated correctly.  Base
2271
     assembler assumes we leave input pointer pointing at char
2272
     following the eol.  */
2273
  *input_line_pointer++ = eol;
2274
}
2275
 
2276
/* reloc_callj: Relocate a 'callj' instruction
2277
 
2278
        This is a "non-(GNU)-standard" machine-dependent hook.  The base
2279
        assembler calls it when it decides it can relocate an address at
2280
        assembly time instead of emitting a relocation directive.
2281
 
2282
        Check to see if the relocation involves a 'callj' instruction to a:
2283
            sysproc:    Replace the default 'call' instruction with a 'calls'
2284
            leafproc:   Replace the default 'call' instruction with a 'bal'.
2285
            other proc: Do nothing.
2286
 
2287
        See b.out.h for details on the 'n_other' field in a symbol structure.
2288
 
2289
   IMPORTANT!:
2290
        Assumes the caller has already figured out, in the case of a leafproc,
2291
        to use the 'bal' entry point, and has substituted that symbol into the
2292
        passed fixup structure.  */
2293
 
2294
int
2295
reloc_callj (fixS *fixP)  /* Relocation that can be done at assembly time.  */
2296
{
2297
  /* Points to the binary for the instruction being relocated.  */
2298
  char *where;
2299
 
2300
  if (!fixP->fx_tcbit)
2301
    /* This wasn't a callj instruction in the first place.  */
2302
    return 0;
2303
 
2304
  where = fixP->fx_frag->fr_literal + fixP->fx_where;
2305
 
2306
  if (TC_S_IS_SYSPROC (fixP->fx_addsy))
2307
    {
2308
      /* Symbol is a .sysproc: replace 'call' with 'calls'.  System
2309
         procedure number is (other-1).  */
2310
      md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
2311
 
2312
      /* Nothing else needs to be done for this instruction.  Make
2313
         sure 'md_number_to_field()' will perform a no-op.  */
2314
      fixP->fx_bit_fixP = (bit_fixS *) 1;
2315
    }
2316
  else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
2317
    {
2318
      /* Should not happen: see block comment above.  */
2319
      as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
2320
    }
2321
  else if (TC_S_IS_BALNAME (fixP->fx_addsy))
2322
    {
2323
      /* Replace 'call' with 'bal'; both instructions have the same
2324
         format, so calling code should complete relocation as if
2325
         nothing happened here.  */
2326
      md_number_to_chars (where, BAL, 4);
2327
    }
2328
  else if (TC_S_IS_BADPROC (fixP->fx_addsy))
2329
    as_bad (_("Looks like a proc, but can't tell what kind.\n"));
2330
 
2331
  /* Otherwise Symbol is neither a sysproc nor a leafproc.  */
2332
  return 0;
2333
}
2334
 
2335
/* Handle the MRI .endian pseudo-op.  */
2336
 
2337
static void
2338
s_endian (int ignore ATTRIBUTE_UNUSED)
2339
{
2340
  char *name;
2341
  char c;
2342
 
2343
  name = input_line_pointer;
2344
  c = get_symbol_end ();
2345
  if (strcasecmp (name, "little") == 0)
2346
    ;
2347
  else if (strcasecmp (name, "big") == 0)
2348
    as_bad (_("big endian mode is not supported"));
2349
  else
2350
    as_warn (_("ignoring unrecognized .endian type `%s'"), name);
2351
 
2352
  *input_line_pointer = c;
2353
 
2354
  demand_empty_rest_of_line ();
2355
}
2356
 
2357
/* We have no need to default values of symbols.  */
2358
 
2359
symbolS *
2360
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
2361
{
2362
  return 0;
2363
}
2364
 
2365
/* Exactly what point is a PC-relative offset relative TO?
2366
   On the i960, they're relative to the address of the instruction,
2367
   which we have set up as the address of the fixup too.  */
2368
long
2369
md_pcrel_from (fixS *fixP)
2370
{
2371
  return fixP->fx_where + fixP->fx_frag->fr_address;
2372
}
2373
 
2374
void
2375
md_apply_fix (fixS *fixP,
2376
               valueT *valP,
2377
               segT seg ATTRIBUTE_UNUSED)
2378
{
2379
  long val = *valP;
2380
  char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2381
 
2382
  if (!fixP->fx_bit_fixP)
2383
    {
2384
      md_number_to_imm (place, val, fixP->fx_size);
2385
    }
2386
  else if ((int) (size_t) fixP->fx_bit_fixP == 13
2387
           && fixP->fx_addsy != NULL
2388
           && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
2389
    {
2390
      /* This is a COBR instruction.  They have only a
2391
         13-bit displacement and are only to be used
2392
         for local branches: flag as error, don't generate
2393
         relocation.  */
2394
      as_bad_where (fixP->fx_file, fixP->fx_line,
2395
                    _("can't use COBR format with external label"));
2396
      fixP->fx_addsy = NULL;
2397
    }
2398
  else
2399
    md_number_to_field (place, val, fixP->fx_bit_fixP);
2400
 
2401
  if (fixP->fx_addsy == NULL)
2402
    fixP->fx_done = 1;
2403
}
2404
 
2405
#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2406
void
2407
tc_bout_fix_to_chars (char *where,
2408
                      fixS *fixP,
2409
                      relax_addressT segment_address_in_file)
2410
{
2411
  static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
2412
  struct relocation_info ri;
2413
  symbolS *symbolP;
2414
 
2415
  memset ((char *) &ri, '\0', sizeof (ri));
2416
  symbolP = fixP->fx_addsy;
2417
  know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2418
  ri.r_bsr = fixP->fx_bsr;      /*SAC LD RELAX HACK */
2419
  /* These two 'cuz of NS32K */
2420
  ri.r_callj = fixP->fx_tcbit;
2421
  if (fixP->fx_bit_fixP)
2422
    ri.r_length = 2;
2423
  else
2424
    ri.r_length = nbytes_r_length[fixP->fx_size];
2425
  ri.r_pcrel = fixP->fx_pcrel;
2426
  ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2427
 
2428
  if (fixP->fx_r_type != NO_RELOC)
2429
    {
2430
      switch (fixP->fx_r_type)
2431
        {
2432
        case rs_align:
2433
          ri.r_index = -2;
2434
          ri.r_pcrel = 1;
2435
          ri.r_length = fixP->fx_size - 1;
2436
          break;
2437
        case rs_org:
2438
          ri.r_index = -2;
2439
          ri.r_pcrel = 0;
2440
          break;
2441
        case rs_fill:
2442
          ri.r_index = -1;
2443
          break;
2444
        default:
2445
          abort ();
2446
        }
2447
      ri.r_extern = 0;
2448
    }
2449
  else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr)
2450
    {
2451
      ri.r_extern = 1;
2452
      ri.r_index = symbolP->sy_number;
2453
    }
2454
  else
2455
    {
2456
      ri.r_extern = 0;
2457
      ri.r_index = S_GET_TYPE (symbolP);
2458
    }
2459
 
2460
  /* Output the relocation information in machine-dependent form.  */
2461
  md_ri_to_chars (where, &ri);
2462
}
2463
 
2464
#endif /* OBJ_AOUT or OBJ_BOUT */
2465
 
2466
/* Align an address by rounding it up to the specified boundary.  */
2467
 
2468
valueT
2469
md_section_align (segT seg,
2470
                  valueT addr)          /* Address to be rounded up.  */
2471
{
2472
  int align;
2473
 
2474
  align = bfd_get_section_alignment (stdoutput, seg);
2475
  return (addr + (1 << align) - 1) & (-1 << align);
2476
}
2477
 
2478
extern int coff_flags;
2479
 
2480
/* For aout or bout, the bal immediately follows the call.
2481
 
2482
   For coff, we cheat and store a pointer to the bal symbol in the
2483
   second aux entry of the call.  */
2484
 
2485
#undef OBJ_ABOUT
2486
#ifdef OBJ_AOUT
2487
#define OBJ_ABOUT
2488
#endif
2489
#ifdef OBJ_BOUT
2490
#define OBJ_ABOUT
2491
#endif
2492
 
2493
void
2494
tc_set_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED,
2495
                    symbolS *balP ATTRIBUTE_UNUSED)
2496
{
2497
  know (TC_S_IS_CALLNAME (callP));
2498
  know (TC_S_IS_BALNAME (balP));
2499
 
2500
#ifdef OBJ_COFF
2501
 
2502
  callP->sy_tc = balP;
2503
  S_SET_NUMBER_AUXILIARY (callP, 2);
2504
 
2505
#else /* ! OBJ_COFF */
2506
#ifdef OBJ_ABOUT
2507
 
2508
  /* If the 'bal' entry doesn't immediately follow the 'call'
2509
     symbol, unlink it from the symbol list and re-insert it.  */
2510
  if (symbol_next (callP) != balP)
2511
    {
2512
      symbol_remove (balP, &symbol_rootP, &symbol_lastP);
2513
      symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
2514
    }                           /* if not in order */
2515
 
2516
#else /* ! OBJ_ABOUT */
2517
  as_fatal ("Only supported for a.out, b.out, or COFF");
2518
#endif /* ! OBJ_ABOUT */
2519
#endif /* ! OBJ_COFF */
2520
}
2521
 
2522
symbolS *
2523
tc_get_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED)
2524
{
2525
  symbolS *retval;
2526
 
2527
  know (TC_S_IS_CALLNAME (callP));
2528
 
2529
#ifdef OBJ_COFF
2530
  retval = callP->sy_tc;
2531
#else
2532
#ifdef OBJ_ABOUT
2533
  retval = symbol_next (callP);
2534
#else
2535
  as_fatal ("Only supported for a.out, b.out, or COFF");
2536
#endif /* ! OBJ_ABOUT */
2537
#endif /* ! OBJ_COFF */
2538
 
2539
  know (TC_S_IS_BALNAME (retval));
2540
  return retval;
2541
}
2542
 
2543
#ifdef OBJ_COFF
2544
void
2545
tc_coff_symbol_emit_hook (symbolS *symbolP ATTRIBUTE_UNUSED)
2546
{
2547
  if (TC_S_IS_CALLNAME (symbolP))
2548
    {
2549
      symbolS *balP = tc_get_bal_of_call (symbolP);
2550
 
2551
      symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
2552
      if (S_GET_STORAGE_CLASS (symbolP) == C_EXT)
2553
        S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT);
2554
      else
2555
        S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT);
2556
      S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
2557
      /* Fix up the bal symbol.  */
2558
      S_SET_STORAGE_CLASS (balP, C_LABEL);
2559
    }
2560
}
2561
#endif /* OBJ_COFF */
2562
 
2563
void
2564
i960_handle_align (fragS *fragp ATTRIBUTE_UNUSED)
2565
{
2566
  if (!linkrelax)
2567
    return;
2568
 
2569
#ifndef OBJ_BOUT
2570
  as_bad (_("option --link-relax is only supported in b.out format"));
2571
  linkrelax = 0;
2572
  return;
2573
#else
2574
 
2575
  /* The text section "ends" with another alignment reloc, to which we
2576
     aren't adding padding.  */
2577
  if (fragp->fr_next == text_last_frag
2578
      || fragp->fr_next == data_last_frag)
2579
    return;
2580
 
2581
  /* alignment directive */
2582
  fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
2583
           (int) fragp->fr_type);
2584
#endif /* OBJ_BOUT */
2585
}
2586
 
2587
int
2588
i960_validate_fix (fixS *fixP, segT this_segment_type ATTRIBUTE_UNUSED)
2589
{
2590
  if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy))
2591
    {
2592
      /* Relocation should be done via the associated 'bal'
2593
         entry point symbol.  */
2594
      if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy)))
2595
        {
2596
          as_bad_where (fixP->fx_file, fixP->fx_line,
2597
                        _("No 'bal' entry point for leafproc %s"),
2598
                        S_GET_NAME (fixP->fx_addsy));
2599
          return 0;
2600
        }
2601
      fixP->fx_addsy = tc_get_bal_of_call (fixP->fx_addsy);
2602
    }
2603
 
2604
  return 1;
2605
}
2606
 
2607
/* From cgen.c:  */
2608
 
2609
static short
2610
tc_bfd_fix2rtype (fixS *fixP)
2611
{
2612
  if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
2613
    return BFD_RELOC_32;
2614
 
2615
  if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
2616
    return BFD_RELOC_24_PCREL;
2617
 
2618
  abort ();
2619
  return 0;
2620
}
2621
 
2622
/* Translate internal representation of relocation info to BFD target
2623
   format.
2624
 
2625
   FIXME: To what extent can we get all relevant targets to use this?  */
2626
 
2627
arelent *
2628
tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
2629
{
2630
  arelent * reloc;
2631
 
2632
  reloc = xmalloc (sizeof (arelent));
2633
 
2634
  /* HACK: Is this right?  */
2635
  fixP->fx_r_type = tc_bfd_fix2rtype (fixP);
2636
 
2637
  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
2638
  if (reloc->howto == NULL)
2639
    {
2640
      as_bad_where (fixP->fx_file, fixP->fx_line,
2641
                    "internal error: can't export reloc type %d (`%s')",
2642
                    fixP->fx_r_type,
2643
                    bfd_get_reloc_code_name (fixP->fx_r_type));
2644
      return NULL;
2645
    }
2646
 
2647
  assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
2648
 
2649
  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
2650
  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
2651
  reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
2652
  reloc->addend = fixP->fx_addnumber;
2653
 
2654
  return reloc;
2655
}
2656
 
2657
/* end from cgen.c */
2658
 
2659
const pseudo_typeS md_pseudo_table[] =
2660
{
2661
  {"bss", s_lcomm, 1},
2662
  {"endian", s_endian, 0},
2663
  {"extended", float_cons, 't'},
2664
  {"leafproc", parse_po, S_LEAFPROC},
2665
  {"sysproc", parse_po, S_SYSPROC},
2666
 
2667
  {"word", cons, 4},
2668
  {"quad", cons, 16},
2669
 
2670
  {0, 0, 0}
2671
};

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.