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[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [config/] [tc-m68k.c] - Blame information for rev 856

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1 38 julius
/* tc-m68k.c -- Assemble for the m68k family
2
   Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3
   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
 
5
   This file is part of GAS, the GNU Assembler.
6
 
7
   GAS is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   GAS is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GAS; see the file COPYING.  If not, write to the Free
19
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20
   02110-1301, USA.  */
21
 
22
#include "as.h"
23
#include "safe-ctype.h"
24
#include "obstack.h"
25
#include "subsegs.h"
26
#include "dwarf2dbg.h"
27
#include "dw2gencfi.h"
28
 
29
#include "opcode/m68k.h"
30
#include "m68k-parse.h"
31
 
32
#if defined (OBJ_ELF)
33
#include "elf/m68k.h"
34
#endif
35
 
36
#ifdef M68KCOFF
37
#include "obj-coff.h"
38
#endif
39
 
40
/* This string holds the chars that always start a comment.  If the
41
   pre-processor is disabled, these aren't very useful.  The macro
42
   tc_comment_chars points to this.  We use this, rather than the
43
   usual comment_chars, so that the --bitwise-or option will work.  */
44
#if defined (TE_SVR4) || defined (TE_DELTA)
45
const char *m68k_comment_chars = "|#";
46
#else
47
const char *m68k_comment_chars = "|";
48
#endif
49
 
50
/* This array holds the chars that only start a comment at the beginning of
51
   a line.  If the line seems to have the form '# 123 filename'
52
   .line and .file directives will appear in the pre-processed output */
53
/* Note that input_file.c hand checks for '#' at the beginning of the
54
   first line of the input file.  This is because the compiler outputs
55
   #NO_APP at the beginning of its output.  */
56
/* Also note that comments like this one will always work.  */
57
const char line_comment_chars[] = "#*";
58
 
59
const char line_separator_chars[] = ";";
60
 
61
/* Chars that can be used to separate mant from exp in floating point nums.  */
62
const char EXP_CHARS[] = "eE";
63
 
64
/* Chars that mean this number is a floating point constant, as
65
   in "0f12.456" or "0d1.2345e12".  */
66
 
67
const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
 
69
/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70
   changed in read.c .  Ideally it shouldn't have to know about it at all,
71
   but nothing is ideal around here.  */
72
 
73
/* Are we trying to generate PIC code?  If so, absolute references
74
   ought to be made into linkage table references or pc-relative
75
   references.  Not implemented.  For ELF there are other means
76
   to denote pic relocations.  */
77
int flag_want_pic;
78
 
79
static int flag_short_refs;     /* -l option.  */
80
static int flag_long_jumps;     /* -S option.  */
81
static int flag_keep_pcrel;     /* --pcrel option.  */
82
 
83
#ifdef REGISTER_PREFIX_OPTIONAL
84
int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85
#else
86
int flag_reg_prefix_optional;
87
#endif
88
 
89
/* Whether --register-prefix-optional was used on the command line.  */
90
static int reg_prefix_optional_seen;
91
 
92
/* The floating point coprocessor to use by default.  */
93
static enum m68k_register m68k_float_copnum = COP1;
94
 
95
/* If this is non-zero, then references to number(%pc) will be taken
96
   to refer to number, rather than to %pc + number.  */
97
static int m68k_abspcadd;
98
 
99
/* If this is non-zero, then the quick forms of the move, add, and sub
100
   instructions are used when possible.  */
101
static int m68k_quick = 1;
102
 
103
/* If this is non-zero, then if the size is not specified for a base
104
   or outer displacement, the assembler assumes that the size should
105
   be 32 bits.  */
106
static int m68k_rel32 = 1;
107
 
108
/* This is non-zero if m68k_rel32 was set from the command line.  */
109
static int m68k_rel32_from_cmdline;
110
 
111
/* The default width to use for an index register when using a base
112
   displacement.  */
113
static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
 
115
/* We want to warn if any text labels are misaligned.  In order to get
116
   the right line number, we need to record the line number for each
117
   label.  */
118
struct label_line
119
{
120
  struct label_line *next;
121
  symbolS *label;
122
  char *file;
123
  unsigned int line;
124
  int text;
125
};
126
 
127
/* The list of labels.  */
128
 
129
static struct label_line *labels;
130
 
131
/* The current label.  */
132
 
133
static struct label_line *current_label;
134
 
135
/* Pointer to list holding the opcodes sorted by name.  */
136
static struct m68k_opcode const ** m68k_sorted_opcodes;
137
 
138
/* Its an arbitrary name:  This means I don't approve of it.
139
   See flames below.  */
140
static struct obstack robyn;
141
 
142
struct m68k_incant
143
  {
144
    const char *m_operands;
145
    unsigned long m_opcode;
146
    short m_opnum;
147
    short m_codenum;
148
    int m_arch;
149
    struct m68k_incant *m_next;
150
  };
151
 
152
#define getone(x)       ((((x)->m_opcode)>>16)&0xffff)
153
#define gettwo(x)       (((x)->m_opcode)&0xffff)
154
 
155
static const enum m68k_register m68000_ctrl[] = { 0 };
156
static const enum m68k_register m68010_ctrl[] = {
157
  SFC, DFC, USP, VBR,
158
 
159
};
160
static const enum m68k_register m68020_ctrl[] = {
161
  SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162
 
163
};
164
static const enum m68k_register m68040_ctrl[] = {
165
  SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166
  USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167
 
168
};
169
static const enum m68k_register m68060_ctrl[] = {
170
  SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171
  USP, VBR, URP, SRP, PCR,
172
 
173
};
174
static const enum m68k_register mcf_ctrl[] = {
175
  CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176
  RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177
 
178
};
179
static const enum m68k_register mcf51qe_ctrl[] = {
180
  VBR,
181
 
182
};
183
static const enum m68k_register mcf5206_ctrl[] = {
184
  CACR, ACR0, ACR1,  VBR, RAMBAR0, RAMBAR_ALT, MBAR,
185
 
186
};
187
static const enum m68k_register mcf5208_ctrl[] = {
188
  CACR, ACR0, ACR1, VBR,  RAMBAR, RAMBAR1,
189
 
190
};
191
static const enum m68k_register mcf5210a_ctrl[] = {
192
  VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
193
 
194
};
195
static const enum m68k_register mcf5213_ctrl[] = {
196
  VBR, RAMBAR, RAMBAR1, FLASHBAR,
197
 
198
};
199
static const enum m68k_register mcf5216_ctrl[] = {
200
  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
201
 
202
};
203
static const enum m68k_register mcf52223_ctrl[] = {
204
  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
205
 
206
};
207
static const enum m68k_register mcf52235_ctrl[] = {
208
  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
209
 
210
};
211
static const enum m68k_register mcf5225_ctrl[] = {
212
  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
213
 
214
};
215
static const enum m68k_register mcf5235_ctrl[] = {
216
  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
217
 
218
};
219
static const enum m68k_register mcf5249_ctrl[] = {
220
  VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
221
 
222
};
223
static const enum m68k_register mcf5250_ctrl[] = {
224
  VBR,
225
 
226
};
227
static const enum m68k_register mcf5253_ctrl[] = {
228
  VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
229
 
230
};
231
static const enum m68k_register mcf5271_ctrl[] = {
232
  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
233
 
234
};
235
static const enum m68k_register mcf5272_ctrl[] = {
236
  VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
237
 
238
};
239
static const enum m68k_register mcf5275_ctrl[] = {
240
  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
241
 
242
};
243
static const enum m68k_register mcf5282_ctrl[] = {
244
  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
245
 
246
};
247
static const enum m68k_register mcf5307_ctrl[] = {
248
  CACR, ACR0, ACR1,  VBR, RAMBAR0, RAMBAR_ALT, MBAR,
249
 
250
};
251
static const enum m68k_register mcf5329_ctrl[] = {
252
  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
253
 
254
};
255
static const enum m68k_register mcf5373_ctrl[] = {
256
  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
257
 
258
};
259
static const enum m68k_register mcfv4e_ctrl[] = {
260
  CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
261
  VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
262
  MBAR, SECMBAR,
263
  MPCR /* Multiprocessor Control register */,
264
  EDRAMBAR /* Embedded DRAM Base Address Register */,
265
  /* Permutation control registers.  */
266
  PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
267
  PCR3U0, PCR3L0, PCR3U1, PCR3L1,
268
  /* Legacy names */
269
  TC /* ASID */, BUSCR /* MMUBAR */,
270
  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
271
  MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
272
  ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
273
 
274
};
275
static const enum m68k_register mcf5407_ctrl[] = {
276
  CACR, ASID, ACR0, ACR1, ACR2, ACR3,
277
  VBR, PC, RAMBAR0, RAMBAR1, MBAR,
278
  /* Legacy names */
279
  TC /* ASID */,
280
  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
281
  MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
282
 
283
};
284
static const enum m68k_register mcf54455_ctrl[] = {
285
  CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
286
  VBR, PC, RAMBAR1, MBAR,
287
  /* Legacy names */
288
  TC /* ASID */, BUSCR /* MMUBAR */,
289
  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
290
  MBAR1 /* MBAR */,  RAMBAR /* RAMBAR1 */,
291
 
292
};
293
static const enum m68k_register mcf5475_ctrl[] = {
294
  CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
295
  VBR, PC, RAMBAR0, RAMBAR1, MBAR,
296
  /* Legacy names */
297
  TC /* ASID */, BUSCR /* MMUBAR */,
298
  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
299
  MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
300
 
301
};
302
static const enum m68k_register mcf5485_ctrl[] = {
303
  CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
304
  VBR, PC, RAMBAR0, RAMBAR1, MBAR,
305
  /* Legacy names */
306
  TC /* ASID */, BUSCR /* MMUBAR */,
307
  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
308
  MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
309
 
310
};
311
static const enum m68k_register fido_ctrl[] = {
312
  SFC, DFC, USP, VBR, CAC, MBO,
313
 
314
};
315
#define cpu32_ctrl m68010_ctrl
316
 
317
static const enum m68k_register *control_regs;
318
 
319
/* Internal form of a 68020 instruction.  */
320
struct m68k_it
321
{
322
  const char *error;
323
  const char *args;             /* List of opcode info.  */
324
  int numargs;
325
 
326
  int numo;                     /* Number of shorts in opcode.  */
327
  short opcode[11];
328
 
329
  struct m68k_op operands[6];
330
 
331
  int nexp;                     /* Number of exprs in use.  */
332
  struct m68k_exp exprs[4];
333
 
334
  int nfrag;                    /* Number of frags we have to produce.  */
335
  struct
336
    {
337
      int fragoff;              /* Where in the current opcode the frag ends.  */
338
      symbolS *fadd;
339
      offsetT foff;
340
      int fragty;
341
    }
342
  fragb[4];
343
 
344
  int nrel;                     /* Num of reloc strucs in use.  */
345
  struct
346
    {
347
      int n;
348
      expressionS exp;
349
      char wid;
350
      char pcrel;
351
      /* In a pc relative address the difference between the address
352
         of the offset and the address that the offset is relative
353
         to.  This depends on the addressing mode.  Basically this
354
         is the value to put in the offset field to address the
355
         first byte of the offset, without regarding the special
356
         significance of some values (in the branch instruction, for
357
         example).  */
358
      int pcrel_fix;
359
#ifdef OBJ_ELF
360
      /* Whether this expression needs special pic relocation, and if
361
         so, which.  */
362
      enum pic_relocation pic_reloc;
363
#endif
364
    }
365
  reloc[5];                     /* Five is enough???  */
366
};
367
 
368
#define cpu_of_arch(x)          ((x) & (m68000up | mcfisa_a | fido_a))
369
#define float_of_arch(x)        ((x) & mfloat)
370
#define mmu_of_arch(x)          ((x) & mmmu)
371
#define arch_coldfire_p(x)      ((x) & mcfisa_a)
372
#define arch_coldfire_fpu(x)    ((x) & cfloat)
373
 
374
/* Macros for determining if cpu supports a specific addressing mode.  */
375
#define HAVE_LONG_DISP(x)       \
376
        ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
377
#define HAVE_LONG_CALL(x)       \
378
        ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
379
#define HAVE_LONG_COND(x)       \
380
        ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
381
#define HAVE_LONG_BRANCH(x)     \
382
        ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
383
#define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
384
 
385
static struct m68k_it the_ins;  /* The instruction being assembled.  */
386
 
387
#define op(ex)          ((ex)->exp.X_op)
388
#define adds(ex)        ((ex)->exp.X_add_symbol)
389
#define subs(ex)        ((ex)->exp.X_op_symbol)
390
#define offs(ex)        ((ex)->exp.X_add_number)
391
 
392
/* Macros for adding things to the m68k_it struct.  */
393
#define addword(w)      (the_ins.opcode[the_ins.numo++] = (w))
394
 
395
/* Like addword, but goes BEFORE general operands.  */
396
 
397
static void
398
insop (int w, const struct m68k_incant *opcode)
399
{
400
  int z;
401
  for (z = the_ins.numo; z > opcode->m_codenum; --z)
402
    the_ins.opcode[z] = the_ins.opcode[z - 1];
403
  for (z = 0; z < the_ins.nrel; z++)
404
    the_ins.reloc[z].n += 2;
405
  for (z = 0; z < the_ins.nfrag; z++)
406
    the_ins.fragb[z].fragoff++;
407
  the_ins.opcode[opcode->m_codenum] = w;
408
  the_ins.numo++;
409
}
410
 
411
/* The numo+1 kludge is so we can hit the low order byte of the prev word.
412
   Blecch.  */
413
static void
414
add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
415
{
416
  the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
417
                                   ? the_ins.numo * 2 - 1
418
                                   : (width == 'b'
419
                                      ? the_ins.numo * 2 + 1
420
                                      : the_ins.numo * 2));
421
  the_ins.reloc[the_ins.nrel].exp = exp->exp;
422
  the_ins.reloc[the_ins.nrel].wid = width;
423
  the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
424
#ifdef OBJ_ELF
425
  the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
426
#endif
427
  the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
428
}
429
 
430
/* Cause an extra frag to be generated here, inserting up to 10 bytes
431
   (that value is chosen in the frag_var call in md_assemble).  TYPE
432
   is the subtype of the frag to be generated; its primary type is
433
   rs_machine_dependent.
434
 
435
   The TYPE parameter is also used by md_convert_frag_1 and
436
   md_estimate_size_before_relax.  The appropriate type of fixup will
437
   be emitted by md_convert_frag_1.
438
 
439
   ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET.  */
440
static void
441
add_frag (symbolS *add, offsetT off, int type)
442
{
443
  the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
444
  the_ins.fragb[the_ins.nfrag].fadd = add;
445
  the_ins.fragb[the_ins.nfrag].foff = off;
446
  the_ins.fragb[the_ins.nfrag++].fragty = type;
447
}
448
 
449
#define isvar(ex) \
450
  (op (ex) != O_constant && op (ex) != O_big)
451
 
452
static char *crack_operand (char *str, struct m68k_op *opP);
453
static int get_num (struct m68k_exp *exp, int ok);
454
static int reverse_16_bits (int in);
455
static int reverse_8_bits (int in);
456
static void install_gen_operand (int mode, int val);
457
static void install_operand (int mode, int val);
458
static void s_bss (int);
459
static void s_data1 (int);
460
static void s_data2 (int);
461
static void s_even (int);
462
static void s_proc (int);
463
static void s_chip (int);
464
static void s_fopt (int);
465
static void s_opt (int);
466
static void s_reg (int);
467
static void s_restore (int);
468
static void s_save (int);
469
static void s_mri_if (int);
470
static void s_mri_else (int);
471
static void s_mri_endi (int);
472
static void s_mri_break (int);
473
static void s_mri_next (int);
474
static void s_mri_for (int);
475
static void s_mri_endf (int);
476
static void s_mri_repeat (int);
477
static void s_mri_until (int);
478
static void s_mri_while (int);
479
static void s_mri_endw (int);
480
static void s_m68k_cpu (int);
481
static void s_m68k_arch (int);
482
 
483
struct m68k_cpu
484
{
485
  unsigned long arch;   /* Architecture features.  */
486
  const enum m68k_register *control_regs;       /* Control regs on chip */
487
  const char *name;     /* Name */
488
  int alias;            /* Alias for a cannonical name.  If 1, then
489
                           succeeds canonical name, if -1 then
490
                           succeeds canonical name, if <-1 ||>1 this is a
491
                           deprecated name, and the next/previous name
492
                           should be used. */
493
};
494
 
495
/* We hold flags for features explicitly enabled and explicitly
496
   disabled.  */
497
static int current_architecture;
498
static int not_current_architecture;
499
static const struct m68k_cpu *selected_arch;
500
static const struct m68k_cpu *selected_cpu;
501
static int initialized;
502
 
503
/* Architecture models.  */
504
static const struct m68k_cpu m68k_archs[] =
505
{
506
  {m68000,                                      m68000_ctrl, "68000", 0},
507
  {m68010,                                      m68010_ctrl, "68010", 0},
508
  {m68020|m68881|m68851,                        m68020_ctrl, "68020", 0},
509
  {m68030|m68881|m68851,                        m68020_ctrl, "68030", 0},
510
  {m68040,                                      m68040_ctrl, "68040", 0},
511
  {m68060,                                      m68060_ctrl, "68060", 0},
512
  {cpu32|m68881,                                cpu32_ctrl, "cpu32", 0},
513
  {fido_a,                                      fido_ctrl, "fidoa", 0},
514
  {mcfisa_a|mcfhwdiv,                           NULL, "isaa", 0},
515
  {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp,          NULL, "isaaplus", 0},
516
  {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp,           NULL, "isab", 0},
517
  {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp,           NULL, "isac", 0},
518
  {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp,    mcf_ctrl, "cfv4", 0},
519
  {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
520
  {0,0,NULL, 0}
521
};
522
 
523
/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
524
   for either.  */
525
static const struct m68k_cpu m68k_extensions[] =
526
{
527
  {m68851,                                      NULL, "68851", -1},
528
  {m68881,                                      NULL, "68881", -1},
529
  {m68881,                                      NULL, "68882", -1},
530
 
531
  {cfloat|m68881,                               NULL, "float", 0},
532
 
533
  {mcfhwdiv,                                    NULL, "div", 1},
534
  {mcfusp,                                      NULL, "usp", 1},
535
  {mcfmac,                                      NULL, "mac", 1},
536
  {mcfemac,                                     NULL, "emac", 1},
537
 
538
  {0,NULL,NULL, 0}
539
};
540
 
541
/* Processor list */
542
static const struct m68k_cpu m68k_cpus[] =
543
{
544
  {m68000,                                      m68000_ctrl, "68000", 0},
545
  {m68000,                                      m68000_ctrl, "68ec000", 1},
546
  {m68000,                                      m68000_ctrl, "68hc000", 1},
547
  {m68000,                                      m68000_ctrl, "68hc001", 1},
548
  {m68000,                                      m68000_ctrl, "68008", 1},
549
  {m68000,                                      m68000_ctrl, "68302", 1},
550
  {m68000,                                      m68000_ctrl, "68306", 1},
551
  {m68000,                                      m68000_ctrl, "68307", 1},
552
  {m68000,                                      m68000_ctrl, "68322", 1},
553
  {m68000,                                      m68000_ctrl, "68356", 1},
554
  {m68010,                                      m68010_ctrl, "68010", 0},
555
  {m68020|m68881|m68851,                        m68020_ctrl, "68020", 0},
556
  {m68020|m68881|m68851,                        m68020_ctrl, "68k", 1},
557
  {m68020|m68881|m68851,                        m68020_ctrl, "68ec020", 1},
558
  {m68030|m68881|m68851,                        m68020_ctrl, "68030", 0},
559
  {m68030|m68881|m68851,                        m68020_ctrl, "68ec030", 1},
560
  {m68040,                                      m68040_ctrl, "68040", 0},
561
  {m68040,                                      m68040_ctrl, "68ec040", 1},
562
  {m68060,                                      m68060_ctrl, "68060", 0},
563
  {m68060,                                      m68060_ctrl, "68ec060", 1},
564
 
565
  {cpu32|m68881,                                cpu32_ctrl, "cpu32",  0},
566
  {cpu32|m68881,                                cpu32_ctrl, "68330", 1},
567
  {cpu32|m68881,                                cpu32_ctrl, "68331", 1},
568
  {cpu32|m68881,                                cpu32_ctrl, "68332", 1},
569
  {cpu32|m68881,                                cpu32_ctrl, "68333", 1},
570
  {cpu32|m68881,                                cpu32_ctrl, "68334", 1},
571
  {cpu32|m68881,                                cpu32_ctrl, "68336", 1},
572
  {cpu32|m68881,                                cpu32_ctrl, "68340", 1},
573
  {cpu32|m68881,                                cpu32_ctrl, "68341", 1},
574
  {cpu32|m68881,                                cpu32_ctrl, "68349", 1},
575
  {cpu32|m68881,                                cpu32_ctrl, "68360", 1},
576
 
577
  {mcfisa_a|mcfisa_c|mcfusp,                    mcf51qe_ctrl, "51qe", 0},
578
 
579
  {mcfisa_a,                                    mcf_ctrl, "5200", 0},
580
  {mcfisa_a,                                    mcf_ctrl, "5202", 1},
581
  {mcfisa_a,                                    mcf_ctrl, "5204", 1},
582
  {mcfisa_a,                                    mcf5206_ctrl, "5206", 1},
583
 
584
  {mcfisa_a|mcfhwdiv|mcfmac,                    mcf5206_ctrl, "5206e", 0},
585
 
586
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5208_ctrl, "5207", -1},
587
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5208_ctrl, "5208", 0},
588
 
589
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5210a_ctrl, "5210a", 0},
590
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5210a_ctrl, "5211a", 1},
591
 
592
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5213_ctrl, "5211", -1},
593
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5213_ctrl, "5212", -1},
594
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5213_ctrl, "5213", 0},
595
 
596
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5216_ctrl, "5214", -1},
597
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5216_ctrl, "5216", 0},
598
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5216_ctrl, "521x", 2},
599
 
600
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf52223_ctrl, "52221", -1},
601
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf52223_ctrl, "52223", 0},
602
 
603
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52230", -1},
604
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52233", -1},
605
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52234", -1},
606
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52235", 0},
607
 
608
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5225_ctrl, "5224", -1},
609
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5225_ctrl, "5225", 0},
610
 
611
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5235_ctrl, "5232", -1},
612
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5235_ctrl, "5233", -1},
613
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5235_ctrl, "5234", -1},
614
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5235_ctrl, "5235", -1},
615
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5235_ctrl, "523x", 0},
616
 
617
  {mcfisa_a|mcfhwdiv|mcfemac,                   mcf5249_ctrl, "5249", 0},
618
  {mcfisa_a|mcfhwdiv|mcfemac,                   mcf5250_ctrl, "5250", 0},
619
  {mcfisa_a|mcfhwdiv|mcfemac,                   mcf5253_ctrl, "5253", 0},
620
 
621
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5271_ctrl, "5270", -1},
622
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5271_ctrl, "5271", 0},
623
 
624
  {mcfisa_a|mcfhwdiv|mcfmac,                    mcf5272_ctrl, "5272", 0},
625
 
626
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5275_ctrl, "5274", -1},
627
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5275_ctrl, "5275", 0},
628
 
629
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5282_ctrl, "5280", -1},
630
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5282_ctrl, "5281", -1},
631
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5282_ctrl, "5282", -1},
632
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5282_ctrl, "528x", 0},
633
 
634
  {mcfisa_a|mcfhwdiv|mcfmac,                    mcf5307_ctrl, "5307", 0},
635
 
636
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5329_ctrl, "5327", -1},
637
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5329_ctrl, "5328", -1},
638
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5329_ctrl, "5329", -1},
639
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5329_ctrl, "532x", 0},
640
 
641
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5373_ctrl, "5372", -1},
642
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5373_ctrl, "5373", -1},
643
  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf5373_ctrl, "537x", 0},
644
 
645
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac,           mcf5407_ctrl, "5407",0},
646
 
647
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54450", -1},
648
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54451", -1},
649
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54452", -1},
650
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54453", -1},
651
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54454", -1},
652
  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54455", 0},
653
 
654
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
655
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
656
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
657
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
658
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
659
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
660
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
661
 
662
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
663
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
664
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
665
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
666
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
667
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
668
  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
669
 
670
  {fido_a,                              fido_ctrl, "fidoa", 0},
671
  {fido_a,                              fido_ctrl, "fido", 1},
672
 
673
  {0,NULL,NULL, 0}
674
  };
675
 
676
static const struct m68k_cpu *m68k_lookup_cpu
677
(const char *, const struct m68k_cpu *, int, int *);
678
static int m68k_set_arch (const char *, int, int);
679
static int m68k_set_cpu (const char *, int, int);
680
static int m68k_set_extension (const char *, int, int);
681
static void m68k_init_arch (void);
682
 
683
/* This is the assembler relaxation table for m68k. m68k is a rich CISC
684
   architecture and we have a lot of relaxation modes.  */
685
 
686
/* Macros used in the relaxation code.  */
687
#define TAB(x,y)        (((x) << 2) + (y))
688
#define TABTYPE(x)      ((x) >> 2)
689
 
690
/* Relaxation states.  */
691
#define BYTE            0
692
#define SHORT           1
693
#define LONG            2
694
#define SZ_UNDEF        3
695
 
696
/* Here are all the relaxation modes we support.  First we can relax ordinary
697
   branches.  On 68020 and higher and on CPU32 all branch instructions take
698
   three forms, so on these CPUs all branches always remain as such.  When we
699
   have to expand to the LONG form on a 68000, though, we substitute an
700
   absolute jump instead.  This is a direct replacement for unconditional
701
   branches and a branch over a jump for conditional branches.  However, if the
702
   user requires PIC and disables this with --pcrel, we can only relax between
703
   BYTE and SHORT forms, punting if that isn't enough.  This gives us four
704
   different relaxation modes for branches:  */
705
 
706
#define BRANCHBWL       0        /* Branch byte, word, or long.  */
707
#define BRABSJUNC       1       /* Absolute jump for LONG, unconditional.  */
708
#define BRABSJCOND      2       /* Absolute jump for LONG, conditional.  */
709
#define BRANCHBW        3       /* Branch byte or word.  */
710
 
711
/* We also relax coprocessor branches and DBcc's.  All CPUs that support
712
   coprocessor branches support them in word and long forms, so we have only
713
   one relaxation mode for them.  DBcc's are word only on all CPUs.  We can
714
   relax them to the LONG form with a branch-around sequence.  This sequence
715
   can use a long branch (if available) or an absolute jump (if acceptable).
716
   This gives us two relaxation modes.  If long branches are not available and
717
   absolute jumps are not acceptable, we don't relax DBcc's.  */
718
 
719
#define FBRANCH         4       /* Coprocessor branch.  */
720
#define DBCCLBR         5       /* DBcc relaxable with a long branch.  */
721
#define DBCCABSJ        6       /* DBcc relaxable with an absolute jump.  */
722
 
723
/* That's all for instruction relaxation.  However, we also relax PC-relative
724
   operands.  Specifically, we have three operand relaxation modes.  On the
725
   68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
726
   on CPU32 they may be 16-bit or 32-bit.  For the latter we relax between the
727
   two.  Also PC+displacement+index operands in their simple form (with a non-
728
   suppressed index without memory indirection) are supported on all CPUs, but
729
   on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
730
   and on CPU32 we relax it to SHORT and LONG forms as well using the extended
731
   form of the PC+displacement+index operand.  Finally, some absolute operands
732
   can be relaxed down to 16-bit PC-relative.  */
733
 
734
#define PCREL1632       7       /* 16-bit or 32-bit PC-relative.  */
735
#define PCINDEX         8       /* PC + displacement + index. */
736
#define ABSTOPCREL      9       /* Absolute relax down to 16-bit PC-relative.  */
737
 
738
/* This relaxation is required for branches where there is no long
739
   branch and we are in pcrel mode.  We generate a bne/beq pair.  */
740
#define BRANCHBWPL      10      /* Branch byte, word or pair of longs
741
                                   */
742
 
743
/* Note that calls to frag_var need to specify the maximum expansion
744
   needed; this is currently 12 bytes for bne/beq pair.  */
745
#define FRAG_VAR_SIZE 12
746
 
747
/* The fields are:
748
   How far Forward this mode will reach:
749
   How far Backward this mode will reach:
750
   How many bytes this mode will add to the size of the frag
751
   Which mode to go to if the offset won't fit in this one
752
 
753
   Please check tc-m68k.h:md_prepare_relax_scan if changing this table.  */
754
relax_typeS md_relax_table[] =
755
{
756
  {   127,   -128,  0, TAB (BRANCHBWL, SHORT) },
757
  { 32767, -32768,  2, TAB (BRANCHBWL, LONG) },
758
  {     0,       0,  4, 0 },
759
  {     1,      1,  0, 0 },
760
 
761
  {   127,   -128,  0, TAB (BRABSJUNC, SHORT) },
762
  { 32767, -32768,  2, TAB (BRABSJUNC, LONG) },
763
  {     0,       0,  4, 0 },
764
  {     1,      1,  0, 0 },
765
 
766
  {   127,   -128,  0, TAB (BRABSJCOND, SHORT) },
767
  { 32767, -32768,  2, TAB (BRABSJCOND, LONG) },
768
  {     0,       0,  6, 0 },
769
  {     1,      1,  0, 0 },
770
 
771
  {   127,   -128,  0, TAB (BRANCHBW, SHORT) },
772
  {     0,       0,  2, 0 },
773
  {     1,      1,  0, 0 },
774
  {     1,      1,  0, 0 },
775
 
776
  {     1,      1,  0, 0 },               /* FBRANCH doesn't come BYTE.  */
777
  { 32767, -32768,  2, TAB (FBRANCH, LONG) },
778
  {     0,       0,  4, 0 },
779
  {     1,      1,  0, 0 },
780
 
781
  {     1,      1,  0, 0 },               /* DBCC doesn't come BYTE.  */
782
  { 32767, -32768,  2, TAB (DBCCLBR, LONG) },
783
  {     0,       0, 10, 0 },
784
  {     1,      1,  0, 0 },
785
 
786
  {     1,      1,  0, 0 },               /* DBCC doesn't come BYTE.  */
787
  { 32767, -32768,  2, TAB (DBCCABSJ, LONG) },
788
  {     0,       0, 10, 0 },
789
  {     1,      1,  0, 0 },
790
 
791
  {     1,      1,  0, 0 },               /* PCREL1632 doesn't come BYTE.  */
792
  { 32767, -32768,  2, TAB (PCREL1632, LONG) },
793
  {     0,       0,  6, 0 },
794
  {     1,      1,  0, 0 },
795
 
796
  {   125,   -130,  0, TAB (PCINDEX, SHORT) },
797
  { 32765, -32770,  2, TAB (PCINDEX, LONG) },
798
  {     0,       0,  4, 0 },
799
  {     1,      1,  0, 0 },
800
 
801
  {     1,      1,  0, 0 },               /* ABSTOPCREL doesn't come BYTE.  */
802
  { 32767, -32768,  2, TAB (ABSTOPCREL, LONG) },
803
  {     0,       0,  4, 0 },
804
  {     1,      1,  0, 0 },
805
 
806
  {   127,   -128,  0, TAB (BRANCHBWPL, SHORT) },
807
  { 32767, -32768,  2, TAB (BRANCHBWPL, LONG) },
808
  {     0,       0,  10, 0 },
809
  {     1,      1,  0, 0 },
810
};
811
 
812
/* These are the machine dependent pseudo-ops.  These are included so
813
   the assembler can work on the output from the SUN C compiler, which
814
   generates these.  */
815
 
816
/* This table describes all the machine specific pseudo-ops the assembler
817
   has to support.  The fields are:
818
   pseudo-op name without dot
819
   function to call to execute this pseudo-op
820
   Integer arg to pass to the function.  */
821
const pseudo_typeS md_pseudo_table[] =
822
{
823
  {"data1", s_data1, 0},
824
  {"data2", s_data2, 0},
825
  {"bss", s_bss, 0},
826
  {"even", s_even, 0},
827
  {"skip", s_space, 0},
828
  {"proc", s_proc, 0},
829
#if defined (TE_SUN3) || defined (OBJ_ELF)
830
  {"align", s_align_bytes, 0},
831
#endif
832
#ifdef OBJ_ELF
833
  {"swbeg", s_ignore, 0},
834
#endif
835
  {"extend", float_cons, 'x'},
836
  {"ldouble", float_cons, 'x'},
837
 
838
  {"arch", s_m68k_arch, 0},
839
  {"cpu", s_m68k_cpu, 0},
840
 
841
  /* The following pseudo-ops are supported for MRI compatibility.  */
842
  {"chip", s_chip, 0},
843
  {"comline", s_space, 1},
844
  {"fopt", s_fopt, 0},
845
  {"mask2", s_ignore, 0},
846
  {"opt", s_opt, 0},
847
  {"reg", s_reg, 0},
848
  {"restore", s_restore, 0},
849
  {"save", s_save, 0},
850
 
851
  {"if", s_mri_if, 0},
852
  {"if.b", s_mri_if, 'b'},
853
  {"if.w", s_mri_if, 'w'},
854
  {"if.l", s_mri_if, 'l'},
855
  {"else", s_mri_else, 0},
856
  {"else.s", s_mri_else, 's'},
857
  {"else.l", s_mri_else, 'l'},
858
  {"endi", s_mri_endi, 0},
859
  {"break", s_mri_break, 0},
860
  {"break.s", s_mri_break, 's'},
861
  {"break.l", s_mri_break, 'l'},
862
  {"next", s_mri_next, 0},
863
  {"next.s", s_mri_next, 's'},
864
  {"next.l", s_mri_next, 'l'},
865
  {"for", s_mri_for, 0},
866
  {"for.b", s_mri_for, 'b'},
867
  {"for.w", s_mri_for, 'w'},
868
  {"for.l", s_mri_for, 'l'},
869
  {"endf", s_mri_endf, 0},
870
  {"repeat", s_mri_repeat, 0},
871
  {"until", s_mri_until, 0},
872
  {"until.b", s_mri_until, 'b'},
873
  {"until.w", s_mri_until, 'w'},
874
  {"until.l", s_mri_until, 'l'},
875
  {"while", s_mri_while, 0},
876
  {"while.b", s_mri_while, 'b'},
877
  {"while.w", s_mri_while, 'w'},
878
  {"while.l", s_mri_while, 'l'},
879
  {"endw", s_mri_endw, 0},
880
 
881
  {0, 0, 0}
882
};
883
 
884
/* The mote pseudo ops are put into the opcode table, since they
885
   don't start with a . they look like opcodes to gas.  */
886
 
887
const pseudo_typeS mote_pseudo_table[] =
888
{
889
 
890
  {"dcl", cons, 4},
891
  {"dc", cons, 2},
892
  {"dcw", cons, 2},
893
  {"dcb", cons, 1},
894
 
895
  {"dsl", s_space, 4},
896
  {"ds", s_space, 2},
897
  {"dsw", s_space, 2},
898
  {"dsb", s_space, 1},
899
 
900
  {"xdef", s_globl, 0},
901
#ifdef OBJ_ELF
902
  {"align", s_align_bytes, 0},
903
#else
904
  {"align", s_align_ptwo, 0},
905
#endif
906
#ifdef M68KCOFF
907
  {"sect", obj_coff_section, 0},
908
  {"section", obj_coff_section, 0},
909
#endif
910
  {0, 0, 0}
911
};
912
 
913
/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
914
   gives identical results to a 32-bit host.  */
915
#define TRUNC(X)        ((valueT) (X) & 0xffffffff)
916
#define SEXT(X)         ((TRUNC (X) ^ 0x80000000) - 0x80000000)
917
 
918
#define issbyte(x)      ((valueT) SEXT (x) + 0x80 < 0x100)
919
#define isubyte(x)      ((valueT) TRUNC (x) < 0x100)
920
#define issword(x)      ((valueT) SEXT (x) + 0x8000 < 0x10000)
921
#define isuword(x)      ((valueT) TRUNC (x) < 0x10000)
922
 
923
#define isbyte(x)       ((valueT) SEXT (x) + 0xff < 0x1ff)
924
#define isword(x)       ((valueT) SEXT (x) + 0xffff < 0x1ffff)
925
#define islong(x)       (1)
926
 
927
static char notend_table[256];
928
static char alt_notend_table[256];
929
#define notend(s)                                               \
930
  (! (notend_table[(unsigned char) *s]                          \
931
      || (*s == ':'                                             \
932
          && alt_notend_table[(unsigned char) s[1]])))
933
 
934
#ifdef OBJ_ELF
935
 
936
/* Return zero if the reference to SYMBOL from within the same segment may
937
   be relaxed.  */
938
 
939
/* On an ELF system, we can't relax an externally visible symbol,
940
   because it may be overridden by a shared library.  However, if
941
   TARGET_OS is "elf", then we presume that we are assembling for an
942
   embedded system, in which case we don't have to worry about shared
943
   libraries, and we can relax any external sym.  */
944
 
945
#define relaxable_symbol(symbol) \
946
  (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
947
     || S_IS_WEAK (symbol)))
948
 
949
/* Compute the relocation code for a fixup of SIZE bytes, using pc
950
   relative relocation if PCREL is non-zero.  PIC says whether a special
951
   pic relocation was requested.  */
952
 
953
static bfd_reloc_code_real_type
954
get_reloc_code (int size, int pcrel, enum pic_relocation pic)
955
{
956
  switch (pic)
957
    {
958
    case pic_got_pcrel:
959
      switch (size)
960
        {
961
        case 1:
962
          return BFD_RELOC_8_GOT_PCREL;
963
        case 2:
964
          return BFD_RELOC_16_GOT_PCREL;
965
        case 4:
966
          return BFD_RELOC_32_GOT_PCREL;
967
        }
968
      break;
969
 
970
    case pic_got_off:
971
      switch (size)
972
        {
973
        case 1:
974
          return BFD_RELOC_8_GOTOFF;
975
        case 2:
976
          return BFD_RELOC_16_GOTOFF;
977
        case 4:
978
          return BFD_RELOC_32_GOTOFF;
979
        }
980
      break;
981
 
982
    case pic_plt_pcrel:
983
      switch (size)
984
        {
985
        case 1:
986
          return BFD_RELOC_8_PLT_PCREL;
987
        case 2:
988
          return BFD_RELOC_16_PLT_PCREL;
989
        case 4:
990
          return BFD_RELOC_32_PLT_PCREL;
991
        }
992
      break;
993
 
994
    case pic_plt_off:
995
      switch (size)
996
        {
997
        case 1:
998
          return BFD_RELOC_8_PLTOFF;
999
        case 2:
1000
          return BFD_RELOC_16_PLTOFF;
1001
        case 4:
1002
          return BFD_RELOC_32_PLTOFF;
1003
        }
1004
      break;
1005
 
1006
    case pic_none:
1007
      if (pcrel)
1008
        {
1009
          switch (size)
1010
            {
1011
            case 1:
1012
              return BFD_RELOC_8_PCREL;
1013
            case 2:
1014
              return BFD_RELOC_16_PCREL;
1015
            case 4:
1016
              return BFD_RELOC_32_PCREL;
1017
            }
1018
        }
1019
      else
1020
        {
1021
          switch (size)
1022
            {
1023
            case 1:
1024
              return BFD_RELOC_8;
1025
            case 2:
1026
              return BFD_RELOC_16;
1027
            case 4:
1028
              return BFD_RELOC_32;
1029
            }
1030
        }
1031
    }
1032
 
1033
  if (pcrel)
1034
    {
1035
      if (pic == pic_none)
1036
        as_bad (_("Can not do %d byte pc-relative relocation"), size);
1037
      else
1038
        as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1039
    }
1040
  else
1041
    {
1042
      if (pic == pic_none)
1043
        as_bad (_("Can not do %d byte relocation"), size);
1044
      else
1045
        as_bad (_("Can not do %d byte pic relocation"), size);
1046
    }
1047
 
1048
  return BFD_RELOC_NONE;
1049
}
1050
 
1051
/* Here we decide which fixups can be adjusted to make them relative
1052
   to the beginning of the section instead of the symbol.  Basically
1053
   we need to make sure that the dynamic relocations are done
1054
   correctly, so in some cases we force the original symbol to be
1055
   used.  */
1056
int
1057
tc_m68k_fix_adjustable (fixS *fixP)
1058
{
1059
  /* Adjust_reloc_syms doesn't know about the GOT.  */
1060
  switch (fixP->fx_r_type)
1061
    {
1062
    case BFD_RELOC_8_GOT_PCREL:
1063
    case BFD_RELOC_16_GOT_PCREL:
1064
    case BFD_RELOC_32_GOT_PCREL:
1065
    case BFD_RELOC_8_GOTOFF:
1066
    case BFD_RELOC_16_GOTOFF:
1067
    case BFD_RELOC_32_GOTOFF:
1068
    case BFD_RELOC_8_PLT_PCREL:
1069
    case BFD_RELOC_16_PLT_PCREL:
1070
    case BFD_RELOC_32_PLT_PCREL:
1071
    case BFD_RELOC_8_PLTOFF:
1072
    case BFD_RELOC_16_PLTOFF:
1073
    case BFD_RELOC_32_PLTOFF:
1074
      return 0;
1075
 
1076
    case BFD_RELOC_VTABLE_INHERIT:
1077
    case BFD_RELOC_VTABLE_ENTRY:
1078
      return 0;
1079
 
1080
    default:
1081
      return 1;
1082
    }
1083
}
1084
 
1085
#else /* !OBJ_ELF */
1086
 
1087
#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1088
 
1089
/* PR gas/3041 Weak symbols are not relaxable
1090
   because they must be treated as extern.  */
1091
#define relaxable_symbol(symbol)   (!(S_IS_WEAK (symbol)))
1092
 
1093
#endif /* OBJ_ELF */
1094
 
1095
arelent *
1096
tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1097
{
1098
  arelent *reloc;
1099
  bfd_reloc_code_real_type code;
1100
 
1101
  /* If the tcbit is set, then this was a fixup of a negative value
1102
     that was never resolved.  We do not have a reloc to handle this,
1103
     so just return.  We assume that other code will have detected this
1104
     situation and produced a helpful error message, so we just tell the
1105
     user that the reloc cannot be produced.  */
1106
  if (fixp->fx_tcbit)
1107
    {
1108
      if (fixp->fx_addsy)
1109
        as_bad_where (fixp->fx_file, fixp->fx_line,
1110
                      _("Unable to produce reloc against symbol '%s'"),
1111
                      S_GET_NAME (fixp->fx_addsy));
1112
      return NULL;
1113
    }
1114
 
1115
  if (fixp->fx_r_type != BFD_RELOC_NONE)
1116
    {
1117
      code = fixp->fx_r_type;
1118
 
1119
      /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1120
         that fixup_segment converted a non-PC relative reloc into a
1121
         PC relative reloc.  In such a case, we need to convert the
1122
         reloc code.  */
1123
      if (fixp->fx_pcrel)
1124
        {
1125
          switch (code)
1126
            {
1127
            case BFD_RELOC_8:
1128
              code = BFD_RELOC_8_PCREL;
1129
              break;
1130
            case BFD_RELOC_16:
1131
              code = BFD_RELOC_16_PCREL;
1132
              break;
1133
            case BFD_RELOC_32:
1134
              code = BFD_RELOC_32_PCREL;
1135
              break;
1136
            case BFD_RELOC_8_PCREL:
1137
            case BFD_RELOC_16_PCREL:
1138
            case BFD_RELOC_32_PCREL:
1139
            case BFD_RELOC_8_GOT_PCREL:
1140
            case BFD_RELOC_16_GOT_PCREL:
1141
            case BFD_RELOC_32_GOT_PCREL:
1142
            case BFD_RELOC_8_GOTOFF:
1143
            case BFD_RELOC_16_GOTOFF:
1144
            case BFD_RELOC_32_GOTOFF:
1145
            case BFD_RELOC_8_PLT_PCREL:
1146
            case BFD_RELOC_16_PLT_PCREL:
1147
            case BFD_RELOC_32_PLT_PCREL:
1148
            case BFD_RELOC_8_PLTOFF:
1149
            case BFD_RELOC_16_PLTOFF:
1150
            case BFD_RELOC_32_PLTOFF:
1151
              break;
1152
            default:
1153
              as_bad_where (fixp->fx_file, fixp->fx_line,
1154
                            _("Cannot make %s relocation PC relative"),
1155
                            bfd_get_reloc_code_name (code));
1156
            }
1157
        }
1158
    }
1159
  else
1160
    {
1161
#define F(SZ,PCREL)             (((SZ) << 1) + (PCREL))
1162
      switch (F (fixp->fx_size, fixp->fx_pcrel))
1163
        {
1164
#define MAP(SZ,PCREL,TYPE)      case F(SZ,PCREL): code = (TYPE); break
1165
          MAP (1, 0, BFD_RELOC_8);
1166
          MAP (2, 0, BFD_RELOC_16);
1167
          MAP (4, 0, BFD_RELOC_32);
1168
          MAP (1, 1, BFD_RELOC_8_PCREL);
1169
          MAP (2, 1, BFD_RELOC_16_PCREL);
1170
          MAP (4, 1, BFD_RELOC_32_PCREL);
1171
        default:
1172
          abort ();
1173
        }
1174
    }
1175
#undef F
1176
#undef MAP
1177
 
1178
  reloc = (arelent *) xmalloc (sizeof (arelent));
1179
  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1180
  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1181
  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1182
#ifndef OBJ_ELF
1183
  if (fixp->fx_pcrel)
1184
    reloc->addend = fixp->fx_addnumber;
1185
  else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1186
           && fixp->fx_addsy
1187
           && S_IS_WEAK (fixp->fx_addsy)
1188
           && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1189
    /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1190
       to put the symbol offset into frags referencing a weak symbol.  */
1191
    reloc->addend = fixp->fx_addnumber
1192
                    - (S_GET_VALUE (fixp->fx_addsy) * 2);
1193
  else
1194
    reloc->addend = 0;
1195
#else
1196
  if (!fixp->fx_pcrel)
1197
    reloc->addend = fixp->fx_addnumber;
1198
  else
1199
    reloc->addend = (section->vma
1200
                     /* Explicit sign extension in case char is
1201
                        unsigned.  */
1202
                     + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1203
                     + fixp->fx_addnumber
1204
                     + md_pcrel_from (fixp));
1205
#endif
1206
 
1207
  reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1208
  assert (reloc->howto != 0);
1209
 
1210
  return reloc;
1211
}
1212
 
1213
/* Handle of the OPCODE hash table.  NULL means any use before
1214
   m68k_ip_begin() will crash.  */
1215
static struct hash_control *op_hash;
1216
 
1217
/* Assemble an m68k instruction.  */
1218
 
1219
static void
1220
m68k_ip (char *instring)
1221
{
1222
  register char *p;
1223
  register struct m68k_op *opP;
1224
  register const struct m68k_incant *opcode;
1225
  register const char *s;
1226
  register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1227
  char *pdot, *pdotmove;
1228
  enum m68k_size siz1, siz2;
1229
  char c;
1230
  int losing;
1231
  int opsfound;
1232
  struct m68k_op operands_backup[6];
1233
  LITTLENUM_TYPE words[6];
1234
  LITTLENUM_TYPE *wordp;
1235
  unsigned long ok_arch = 0;
1236
 
1237
  if (*instring == ' ')
1238
    instring++;                 /* Skip leading whitespace.  */
1239
 
1240
  /* Scan up to end of operation-code, which MUST end in end-of-string
1241
     or exactly 1 space.  */
1242
  pdot = 0;
1243
  for (p = instring; *p != '\0'; p++)
1244
    {
1245
      if (*p == ' ')
1246
        break;
1247
      if (*p == '.')
1248
        pdot = p;
1249
    }
1250
 
1251
  if (p == instring)
1252
    {
1253
      the_ins.error = _("No operator");
1254
      return;
1255
    }
1256
 
1257
  /* p now points to the end of the opcode name, probably whitespace.
1258
     Make sure the name is null terminated by clobbering the
1259
     whitespace, look it up in the hash table, then fix it back.
1260
     Remove a dot, first, since the opcode tables have none.  */
1261
  if (pdot != NULL)
1262
    {
1263
      for (pdotmove = pdot; pdotmove < p; pdotmove++)
1264
        *pdotmove = pdotmove[1];
1265
      p--;
1266
    }
1267
 
1268
  c = *p;
1269
  *p = '\0';
1270
  opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1271
  *p = c;
1272
 
1273
  if (pdot != NULL)
1274
    {
1275
      for (pdotmove = p; pdotmove > pdot; pdotmove--)
1276
        *pdotmove = pdotmove[-1];
1277
      *pdot = '.';
1278
      ++p;
1279
    }
1280
 
1281
  if (opcode == NULL)
1282
    {
1283
      the_ins.error = _("Unknown operator");
1284
      return;
1285
    }
1286
 
1287
  /* Found a legitimate opcode, start matching operands.  */
1288
  while (*p == ' ')
1289
    ++p;
1290
 
1291
  if (opcode->m_operands == 0)
1292
    {
1293
      char *old = input_line_pointer;
1294
      *old = '\n';
1295
      input_line_pointer = p;
1296
      /* Ahh - it's a motorola style psuedo op.  */
1297
      mote_pseudo_table[opcode->m_opnum].poc_handler
1298
        (mote_pseudo_table[opcode->m_opnum].poc_val);
1299
      input_line_pointer = old;
1300
      *old = 0;
1301
 
1302
      return;
1303
    }
1304
 
1305
  if (flag_mri && opcode->m_opnum == 0)
1306
    {
1307
      /* In MRI mode, random garbage is allowed after an instruction
1308
         which accepts no operands.  */
1309
      the_ins.args = opcode->m_operands;
1310
      the_ins.numargs = opcode->m_opnum;
1311
      the_ins.numo = opcode->m_codenum;
1312
      the_ins.opcode[0] = getone (opcode);
1313
      the_ins.opcode[1] = gettwo (opcode);
1314
      return;
1315
    }
1316
 
1317
  for (opP = &the_ins.operands[0]; *p; opP++)
1318
    {
1319
      p = crack_operand (p, opP);
1320
 
1321
      if (opP->error)
1322
        {
1323
          the_ins.error = opP->error;
1324
          return;
1325
        }
1326
    }
1327
 
1328
  opsfound = opP - &the_ins.operands[0];
1329
 
1330
  /* This ugly hack is to support the floating pt opcodes in their
1331
     standard form.  Essentially, we fake a first enty of type COP#1 */
1332
  if (opcode->m_operands[0] == 'I')
1333
    {
1334
      int n;
1335
 
1336
      for (n = opsfound; n > 0; --n)
1337
        the_ins.operands[n] = the_ins.operands[n - 1];
1338
 
1339
      memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1340
      the_ins.operands[0].mode = CONTROL;
1341
      the_ins.operands[0].reg = m68k_float_copnum;
1342
      opsfound++;
1343
    }
1344
 
1345
  /* We've got the operands.  Find an opcode that'll accept them.  */
1346
  for (losing = 0;;)
1347
    {
1348
      /* If we didn't get the right number of ops, or we have no
1349
         common model with this pattern then reject this pattern.  */
1350
 
1351
      ok_arch |= opcode->m_arch;
1352
      if (opsfound != opcode->m_opnum
1353
          || ((opcode->m_arch & current_architecture) == 0))
1354
        ++losing;
1355
      else
1356
        {
1357
          int i;
1358
 
1359
          /* Make a copy of the operands of this insn so that
1360
             we can modify them safely, should we want to.  */
1361
          assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1362
          for (i = 0; i < opsfound; i++)
1363
            operands_backup[i] = the_ins.operands[i];
1364
 
1365
          for (s = opcode->m_operands, opP = &operands_backup[0];
1366
               *s && !losing;
1367
               s += 2, opP++)
1368
            {
1369
              /* Warning: this switch is huge! */
1370
              /* I've tried to organize the cases into this order:
1371
                 non-alpha first, then alpha by letter.  Lower-case
1372
                 goes directly before uppercase counterpart.  */
1373
              /* Code with multiple case ...: gets sorted by the lowest
1374
                 case ... it belongs to.  I hope this makes sense.  */
1375
              switch (*s)
1376
                {
1377
                case '!':
1378
                  switch (opP->mode)
1379
                    {
1380
                    case IMMED:
1381
                    case DREG:
1382
                    case AREG:
1383
                    case FPREG:
1384
                    case CONTROL:
1385
                    case AINC:
1386
                    case ADEC:
1387
                    case REGLST:
1388
                      losing++;
1389
                      break;
1390
                    default:
1391
                      break;
1392
                    }
1393
                  break;
1394
 
1395
                case '<':
1396
                  switch (opP->mode)
1397
                    {
1398
                    case DREG:
1399
                    case AREG:
1400
                    case FPREG:
1401
                    case CONTROL:
1402
                    case IMMED:
1403
                    case ADEC:
1404
                    case REGLST:
1405
                      losing++;
1406
                      break;
1407
                    default:
1408
                      break;
1409
                    }
1410
                  break;
1411
 
1412
                case '>':
1413
                  switch (opP->mode)
1414
                    {
1415
                    case DREG:
1416
                    case AREG:
1417
                    case FPREG:
1418
                    case CONTROL:
1419
                    case IMMED:
1420
                    case AINC:
1421
                    case REGLST:
1422
                      losing++;
1423
                      break;
1424
                    case ABSL:
1425
                      break;
1426
                    default:
1427
                      if (opP->reg == PC
1428
                          || opP->reg == ZPC)
1429
                        losing++;
1430
                      break;
1431
                    }
1432
                  break;
1433
 
1434
                case 'm':
1435
                  switch (opP->mode)
1436
                    {
1437
                    case DREG:
1438
                    case AREG:
1439
                    case AINDR:
1440
                    case AINC:
1441
                    case ADEC:
1442
                      break;
1443
                    default:
1444
                      losing++;
1445
                    }
1446
                  break;
1447
 
1448
                case 'n':
1449
                  switch (opP->mode)
1450
                    {
1451
                    case DISP:
1452
                      break;
1453
                    default:
1454
                      losing++;
1455
                    }
1456
                  break;
1457
 
1458
                case 'o':
1459
                  switch (opP->mode)
1460
                    {
1461
                    case BASE:
1462
                    case ABSL:
1463
                    case IMMED:
1464
                      break;
1465
                    default:
1466
                      losing++;
1467
                    }
1468
                  break;
1469
 
1470
                case 'p':
1471
                  switch (opP->mode)
1472
                    {
1473
                    case DREG:
1474
                    case AREG:
1475
                    case AINDR:
1476
                    case AINC:
1477
                    case ADEC:
1478
                      break;
1479
                    case DISP:
1480
                      if (opP->reg == PC || opP->reg == ZPC)
1481
                        losing++;
1482
                      break;
1483
                    default:
1484
                      losing++;
1485
                    }
1486
                  break;
1487
 
1488
                case 'q':
1489
                  switch (opP->mode)
1490
                    {
1491
                    case DREG:
1492
                    case AINDR:
1493
                    case AINC:
1494
                    case ADEC:
1495
                      break;
1496
                    case DISP:
1497
                      if (opP->reg == PC || opP->reg == ZPC)
1498
                        losing++;
1499
                      break;
1500
                    default:
1501
                      losing++;
1502
                      break;
1503
                    }
1504
                  break;
1505
 
1506
                case 'v':
1507
                  switch (opP->mode)
1508
                    {
1509
                    case DREG:
1510
                    case AINDR:
1511
                    case AINC:
1512
                    case ADEC:
1513
                    case ABSL:
1514
                      break;
1515
                    case DISP:
1516
                      if (opP->reg == PC || opP->reg == ZPC)
1517
                        losing++;
1518
                      break;
1519
                    default:
1520
                      losing++;
1521
                      break;
1522
                    }
1523
                  break;
1524
 
1525
                case '#':
1526
                  if (opP->mode != IMMED)
1527
                    losing++;
1528
                  else if (s[1] == 'b'
1529
                           && ! isvar (&opP->disp)
1530
                           && (opP->disp.exp.X_op != O_constant
1531
                               || ! isbyte (opP->disp.exp.X_add_number)))
1532
                    losing++;
1533
                  else if (s[1] == 'B'
1534
                           && ! isvar (&opP->disp)
1535
                           && (opP->disp.exp.X_op != O_constant
1536
                               || ! issbyte (opP->disp.exp.X_add_number)))
1537
                    losing++;
1538
                  else if (s[1] == 'w'
1539
                           && ! isvar (&opP->disp)
1540
                           && (opP->disp.exp.X_op != O_constant
1541
                               || ! isword (opP->disp.exp.X_add_number)))
1542
                    losing++;
1543
                  else if (s[1] == 'W'
1544
                           && ! isvar (&opP->disp)
1545
                           && (opP->disp.exp.X_op != O_constant
1546
                               || ! issword (opP->disp.exp.X_add_number)))
1547
                    losing++;
1548
                  break;
1549
 
1550
                case '^':
1551
                case 'T':
1552
                  if (opP->mode != IMMED)
1553
                    losing++;
1554
                  break;
1555
 
1556
                case '$':
1557
                  if (opP->mode == AREG
1558
                      || opP->mode == CONTROL
1559
                      || opP->mode == FPREG
1560
                      || opP->mode == IMMED
1561
                      || opP->mode == REGLST
1562
                      || (opP->mode != ABSL
1563
                          && (opP->reg == PC
1564
                              || opP->reg == ZPC)))
1565
                    losing++;
1566
                  break;
1567
 
1568
                case '%':
1569
                  if (opP->mode == CONTROL
1570
                      || opP->mode == FPREG
1571
                      || opP->mode == REGLST
1572
                      || opP->mode == IMMED
1573
                      || (opP->mode != ABSL
1574
                          && (opP->reg == PC
1575
                              || opP->reg == ZPC)))
1576
                    losing++;
1577
                  break;
1578
 
1579
                case '&':
1580
                  switch (opP->mode)
1581
                    {
1582
                    case DREG:
1583
                    case AREG:
1584
                    case FPREG:
1585
                    case CONTROL:
1586
                    case IMMED:
1587
                    case AINC:
1588
                    case ADEC:
1589
                    case REGLST:
1590
                      losing++;
1591
                      break;
1592
                    case ABSL:
1593
                      break;
1594
                    default:
1595
                      if (opP->reg == PC
1596
                          || opP->reg == ZPC)
1597
                        losing++;
1598
                      break;
1599
                    }
1600
                  break;
1601
 
1602
                case '*':
1603
                  if (opP->mode == CONTROL
1604
                      || opP->mode == FPREG
1605
                      || opP->mode == REGLST)
1606
                    losing++;
1607
                  break;
1608
 
1609
                case '+':
1610
                  if (opP->mode != AINC)
1611
                    losing++;
1612
                  break;
1613
 
1614
                case '-':
1615
                  if (opP->mode != ADEC)
1616
                    losing++;
1617
                  break;
1618
 
1619
                case '/':
1620
                  switch (opP->mode)
1621
                    {
1622
                    case AREG:
1623
                    case CONTROL:
1624
                    case FPREG:
1625
                    case AINC:
1626
                    case ADEC:
1627
                    case IMMED:
1628
                    case REGLST:
1629
                      losing++;
1630
                      break;
1631
                    default:
1632
                      break;
1633
                    }
1634
                  break;
1635
 
1636
                case ';':
1637
                  switch (opP->mode)
1638
                    {
1639
                    case AREG:
1640
                    case CONTROL:
1641
                    case FPREG:
1642
                    case REGLST:
1643
                      losing++;
1644
                      break;
1645
                    default:
1646
                      break;
1647
                    }
1648
                  break;
1649
 
1650
                case '?':
1651
                  switch (opP->mode)
1652
                    {
1653
                    case AREG:
1654
                    case CONTROL:
1655
                    case FPREG:
1656
                    case AINC:
1657
                    case ADEC:
1658
                    case IMMED:
1659
                    case REGLST:
1660
                      losing++;
1661
                      break;
1662
                    case ABSL:
1663
                      break;
1664
                    default:
1665
                      if (opP->reg == PC || opP->reg == ZPC)
1666
                        losing++;
1667
                      break;
1668
                    }
1669
                  break;
1670
 
1671
                case '@':
1672
                  switch (opP->mode)
1673
                    {
1674
                    case AREG:
1675
                    case CONTROL:
1676
                    case FPREG:
1677
                    case IMMED:
1678
                    case REGLST:
1679
                      losing++;
1680
                      break;
1681
                    default:
1682
                      break;
1683
                    }
1684
                  break;
1685
 
1686
                case '~':       /* For now! (JF FOO is this right?) */
1687
                  switch (opP->mode)
1688
                    {
1689
                    case DREG:
1690
                    case AREG:
1691
                    case CONTROL:
1692
                    case FPREG:
1693
                    case IMMED:
1694
                    case REGLST:
1695
                      losing++;
1696
                      break;
1697
                    case ABSL:
1698
                      break;
1699
                    default:
1700
                      if (opP->reg == PC
1701
                          || opP->reg == ZPC)
1702
                        losing++;
1703
                      break;
1704
                    }
1705
                  break;
1706
 
1707
                case '3':
1708
                  if (opP->mode != CONTROL
1709
                      || (opP->reg != TT0 && opP->reg != TT1))
1710
                    losing++;
1711
                  break;
1712
 
1713
                case 'A':
1714
                  if (opP->mode != AREG)
1715
                    losing++;
1716
                  break;
1717
 
1718
                case 'a':
1719
                  if (opP->mode != AINDR)
1720
                    ++losing;
1721
                  break;
1722
 
1723
                case '4':
1724
                  if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1725
                      && (opP->mode != DISP
1726
                           || opP->reg < ADDR0
1727
                           || opP->reg > ADDR7))
1728
                    ++losing;
1729
                  break;
1730
 
1731
                case 'B':       /* FOO */
1732
                  if (opP->mode != ABSL
1733
                      || (flag_long_jumps
1734
                          && strncmp (instring, "jbsr", 4) == 0))
1735
                    losing++;
1736
                  break;
1737
 
1738
                case 'b':
1739
                  switch (opP->mode)
1740
                    {
1741
                    case IMMED:
1742
                    case ABSL:
1743
                    case AREG:
1744
                    case FPREG:
1745
                    case CONTROL:
1746
                    case POST:
1747
                    case PRE:
1748
                    case REGLST:
1749
                      losing++;
1750
                      break;
1751
                    default:
1752
                      break;
1753
                    }
1754
                  break;
1755
 
1756
                case 'C':
1757
                  if (opP->mode != CONTROL || opP->reg != CCR)
1758
                    losing++;
1759
                  break;
1760
 
1761
                case 'd':
1762
                  if (opP->mode != DISP
1763
                      || opP->reg < ADDR0
1764
                      || opP->reg > ADDR7)
1765
                    losing++;
1766
                  break;
1767
 
1768
                case 'D':
1769
                  if (opP->mode != DREG)
1770
                    losing++;
1771
                  break;
1772
 
1773
                case 'E':
1774
                  if (opP->reg != ACC)
1775
                    losing++;
1776
                  break;
1777
 
1778
                case 'e':
1779
                  if (opP->reg != ACC && opP->reg != ACC1
1780
                      && opP->reg != ACC2 && opP->reg != ACC3)
1781
                    losing++;
1782
                  break;
1783
 
1784
                case 'F':
1785
                  if (opP->mode != FPREG)
1786
                    losing++;
1787
                  break;
1788
 
1789
                case 'G':
1790
                  if (opP->reg != MACSR)
1791
                    losing++;
1792
                  break;
1793
 
1794
                case 'g':
1795
                  if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1796
                    losing++;
1797
                  break;
1798
 
1799
                case 'H':
1800
                  if (opP->reg != MASK)
1801
                    losing++;
1802
                  break;
1803
 
1804
                case 'I':
1805
                  if (opP->mode != CONTROL
1806
                      || opP->reg < COP0
1807
                      || opP->reg > COP7)
1808
                    losing++;
1809
                  break;
1810
 
1811
                case 'i':
1812
                  if (opP->mode != LSH && opP->mode != RSH)
1813
                    losing++;
1814
                  break;
1815
 
1816
                case 'J':
1817
                  if (opP->mode != CONTROL
1818
                      || opP->reg < USP
1819
                      || opP->reg > last_movec_reg
1820
                      || !control_regs)
1821
                    losing++;
1822
                  else
1823
                    {
1824
                      const enum m68k_register *rp;
1825
 
1826
                      for (rp = control_regs; *rp; rp++)
1827
                        {
1828
                          if (*rp == opP->reg)
1829
                            break;
1830
                          /* In most CPUs RAMBAR refers to control reg
1831
                             c05 (RAMBAR1), but a few CPUs have it
1832
                             refer to c04 (RAMBAR0).  */
1833
                          else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1834
                            {
1835
                              opP->reg = RAMBAR_ALT;
1836
                              break;
1837
                            }
1838
                        }
1839
                      if (*rp == 0)
1840
                        losing++;
1841
                    }
1842
                  break;
1843
 
1844
                case 'k':
1845
                  if (opP->mode != IMMED)
1846
                    losing++;
1847
                  break;
1848
 
1849
                case 'l':
1850
                case 'L':
1851
                  if (opP->mode == DREG
1852
                      || opP->mode == AREG
1853
                      || opP->mode == FPREG)
1854
                    {
1855
                      if (s[1] == '8')
1856
                        losing++;
1857
                      else
1858
                        {
1859
                          switch (opP->mode)
1860
                            {
1861
                            case DREG:
1862
                              opP->mask = 1 << (opP->reg - DATA0);
1863
                              break;
1864
                            case AREG:
1865
                              opP->mask = 1 << (opP->reg - ADDR0 + 8);
1866
                              break;
1867
                            case FPREG:
1868
                              opP->mask = 1 << (opP->reg - FP0 + 16);
1869
                              break;
1870
                            default:
1871
                              abort ();
1872
                            }
1873
                          opP->mode = REGLST;
1874
                        }
1875
                    }
1876
                  else if (opP->mode == CONTROL)
1877
                    {
1878
                      if (s[1] != '8')
1879
                        losing++;
1880
                      else
1881
                        {
1882
                          switch (opP->reg)
1883
                            {
1884
                            case FPI:
1885
                              opP->mask = 1 << 24;
1886
                              break;
1887
                            case FPS:
1888
                              opP->mask = 1 << 25;
1889
                              break;
1890
                            case FPC:
1891
                              opP->mask = 1 << 26;
1892
                              break;
1893
                            default:
1894
                              losing++;
1895
                              break;
1896
                            }
1897
                          opP->mode = REGLST;
1898
                        }
1899
                    }
1900
                  else if (opP->mode != REGLST)
1901
                    losing++;
1902
                  else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1903
                    losing++;
1904
                  else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1905
                    losing++;
1906
                  break;
1907
 
1908
                case 'M':
1909
                  if (opP->mode != IMMED)
1910
                    losing++;
1911
                  else if (opP->disp.exp.X_op != O_constant
1912
                           || ! issbyte (opP->disp.exp.X_add_number))
1913
                    losing++;
1914
                  else if (! m68k_quick
1915
                           && instring[3] != 'q'
1916
                           && instring[4] != 'q')
1917
                    losing++;
1918
                  break;
1919
 
1920
                case 'O':
1921
                  if (opP->mode != DREG
1922
                      && opP->mode != IMMED
1923
                      && opP->mode != ABSL)
1924
                    losing++;
1925
                  break;
1926
 
1927
                case 'Q':
1928
                  if (opP->mode != IMMED)
1929
                    losing++;
1930
                  else if (opP->disp.exp.X_op != O_constant
1931
                           || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1932
                    losing++;
1933
                  else if (! m68k_quick
1934
                           && (strncmp (instring, "add", 3) == 0
1935
                               || strncmp (instring, "sub", 3) == 0)
1936
                           && instring[3] != 'q')
1937
                    losing++;
1938
                  break;
1939
 
1940
                case 'R':
1941
                  if (opP->mode != DREG && opP->mode != AREG)
1942
                    losing++;
1943
                  break;
1944
 
1945
                case 'r':
1946
                  if (opP->mode != AINDR
1947
                      && (opP->mode != BASE
1948
                          || (opP->reg != 0
1949
                              && opP->reg != ZADDR0)
1950
                          || opP->disp.exp.X_op != O_absent
1951
                          || ((opP->index.reg < DATA0
1952
                               || opP->index.reg > DATA7)
1953
                              && (opP->index.reg < ADDR0
1954
                                  || opP->index.reg > ADDR7))
1955
                          || opP->index.size != SIZE_UNSPEC
1956
                          || opP->index.scale != 1))
1957
                    losing++;
1958
                  break;
1959
 
1960
                case 's':
1961
                  if (opP->mode != CONTROL
1962
                      || ! (opP->reg == FPI
1963
                            || opP->reg == FPS
1964
                            || opP->reg == FPC))
1965
                    losing++;
1966
                  break;
1967
 
1968
                case 'S':
1969
                  if (opP->mode != CONTROL || opP->reg != SR)
1970
                    losing++;
1971
                  break;
1972
 
1973
                case 't':
1974
                  if (opP->mode != IMMED)
1975
                    losing++;
1976
                  else if (opP->disp.exp.X_op != O_constant
1977
                           || TRUNC (opP->disp.exp.X_add_number) > 7)
1978
                    losing++;
1979
                  break;
1980
 
1981
                case 'U':
1982
                  if (opP->mode != CONTROL || opP->reg != USP)
1983
                    losing++;
1984
                  break;
1985
 
1986
                case 'x':
1987
                  if (opP->mode != IMMED)
1988
                    losing++;
1989
                  else if (opP->disp.exp.X_op != O_constant
1990
                           || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1991
                               && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1992
                    losing++;
1993
                  break;
1994
 
1995
                case 'j':
1996
                  if (opP->mode != IMMED)
1997
                    losing++;
1998
                  else if (opP->disp.exp.X_op != O_constant
1999
                           || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2000
                    losing++;
2001
                  break;
2002
 
2003
                case 'K':
2004
                  if (opP->mode != IMMED)
2005
                    losing++;
2006
                  else if (opP->disp.exp.X_op != O_constant
2007
                           || TRUNC (opP->disp.exp.X_add_number) > 511)
2008
                    losing++;
2009
                  break;
2010
 
2011
                  /* JF these are out of order.  We could put them
2012
                     in order if we were willing to put up with
2013
                     bunches of #ifdef m68851s in the code.
2014
 
2015
                     Don't forget that you need these operands
2016
                     to use 68030 MMU instructions.  */
2017
#ifndef NO_68851
2018
                  /* Memory addressing mode used by pflushr.  */
2019
                case '|':
2020
                  if (opP->mode == CONTROL
2021
                      || opP->mode == FPREG
2022
                      || opP->mode == DREG
2023
                      || opP->mode == AREG
2024
                      || opP->mode == REGLST)
2025
                    losing++;
2026
                  /* We should accept immediate operands, but they
2027
                     supposedly have to be quad word, and we don't
2028
                     handle that.  I would like to see what a Motorola
2029
                     assembler does before doing something here.  */
2030
                  if (opP->mode == IMMED)
2031
                    losing++;
2032
                  break;
2033
 
2034
                case 'f':
2035
                  if (opP->mode != CONTROL
2036
                      || (opP->reg != SFC && opP->reg != DFC))
2037
                    losing++;
2038
                  break;
2039
 
2040
                case '0':
2041
                  if (opP->mode != CONTROL || opP->reg != TC)
2042
                    losing++;
2043
                  break;
2044
 
2045
                case '1':
2046
                  if (opP->mode != CONTROL || opP->reg != AC)
2047
                    losing++;
2048
                  break;
2049
 
2050
                case '2':
2051
                  if (opP->mode != CONTROL
2052
                      || (opP->reg != CAL
2053
                          && opP->reg != VAL
2054
                          && opP->reg != SCC))
2055
                    losing++;
2056
                  break;
2057
 
2058
                case 'V':
2059
                  if (opP->mode != CONTROL
2060
                      || opP->reg != VAL)
2061
                    losing++;
2062
                  break;
2063
 
2064
                case 'W':
2065
                  if (opP->mode != CONTROL
2066
                      || (opP->reg != DRP
2067
                          && opP->reg != SRP
2068
                          && opP->reg != CRP))
2069
                    losing++;
2070
                  break;
2071
 
2072
                case 'w':
2073
                  switch (opP->mode)
2074
                    {
2075
                      case IMMED:
2076
                      case ABSL:
2077
                      case AREG:
2078
                      case DREG:
2079
                      case FPREG:
2080
                      case CONTROL:
2081
                      case POST:
2082
                      case PRE:
2083
                      case REGLST:
2084
                        losing++;
2085
                        break;
2086
                      default:
2087
                        break;
2088
                    }
2089
                  break;
2090
 
2091
                case 'X':
2092
                  if (opP->mode != CONTROL
2093
                      || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2094
                          && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2095
                    losing++;
2096
                  break;
2097
 
2098
                case 'Y':
2099
                  if (opP->mode != CONTROL || opP->reg != PSR)
2100
                    losing++;
2101
                  break;
2102
 
2103
                case 'Z':
2104
                  if (opP->mode != CONTROL || opP->reg != PCSR)
2105
                    losing++;
2106
                  break;
2107
#endif
2108
                case 'c':
2109
                  if (opP->mode != CONTROL
2110
                      || (opP->reg != NC
2111
                          && opP->reg != IC
2112
                          && opP->reg != DC
2113
                          && opP->reg != BC))
2114
                    losing++;
2115
                  break;
2116
 
2117
                case '_':
2118
                  if (opP->mode != ABSL)
2119
                    ++losing;
2120
                  break;
2121
 
2122
                case 'u':
2123
                  if (opP->reg < DATA0L || opP->reg > ADDR7U)
2124
                    losing++;
2125
                  /* FIXME: kludge instead of fixing parser:
2126
                     upper/lower registers are *not* CONTROL
2127
                     registers, but ordinary ones.  */
2128
                  if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2129
                      || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2130
                    opP->mode = DREG;
2131
                  else
2132
                    opP->mode = AREG;
2133
                  break;
2134
 
2135
                 case 'y':
2136
                   if (!(opP->mode == AINDR
2137
                         || (opP->mode == DISP
2138
                             && !(opP->reg == PC || opP->reg == ZPC))))
2139
                     losing++;
2140
                   break;
2141
 
2142
                 case 'z':
2143
                   if (!(opP->mode == AINDR || opP->mode == DISP))
2144
                     losing++;
2145
                   break;
2146
 
2147
                default:
2148
                  abort ();
2149
                }
2150
 
2151
              if (losing)
2152
                break;
2153
            }
2154
 
2155
          /* Since we have found the correct instruction, copy
2156
             in the modifications that we may have made.  */
2157
          if (!losing)
2158
            for (i = 0; i < opsfound; i++)
2159
              the_ins.operands[i] = operands_backup[i];
2160
        }
2161
 
2162
      if (!losing)
2163
        break;
2164
 
2165
      opcode = opcode->m_next;
2166
 
2167
      if (!opcode)
2168
        {
2169
          if (ok_arch
2170
              && !(ok_arch & current_architecture))
2171
            {
2172
              const struct m68k_cpu *cpu;
2173
              int any = 0;
2174
              size_t space = 400;
2175
              char *buf = xmalloc (space + 1);
2176
              size_t len;
2177
              int paren = 1;
2178
 
2179
              the_ins.error = buf;
2180
              /* Make sure there's a NUL at the end of the buffer -- strncpy
2181
                 won't write one when it runs out of buffer.  */
2182
              buf[space] = 0;
2183
#define APPEND(STRING) \
2184
  (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2185
 
2186
              APPEND (_("invalid instruction for this architecture; needs "));
2187
              switch (ok_arch)
2188
                {
2189
                case mcfisa_a:
2190
                  APPEND ("ColdFire ISA_A");
2191
                  break;
2192
                case mcfhwdiv:
2193
                  APPEND ("ColdFire ");
2194
                  APPEND (_("hardware divide"));
2195
                  break;
2196
                case mcfisa_aa:
2197
                  APPEND ("ColdFire ISA_A+");
2198
                  break;
2199
                case mcfisa_b:
2200
                  APPEND ("ColdFire ISA_B");
2201
                  break;
2202
                case mcfisa_c:
2203
                  APPEND ("ColdFire ISA_C");
2204
                  break;
2205
                case cfloat:
2206
                  APPEND ("ColdFire fpu");
2207
                  break;
2208
                case mfloat:
2209
                  APPEND ("M68K fpu");
2210
                  break;
2211
                case mmmu:
2212
                  APPEND ("M68K mmu");
2213
                  break;
2214
                case m68020up:
2215
                  APPEND ("68020 ");
2216
                  APPEND (_("or higher"));
2217
                  break;
2218
                case m68000up:
2219
                  APPEND ("68000 ");
2220
                  APPEND (_("or higher"));
2221
                  break;
2222
                case m68010up:
2223
                  APPEND ("68010 ");
2224
                  APPEND (_("or higher"));
2225
                  break;
2226
                default:
2227
                  paren = 0;
2228
                }
2229
              if (paren)
2230
                APPEND (" (");
2231
 
2232
              for (cpu = m68k_cpus; cpu->name; cpu++)
2233
                if (!cpu->alias && (cpu->arch & ok_arch))
2234
                  {
2235
                    const struct m68k_cpu *alias;
2236
                    int seen_master = 0;
2237
 
2238
                    if (any)
2239
                      APPEND (", ");
2240
                    any = 0;
2241
                    APPEND (cpu->name);
2242
                    for (alias = cpu; alias != m68k_cpus; alias--)
2243
                      if (alias[-1].alias >= 0)
2244
                        break;
2245
                    for (; !seen_master || alias->alias > 0; alias++)
2246
                        {
2247
                          if (!alias->alias)
2248
                            seen_master = 1;
2249
                          else
2250
                            {
2251
                              if (any)
2252
                                APPEND (", ");
2253
                              else
2254
                                APPEND (" [");
2255
                              APPEND (alias->name);
2256
                              any = 1;
2257
                            }
2258
                        }
2259
                    if (any)
2260
                      APPEND ("]");
2261
                    any = 1;
2262
                  }
2263
              if (paren)
2264
                APPEND (")");
2265
#undef APPEND
2266
              if (!space)
2267
                {
2268
                  /* We ran out of space, so replace the end of the list
2269
                     with ellipsis.  */
2270
                  buf -= 4;
2271
                  while (*buf != ' ')
2272
                    buf--;
2273
                  strcpy (buf, " ...");
2274
                }
2275
            }
2276
          else
2277
            the_ins.error = _("operands mismatch");
2278
          return;
2279
        }
2280
 
2281
      losing = 0;
2282
    }
2283
 
2284
  /* Now assemble it.  */
2285
  the_ins.args = opcode->m_operands;
2286
  the_ins.numargs = opcode->m_opnum;
2287
  the_ins.numo = opcode->m_codenum;
2288
  the_ins.opcode[0] = getone (opcode);
2289
  the_ins.opcode[1] = gettwo (opcode);
2290
 
2291
  for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2292
    {
2293
      int have_disp = 0;
2294
      int use_pl = 0;
2295
 
2296
      /* This switch is a doozy.
2297
         Watch the first step; its a big one! */
2298
      switch (s[0])
2299
        {
2300
 
2301
        case '*':
2302
        case '~':
2303
        case '%':
2304
        case ';':
2305
        case '@':
2306
        case '!':
2307
        case '&':
2308
        case '$':
2309
        case '?':
2310
        case '/':
2311
        case '<':
2312
        case '>':
2313
        case 'b':
2314
        case 'm':
2315
        case 'n':
2316
        case 'o':
2317
        case 'p':
2318
        case 'q':
2319
        case 'v':
2320
        case 'w':
2321
        case 'y':
2322
        case 'z':
2323
        case '4':
2324
#ifndef NO_68851
2325
        case '|':
2326
#endif
2327
          switch (opP->mode)
2328
            {
2329
            case IMMED:
2330
              tmpreg = 0x3c;    /* 7.4 */
2331
              if (strchr ("bwl", s[1]))
2332
                nextword = get_num (&opP->disp, 90);
2333
              else
2334
                nextword = get_num (&opP->disp, 0);
2335
              if (isvar (&opP->disp))
2336
                add_fix (s[1], &opP->disp, 0, 0);
2337
              switch (s[1])
2338
                {
2339
                case 'b':
2340
                  if (!isbyte (nextword))
2341
                    opP->error = _("operand out of range");
2342
                  addword (nextword);
2343
                  baseo = 0;
2344
                  break;
2345
                case 'w':
2346
                  if (!isword (nextword))
2347
                    opP->error = _("operand out of range");
2348
                  addword (nextword);
2349
                  baseo = 0;
2350
                  break;
2351
                case 'W':
2352
                  if (!issword (nextword))
2353
                    opP->error = _("operand out of range");
2354
                  addword (nextword);
2355
                  baseo = 0;
2356
                  break;
2357
                case 'l':
2358
                  addword (nextword >> 16);
2359
                  addword (nextword);
2360
                  baseo = 0;
2361
                  break;
2362
 
2363
                case 'f':
2364
                  baseo = 2;
2365
                  outro = 8;
2366
                  break;
2367
                case 'F':
2368
                  baseo = 4;
2369
                  outro = 11;
2370
                  break;
2371
                case 'x':
2372
                  baseo = 6;
2373
                  outro = 15;
2374
                  break;
2375
                case 'p':
2376
                  baseo = 6;
2377
                  outro = -1;
2378
                  break;
2379
                default:
2380
                  abort ();
2381
                }
2382
              if (!baseo)
2383
                break;
2384
 
2385
              /* We gotta put out some float.  */
2386
              if (op (&opP->disp) != O_big)
2387
                {
2388
                  valueT val;
2389
                  int gencnt;
2390
 
2391
                  /* Can other cases happen here?  */
2392
                  if (op (&opP->disp) != O_constant)
2393
                    abort ();
2394
 
2395
                  val = (valueT) offs (&opP->disp);
2396
                  gencnt = 0;
2397
                  do
2398
                    {
2399
                      generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2400
                      val >>= LITTLENUM_NUMBER_OF_BITS;
2401
                      ++gencnt;
2402
                    }
2403
                  while (val != 0);
2404
                  offs (&opP->disp) = gencnt;
2405
                }
2406
              if (offs (&opP->disp) > 0)
2407
                {
2408
                  if (offs (&opP->disp) > baseo)
2409
                    {
2410
                      as_warn (_("Bignum too big for %c format; truncated"),
2411
                               s[1]);
2412
                      offs (&opP->disp) = baseo;
2413
                    }
2414
                  baseo -= offs (&opP->disp);
2415
                  while (baseo--)
2416
                    addword (0);
2417
                  for (wordp = generic_bignum + offs (&opP->disp) - 1;
2418
                       offs (&opP->disp)--;
2419
                       --wordp)
2420
                    addword (*wordp);
2421
                  break;
2422
                }
2423
              gen_to_words (words, baseo, (long) outro);
2424
              for (wordp = words; baseo--; wordp++)
2425
                addword (*wordp);
2426
              break;
2427
            case DREG:
2428
              tmpreg = opP->reg - DATA; /* 0.dreg */
2429
              break;
2430
            case AREG:
2431
              tmpreg = 0x08 + opP->reg - ADDR;  /* 1.areg */
2432
              break;
2433
            case AINDR:
2434
              tmpreg = 0x10 + opP->reg - ADDR;  /* 2.areg */
2435
              break;
2436
            case ADEC:
2437
              tmpreg = 0x20 + opP->reg - ADDR;  /* 4.areg */
2438
              break;
2439
            case AINC:
2440
              tmpreg = 0x18 + opP->reg - ADDR;  /* 3.areg */
2441
              break;
2442
            case DISP:
2443
 
2444
              nextword = get_num (&opP->disp, 90);
2445
 
2446
              /* Convert mode 5 addressing with a zero offset into
2447
                 mode 2 addressing to reduce the instruction size by a
2448
                 word.  */
2449
              if (! isvar (&opP->disp)
2450
                  && (nextword == 0)
2451
                  && (opP->disp.size == SIZE_UNSPEC)
2452
                  && (opP->reg >= ADDR0)
2453
                  && (opP->reg <= ADDR7))
2454
                {
2455
                  tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2456
                  break;
2457
                }
2458
 
2459
              if (opP->reg == PC
2460
                  && ! isvar (&opP->disp)
2461
                  && m68k_abspcadd)
2462
                {
2463
                  opP->disp.exp.X_op = O_symbol;
2464
                  opP->disp.exp.X_add_symbol =
2465
                    section_symbol (absolute_section);
2466
                }
2467
 
2468
              /* Force into index mode.  Hope this works.  */
2469
 
2470
              /* We do the first bit for 32-bit displacements, and the
2471
                 second bit for 16 bit ones.  It is possible that we
2472
                 should make the default be WORD instead of LONG, but
2473
                 I think that'd break GCC, so we put up with a little
2474
                 inefficiency for the sake of working output.  */
2475
 
2476
              if (!issword (nextword)
2477
                  || (isvar (&opP->disp)
2478
                      && ((opP->disp.size == SIZE_UNSPEC
2479
                           && flag_short_refs == 0
2480
                           && cpu_of_arch (current_architecture) >= m68020
2481
                           && ! arch_coldfire_p (current_architecture))
2482
                          || opP->disp.size == SIZE_LONG)))
2483
                {
2484
                  if (cpu_of_arch (current_architecture) < m68020
2485
                      || arch_coldfire_p (current_architecture))
2486
                    opP->error =
2487
                      _("displacement too large for this architecture; needs 68020 or higher");
2488
                  if (opP->reg == PC)
2489
                    tmpreg = 0x3B;      /* 7.3 */
2490
                  else
2491
                    tmpreg = 0x30 + opP->reg - ADDR;    /* 6.areg */
2492
                  if (isvar (&opP->disp))
2493
                    {
2494
                      if (opP->reg == PC)
2495
                        {
2496
                          if (opP->disp.size == SIZE_LONG
2497
#ifdef OBJ_ELF
2498
                              /* If the displacement needs pic
2499
                                 relocation it cannot be relaxed.  */
2500
                              || opP->disp.pic_reloc != pic_none
2501
#endif
2502
                              )
2503
                            {
2504
                              addword (0x0170);
2505
                              add_fix ('l', &opP->disp, 1, 2);
2506
                            }
2507
                          else
2508
                            {
2509
                              add_frag (adds (&opP->disp),
2510
                                        SEXT (offs (&opP->disp)),
2511
                                        TAB (PCREL1632, SZ_UNDEF));
2512
                              break;
2513
                            }
2514
                        }
2515
                      else
2516
                        {
2517
                          addword (0x0170);
2518
                          add_fix ('l', &opP->disp, 0, 0);
2519
                        }
2520
                    }
2521
                  else
2522
                    addword (0x0170);
2523
                  addword (nextword >> 16);
2524
                }
2525
              else
2526
                {
2527
                  if (opP->reg == PC)
2528
                    tmpreg = 0x3A;      /* 7.2 */
2529
                  else
2530
                    tmpreg = 0x28 + opP->reg - ADDR;    /* 5.areg */
2531
 
2532
                  if (isvar (&opP->disp))
2533
                    {
2534
                      if (opP->reg == PC)
2535
                        {
2536
                          add_fix ('w', &opP->disp, 1, 0);
2537
                        }
2538
                      else
2539
                        add_fix ('w', &opP->disp, 0, 0);
2540
                    }
2541
                }
2542
              addword (nextword);
2543
              break;
2544
 
2545
            case POST:
2546
            case PRE:
2547
            case BASE:
2548
              nextword = 0;
2549
              baseo = get_num (&opP->disp, 90);
2550
              if (opP->mode == POST || opP->mode == PRE)
2551
                outro = get_num (&opP->odisp, 90);
2552
              /* Figure out the `addressing mode'.
2553
                 Also turn on the BASE_DISABLE bit, if needed.  */
2554
              if (opP->reg == PC || opP->reg == ZPC)
2555
                {
2556
                  tmpreg = 0x3b;        /* 7.3 */
2557
                  if (opP->reg == ZPC)
2558
                    nextword |= 0x80;
2559
                }
2560
              else if (opP->reg == 0)
2561
                {
2562
                  nextword |= 0x80;
2563
                  tmpreg = 0x30;        /* 6.garbage */
2564
                }
2565
              else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2566
                {
2567
                  nextword |= 0x80;
2568
                  tmpreg = 0x30 + opP->reg - ZADDR0;
2569
                }
2570
              else
2571
                tmpreg = 0x30 + opP->reg - ADDR;        /* 6.areg */
2572
 
2573
              siz1 = opP->disp.size;
2574
              if (opP->mode == POST || opP->mode == PRE)
2575
                siz2 = opP->odisp.size;
2576
              else
2577
                siz2 = SIZE_UNSPEC;
2578
 
2579
              /* Index register stuff.  */
2580
              if (opP->index.reg != 0
2581
                  && opP->index.reg >= DATA
2582
                  && opP->index.reg <= ADDR7)
2583
                {
2584
                  nextword |= (opP->index.reg - DATA) << 12;
2585
 
2586
                  if (opP->index.size == SIZE_LONG
2587
                      || (opP->index.size == SIZE_UNSPEC
2588
                          && m68k_index_width_default == SIZE_LONG))
2589
                    nextword |= 0x800;
2590
 
2591
                  if ((opP->index.scale != 1
2592
                       && cpu_of_arch (current_architecture) < m68020)
2593
                      || (opP->index.scale == 8
2594
                          && (arch_coldfire_p (current_architecture)
2595
                              && !arch_coldfire_fpu (current_architecture))))
2596
                    {
2597
                      opP->error =
2598
                        _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2599
                    }
2600
 
2601
                  if (arch_coldfire_p (current_architecture)
2602
                      && opP->index.size == SIZE_WORD)
2603
                    opP->error = _("invalid index size for coldfire");
2604
 
2605
                  switch (opP->index.scale)
2606
                    {
2607
                    case 1:
2608
                      break;
2609
                    case 2:
2610
                      nextword |= 0x200;
2611
                      break;
2612
                    case 4:
2613
                      nextword |= 0x400;
2614
                      break;
2615
                    case 8:
2616
                      nextword |= 0x600;
2617
                      break;
2618
                    default:
2619
                      abort ();
2620
                    }
2621
                  /* IF its simple,
2622
                     GET US OUT OF HERE! */
2623
 
2624
                  /* Must be INDEX, with an index register.  Address
2625
                     register cannot be ZERO-PC, and either :b was
2626
                     forced, or we know it will fit.  For a 68000 or
2627
                     68010, force this mode anyways, because the
2628
                     larger modes aren't supported.  */
2629
                  if (opP->mode == BASE
2630
                      && ((opP->reg >= ADDR0
2631
                           && opP->reg <= ADDR7)
2632
                          || opP->reg == PC))
2633
                    {
2634
                      if (siz1 == SIZE_BYTE
2635
                          || cpu_of_arch (current_architecture) < m68020
2636
                          || arch_coldfire_p (current_architecture)
2637
                          || (siz1 == SIZE_UNSPEC
2638
                              && ! isvar (&opP->disp)
2639
                              && issbyte (baseo)))
2640
                        {
2641
                          nextword += baseo & 0xff;
2642
                          addword (nextword);
2643
                          if (isvar (&opP->disp))
2644
                            {
2645
                              /* Do a byte relocation.  If it doesn't
2646
                                 fit (possible on m68000) let the
2647
                                 fixup processing complain later.  */
2648
                              if (opP->reg == PC)
2649
                                add_fix ('B', &opP->disp, 1, 1);
2650
                              else
2651
                                add_fix ('B', &opP->disp, 0, 0);
2652
                            }
2653
                          else if (siz1 != SIZE_BYTE)
2654
                            {
2655
                              if (siz1 != SIZE_UNSPEC)
2656
                                as_warn (_("Forcing byte displacement"));
2657
                              if (! issbyte (baseo))
2658
                                opP->error = _("byte displacement out of range");
2659
                            }
2660
 
2661
                          break;
2662
                        }
2663
                      else if (siz1 == SIZE_UNSPEC
2664
                               && opP->reg == PC
2665
                               && isvar (&opP->disp)
2666
                               && subs (&opP->disp) == NULL
2667
#ifdef OBJ_ELF
2668
                               /* If the displacement needs pic
2669
                                  relocation it cannot be relaxed.  */
2670
                               && opP->disp.pic_reloc == pic_none
2671
#endif
2672
                               )
2673
                        {
2674
                          /* The code in md_convert_frag_1 needs to be
2675
                             able to adjust nextword.  Call frag_grow
2676
                             to ensure that we have enough space in
2677
                             the frag obstack to make all the bytes
2678
                             contiguous.  */
2679
                          frag_grow (14);
2680
                          nextword += baseo & 0xff;
2681
                          addword (nextword);
2682
                          add_frag (adds (&opP->disp),
2683
                                    SEXT (offs (&opP->disp)),
2684
                                    TAB (PCINDEX, SZ_UNDEF));
2685
 
2686
                          break;
2687
                        }
2688
                    }
2689
                }
2690
              else
2691
                {
2692
                  nextword |= 0x40;     /* No index reg.  */
2693
                  if (opP->index.reg >= ZDATA0
2694
                      && opP->index.reg <= ZDATA7)
2695
                    nextword |= (opP->index.reg - ZDATA0) << 12;
2696
                  else if (opP->index.reg >= ZADDR0
2697
                           || opP->index.reg <= ZADDR7)
2698
                    nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2699
                }
2700
 
2701
              /* It isn't simple.  */
2702
 
2703
              if (cpu_of_arch (current_architecture) < m68020
2704
                  || arch_coldfire_p (current_architecture))
2705
                opP->error =
2706
                  _("invalid operand mode for this architecture; needs 68020 or higher");
2707
 
2708
              nextword |= 0x100;
2709
              /* If the guy specified a width, we assume that it is
2710
                 wide enough.  Maybe it isn't.  If so, we lose.  */
2711
              switch (siz1)
2712
                {
2713
                case SIZE_UNSPEC:
2714
                  if (isvar (&opP->disp)
2715
                      ? m68k_rel32
2716
                      : ! issword (baseo))
2717
                    {
2718
                      siz1 = SIZE_LONG;
2719
                      nextword |= 0x30;
2720
                    }
2721
                  else if (! isvar (&opP->disp) && baseo == 0)
2722
                    nextword |= 0x10;
2723
                  else
2724
                    {
2725
                      nextword |= 0x20;
2726
                      siz1 = SIZE_WORD;
2727
                    }
2728
                  break;
2729
                case SIZE_BYTE:
2730
                  as_warn (_(":b not permitted; defaulting to :w"));
2731
                  /* Fall through.  */
2732
                case SIZE_WORD:
2733
                  nextword |= 0x20;
2734
                  break;
2735
                case SIZE_LONG:
2736
                  nextword |= 0x30;
2737
                  break;
2738
                }
2739
 
2740
              /* Figure out inner displacement stuff.  */
2741
              if (opP->mode == POST || opP->mode == PRE)
2742
                {
2743
                  if (cpu_of_arch (current_architecture) & cpu32)
2744
                    opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2745
                  switch (siz2)
2746
                    {
2747
                    case SIZE_UNSPEC:
2748
                      if (isvar (&opP->odisp)
2749
                          ? m68k_rel32
2750
                          : ! issword (outro))
2751
                        {
2752
                          siz2 = SIZE_LONG;
2753
                          nextword |= 0x3;
2754
                        }
2755
                      else if (! isvar (&opP->odisp) && outro == 0)
2756
                        nextword |= 0x1;
2757
                      else
2758
                        {
2759
                          nextword |= 0x2;
2760
                          siz2 = SIZE_WORD;
2761
                        }
2762
                      break;
2763
                    case 1:
2764
                      as_warn (_(":b not permitted; defaulting to :w"));
2765
                      /* Fall through.  */
2766
                    case 2:
2767
                      nextword |= 0x2;
2768
                      break;
2769
                    case 3:
2770
                      nextword |= 0x3;
2771
                      break;
2772
                    }
2773
                  if (opP->mode == POST
2774
                      && (nextword & 0x40) == 0)
2775
                    nextword |= 0x04;
2776
                }
2777
              addword (nextword);
2778
 
2779
              if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2780
                {
2781
                  if (opP->reg == PC || opP->reg == ZPC)
2782
                    add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2783
                  else
2784
                    add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2785
                }
2786
              if (siz1 == SIZE_LONG)
2787
                addword (baseo >> 16);
2788
              if (siz1 != SIZE_UNSPEC)
2789
                addword (baseo);
2790
 
2791
              if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2792
                add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2793
              if (siz2 == SIZE_LONG)
2794
                addword (outro >> 16);
2795
              if (siz2 != SIZE_UNSPEC)
2796
                addword (outro);
2797
 
2798
              break;
2799
 
2800
            case ABSL:
2801
              nextword = get_num (&opP->disp, 90);
2802
              switch (opP->disp.size)
2803
                {
2804
                default:
2805
                  abort ();
2806
                case SIZE_UNSPEC:
2807
                  if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2808
                    {
2809
                      tmpreg = 0x38;    /* 7.0 */
2810
                      addword (nextword);
2811
                      break;
2812
                    }
2813
                  if (isvar (&opP->disp)
2814
                      && !subs (&opP->disp)
2815
                      && adds (&opP->disp)
2816
#ifdef OBJ_ELF
2817
                      /* If the displacement needs pic relocation it
2818
                         cannot be relaxed.  */
2819
                      && opP->disp.pic_reloc == pic_none
2820
#endif
2821
                      && !flag_long_jumps
2822
                      && !strchr ("~%&$?", s[0]))
2823
                    {
2824
                      tmpreg = 0x3A;    /* 7.2 */
2825
                      add_frag (adds (&opP->disp),
2826
                                SEXT (offs (&opP->disp)),
2827
                                TAB (ABSTOPCREL, SZ_UNDEF));
2828
                      break;
2829
                    }
2830
                  /* Fall through into long.  */
2831
                case SIZE_LONG:
2832
                  if (isvar (&opP->disp))
2833
                    add_fix ('l', &opP->disp, 0, 0);
2834
 
2835
                  tmpreg = 0x39;/* 7.1 mode */
2836
                  addword (nextword >> 16);
2837
                  addword (nextword);
2838
                  break;
2839
 
2840
                case SIZE_BYTE:
2841
                  as_bad (_("unsupported byte value; use a different suffix"));
2842
                  /* Fall through.  */
2843
 
2844
                case SIZE_WORD:
2845
                  if (isvar (&opP->disp))
2846
                    add_fix ('w', &opP->disp, 0, 0);
2847
 
2848
                  tmpreg = 0x38;/* 7.0 mode */
2849
                  addword (nextword);
2850
                  break;
2851
                }
2852
              break;
2853
            case CONTROL:
2854
            case FPREG:
2855
            default:
2856
              as_bad (_("unknown/incorrect operand"));
2857
              /* abort (); */
2858
            }
2859
 
2860
          /* If s[0] is '4', then this is for the mac instructions
2861
             that can have a trailing_ampersand set.  If so, set 0x100
2862
             bit on tmpreg so install_gen_operand can check for it and
2863
             set the appropriate bit (word2, bit 5).  */
2864
          if (s[0] == '4')
2865
            {
2866
              if (opP->trailing_ampersand)
2867
                tmpreg |= 0x100;
2868
            }
2869
          install_gen_operand (s[1], tmpreg);
2870
          break;
2871
 
2872
        case '#':
2873
        case '^':
2874
          switch (s[1])
2875
            {                   /* JF: I hate floating point! */
2876
            case 'j':
2877
              tmpreg = 70;
2878
              break;
2879
            case '8':
2880
              tmpreg = 20;
2881
              break;
2882
            case 'C':
2883
              tmpreg = 50;
2884
              break;
2885
            case '3':
2886
            default:
2887
              tmpreg = 90;
2888
              break;
2889
            }
2890
          tmpreg = get_num (&opP->disp, tmpreg);
2891
          if (isvar (&opP->disp))
2892
            add_fix (s[1], &opP->disp, 0, 0);
2893
          switch (s[1])
2894
            {
2895
            case 'b':           /* Danger:  These do no check for
2896
                                   certain types of overflow.
2897
                                   user beware! */
2898
              if (!isbyte (tmpreg))
2899
                opP->error = _("out of range");
2900
              insop (tmpreg, opcode);
2901
              if (isvar (&opP->disp))
2902
                the_ins.reloc[the_ins.nrel - 1].n =
2903
                  (opcode->m_codenum) * 2 + 1;
2904
              break;
2905
            case 'B':
2906
              if (!issbyte (tmpreg))
2907
                opP->error = _("out of range");
2908
              the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2909
              if (isvar (&opP->disp))
2910
                the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2911
              break;
2912
            case 'w':
2913
              if (!isword (tmpreg))
2914
                opP->error = _("out of range");
2915
              insop (tmpreg, opcode);
2916
              if (isvar (&opP->disp))
2917
                the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2918
              break;
2919
            case 'W':
2920
              if (!issword (tmpreg))
2921
                opP->error = _("out of range");
2922
              insop (tmpreg, opcode);
2923
              if (isvar (&opP->disp))
2924
                the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2925
              break;
2926
            case 'l':
2927
              /* Because of the way insop works, we put these two out
2928
                 backwards.  */
2929
              insop (tmpreg, opcode);
2930
              insop (tmpreg >> 16, opcode);
2931
              if (isvar (&opP->disp))
2932
                the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2933
              break;
2934
            case '3':
2935
              tmpreg &= 0xFF;
2936
            case '8':
2937
            case 'C':
2938
            case 'j':
2939
              install_operand (s[1], tmpreg);
2940
              break;
2941
            default:
2942
              abort ();
2943
            }
2944
          break;
2945
 
2946
        case '+':
2947
        case '-':
2948
        case 'A':
2949
        case 'a':
2950
          install_operand (s[1], opP->reg - ADDR);
2951
          break;
2952
 
2953
        case 'B':
2954
          tmpreg = get_num (&opP->disp, 90);
2955
 
2956
          switch (s[1])
2957
            {
2958
            case 'B':
2959
              add_fix ('B', &opP->disp, 1, -1);
2960
              break;
2961
            case 'W':
2962
              add_fix ('w', &opP->disp, 1, 0);
2963
              addword (0);
2964
              break;
2965
            case 'L':
2966
            long_branch:
2967
              the_ins.opcode[0] |= 0xff;
2968
              add_fix ('l', &opP->disp, 1, 0);
2969
              addword (0);
2970
              addword (0);
2971
              break;
2972
            case 'g': /* Conditional branch */
2973
              have_disp = HAVE_LONG_CALL (current_architecture);
2974
              goto var_branch;
2975
 
2976
            case 'b': /* Unconditional branch */
2977
              have_disp = HAVE_LONG_BRANCH (current_architecture);
2978
              use_pl = LONG_BRANCH_VIA_COND (current_architecture);
2979
              goto var_branch;
2980
 
2981
            case 's': /* Unconditional subroutine */
2982
              have_disp = HAVE_LONG_CALL (current_architecture);
2983
 
2984
              var_branch:
2985
              if (subs (&opP->disp)     /* We can't relax it.  */
2986
#ifdef OBJ_ELF
2987
                  /* If the displacement needs pic relocation it cannot be
2988
                     relaxed.  */
2989
                  || opP->disp.pic_reloc != pic_none
2990
#endif
2991
                  || 0)
2992
                {
2993
                  if (!have_disp)
2994
                    as_warn (_("Can't use long branches on this architecture"));
2995
                  goto long_branch;
2996
                }
2997
 
2998
              /* This could either be a symbol, or an absolute
2999
                 address.  If it's an absolute address, turn it into
3000
                 an absolute jump right here and keep it out of the
3001
                 relaxer.  */
3002
              if (adds (&opP->disp) == 0)
3003
                {
3004
                  if (the_ins.opcode[0] == 0x6000)       /* jbra */
3005
                    the_ins.opcode[0] = 0x4EF9;
3006
                  else if (the_ins.opcode[0] == 0x6100)  /* jbsr */
3007
                    the_ins.opcode[0] = 0x4EB9;
3008
                  else                                  /* jCC */
3009
                    {
3010
                      the_ins.opcode[0] ^= 0x0100;
3011
                      the_ins.opcode[0] |= 0x0006;
3012
                      addword (0x4EF9);
3013
                    }
3014
                  add_fix ('l', &opP->disp, 0, 0);
3015
                  addword (0);
3016
                  addword (0);
3017
                  break;
3018
                }
3019
 
3020
              /* Now we know it's going into the relaxer.  Now figure
3021
                 out which mode.  We try in this order of preference:
3022
                 long branch, absolute jump, byte/word branches only.  */
3023
              if (have_disp)
3024
                add_frag (adds (&opP->disp),
3025
                          SEXT (offs (&opP->disp)),
3026
                          TAB (BRANCHBWL, SZ_UNDEF));
3027
              else if (! flag_keep_pcrel)
3028
                {
3029
                  if ((the_ins.opcode[0] == 0x6000)
3030
                      || (the_ins.opcode[0] == 0x6100))
3031
                    add_frag (adds (&opP->disp),
3032
                              SEXT (offs (&opP->disp)),
3033
                              TAB (BRABSJUNC, SZ_UNDEF));
3034
                  else
3035
                    add_frag (adds (&opP->disp),
3036
                              SEXT (offs (&opP->disp)),
3037
                              TAB (BRABSJCOND, SZ_UNDEF));
3038
                }
3039
              else
3040
                add_frag (adds (&opP->disp),
3041
                          SEXT (offs (&opP->disp)),
3042
                          (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3043
                           : TAB (BRANCHBW, SZ_UNDEF)));
3044
              break;
3045
            case 'w':
3046
              if (isvar (&opP->disp))
3047
                {
3048
                  /* Check for DBcc instructions.  We can relax them,
3049
                     but only if we have long branches and/or absolute
3050
                     jumps.  */
3051
                  if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3052
                      && (HAVE_LONG_BRANCH (current_architecture)
3053
                          || ! flag_keep_pcrel))
3054
                    {
3055
                      if (HAVE_LONG_BRANCH (current_architecture))
3056
                        add_frag (adds (&opP->disp),
3057
                                  SEXT (offs (&opP->disp)),
3058
                                  TAB (DBCCLBR, SZ_UNDEF));
3059
                      else
3060
                        add_frag (adds (&opP->disp),
3061
                                  SEXT (offs (&opP->disp)),
3062
                                  TAB (DBCCABSJ, SZ_UNDEF));
3063
                      break;
3064
                    }
3065
                  add_fix ('w', &opP->disp, 1, 0);
3066
                }
3067
              addword (0);
3068
              break;
3069
            case 'C':           /* Fixed size LONG coproc branches.  */
3070
              add_fix ('l', &opP->disp, 1, 0);
3071
              addword (0);
3072
              addword (0);
3073
              break;
3074
            case 'c':           /* Var size Coprocesssor branches.  */
3075
              if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3076
                {
3077
                  the_ins.opcode[the_ins.numo - 1] |= 0x40;
3078
                  add_fix ('l', &opP->disp, 1, 0);
3079
                  addword (0);
3080
                  addword (0);
3081
                }
3082
              else
3083
                add_frag (adds (&opP->disp),
3084
                          SEXT (offs (&opP->disp)),
3085
                          TAB (FBRANCH, SZ_UNDEF));
3086
              break;
3087
            default:
3088
              abort ();
3089
            }
3090
          break;
3091
 
3092
        case 'C':               /* Ignore it.  */
3093
          break;
3094
 
3095
        case 'd':               /* JF this is a kludge.  */
3096
          install_operand ('s', opP->reg - ADDR);
3097
          tmpreg = get_num (&opP->disp, 90);
3098
          if (!issword (tmpreg))
3099
            {
3100
              as_warn (_("Expression out of range, using 0"));
3101
              tmpreg = 0;
3102
            }
3103
          addword (tmpreg);
3104
          break;
3105
 
3106
        case 'D':
3107
          install_operand (s[1], opP->reg - DATA);
3108
          break;
3109
 
3110
        case 'e':  /* EMAC ACCx, reg/reg.  */
3111
          install_operand (s[1], opP->reg - ACC);
3112
          break;
3113
 
3114
        case 'E':               /* Ignore it.  */
3115
          break;
3116
 
3117
        case 'F':
3118
          install_operand (s[1], opP->reg - FP0);
3119
          break;
3120
 
3121
        case 'g':  /* EMAC ACCEXTx.  */
3122
          install_operand (s[1], opP->reg - ACCEXT01);
3123
          break;
3124
 
3125
        case 'G':               /* Ignore it.  */
3126
        case 'H':
3127
          break;
3128
 
3129
        case 'I':
3130
          tmpreg = opP->reg - COP0;
3131
          install_operand (s[1], tmpreg);
3132
          break;
3133
 
3134
        case 'i':  /* MAC/EMAC scale factor.  */
3135
          install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3136
          break;
3137
 
3138
        case 'J':               /* JF foo.  */
3139
          switch (opP->reg)
3140
            {
3141
            case SFC:
3142
              tmpreg = 0x000;
3143
              break;
3144
            case DFC:
3145
              tmpreg = 0x001;
3146
              break;
3147
            case CACR:
3148
              tmpreg = 0x002;
3149
              break;
3150
            case TC:
3151
            case ASID:
3152
              tmpreg = 0x003;
3153
              break;
3154
            case ACR0:
3155
            case ITT0:
3156
              tmpreg = 0x004;
3157
              break;
3158
            case ACR1:
3159
            case ITT1:
3160
              tmpreg = 0x005;
3161
              break;
3162
            case ACR2:
3163
            case DTT0:
3164
              tmpreg = 0x006;
3165
              break;
3166
            case ACR3:
3167
            case DTT1:
3168
              tmpreg = 0x007;
3169
              break;
3170
            case BUSCR:
3171
            case MMUBAR:
3172
              tmpreg = 0x008;
3173
              break;
3174
 
3175
            case USP:
3176
              tmpreg = 0x800;
3177
              break;
3178
            case VBR:
3179
              tmpreg = 0x801;
3180
              break;
3181
            case CAAR:
3182
              tmpreg = 0x802;
3183
              break;
3184
            case MSP:
3185
              tmpreg = 0x803;
3186
              break;
3187
            case ISP:
3188
              tmpreg = 0x804;
3189
              break;
3190
            case MMUSR:
3191
              tmpreg = 0x805;
3192
              break;
3193
            case URP:
3194
              tmpreg = 0x806;
3195
              break;
3196
            case SRP:
3197
              tmpreg = 0x807;
3198
              break;
3199
            case PCR:
3200
              tmpreg = 0x808;
3201
              break;
3202
            case ROMBAR:
3203
            case ROMBAR0:
3204
              tmpreg = 0xC00;
3205
              break;
3206
            case ROMBAR1:
3207
              tmpreg = 0xC01;
3208
              break;
3209
            case FLASHBAR:
3210
            case RAMBAR0:
3211
            case RAMBAR_ALT:
3212
              tmpreg = 0xC04;
3213
              break;
3214
            case RAMBAR:
3215
            case RAMBAR1:
3216
              tmpreg = 0xC05;
3217
              break;
3218
            case MPCR:
3219
              tmpreg = 0xC0C;
3220
              break;
3221
            case EDRAMBAR:
3222
              tmpreg = 0xC0D;
3223
              break;
3224
            case MBAR0:
3225
            case MBAR2:
3226
            case SECMBAR:
3227
              tmpreg = 0xC0E;
3228
              break;
3229
            case MBAR1:
3230
            case MBAR:
3231
              tmpreg = 0xC0F;
3232
              break;
3233
            case PCR1U0:
3234
              tmpreg = 0xD02;
3235
              break;
3236
            case PCR1L0:
3237
              tmpreg = 0xD03;
3238
              break;
3239
            case PCR2U0:
3240
              tmpreg = 0xD04;
3241
              break;
3242
            case PCR2L0:
3243
              tmpreg = 0xD05;
3244
              break;
3245
            case PCR3U0:
3246
              tmpreg = 0xD06;
3247
              break;
3248
            case PCR3L0:
3249
              tmpreg = 0xD07;
3250
              break;
3251
            case PCR1L1:
3252
              tmpreg = 0xD0A;
3253
              break;
3254
            case PCR1U1:
3255
              tmpreg = 0xD0B;
3256
              break;
3257
            case PCR2L1:
3258
              tmpreg = 0xD0C;
3259
              break;
3260
            case PCR2U1:
3261
              tmpreg = 0xD0D;
3262
              break;
3263
            case PCR3L1:
3264
              tmpreg = 0xD0E;
3265
              break;
3266
            case PCR3U1:
3267
              tmpreg = 0xD0F;
3268
              break;
3269
            case CAC:
3270
              tmpreg = 0xFFE;
3271
              break;
3272
            case MBO:
3273
              tmpreg = 0xFFF;
3274
              break;
3275
            default:
3276
              abort ();
3277
            }
3278
          install_operand (s[1], tmpreg);
3279
          break;
3280
 
3281
        case 'k':
3282
          tmpreg = get_num (&opP->disp, 55);
3283
          install_operand (s[1], tmpreg & 0x7f);
3284
          break;
3285
 
3286
        case 'l':
3287
          tmpreg = opP->mask;
3288
          if (s[1] == 'w')
3289
            {
3290
              if (tmpreg & 0x7FF0000)
3291
                as_bad (_("Floating point register in register list"));
3292
              insop (reverse_16_bits (tmpreg), opcode);
3293
            }
3294
          else
3295
            {
3296
              if (tmpreg & 0x700FFFF)
3297
                as_bad (_("Wrong register in floating-point reglist"));
3298
              install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3299
            }
3300
          break;
3301
 
3302
        case 'L':
3303
          tmpreg = opP->mask;
3304
          if (s[1] == 'w')
3305
            {
3306
              if (tmpreg & 0x7FF0000)
3307
                as_bad (_("Floating point register in register list"));
3308
              insop (tmpreg, opcode);
3309
            }
3310
          else if (s[1] == '8')
3311
            {
3312
              if (tmpreg & 0x0FFFFFF)
3313
                as_bad (_("incorrect register in reglist"));
3314
              install_operand (s[1], tmpreg >> 24);
3315
            }
3316
          else
3317
            {
3318
              if (tmpreg & 0x700FFFF)
3319
                as_bad (_("wrong register in floating-point reglist"));
3320
              else
3321
                install_operand (s[1], tmpreg >> 16);
3322
            }
3323
          break;
3324
 
3325
        case 'M':
3326
          install_operand (s[1], get_num (&opP->disp, 60));
3327
          break;
3328
 
3329
        case 'O':
3330
          tmpreg = ((opP->mode == DREG)
3331
                    ? 0x20 + (int) (opP->reg - DATA)
3332
                    : (get_num (&opP->disp, 40) & 0x1F));
3333
          install_operand (s[1], tmpreg);
3334
          break;
3335
 
3336
        case 'Q':
3337
          tmpreg = get_num (&opP->disp, 10);
3338
          if (tmpreg == 8)
3339
            tmpreg = 0;
3340
          install_operand (s[1], tmpreg);
3341
          break;
3342
 
3343
        case 'R':
3344
          /* This depends on the fact that ADDR registers are eight
3345
             more than their corresponding DATA regs, so the result
3346
             will have the ADDR_REG bit set.  */
3347
          install_operand (s[1], opP->reg - DATA);
3348
          break;
3349
 
3350
        case 'r':
3351
          if (opP->mode == AINDR)
3352
            install_operand (s[1], opP->reg - DATA);
3353
          else
3354
            install_operand (s[1], opP->index.reg - DATA);
3355
          break;
3356
 
3357
        case 's':
3358
          if (opP->reg == FPI)
3359
            tmpreg = 0x1;
3360
          else if (opP->reg == FPS)
3361
            tmpreg = 0x2;
3362
          else if (opP->reg == FPC)
3363
            tmpreg = 0x4;
3364
          else
3365
            abort ();
3366
          install_operand (s[1], tmpreg);
3367
          break;
3368
 
3369
        case 'S':               /* Ignore it.  */
3370
          break;
3371
 
3372
        case 'T':
3373
          install_operand (s[1], get_num (&opP->disp, 30));
3374
          break;
3375
 
3376
        case 'U':               /* Ignore it.  */
3377
          break;
3378
 
3379
        case 'c':
3380
          switch (opP->reg)
3381
            {
3382
            case NC:
3383
              tmpreg = 0;
3384
              break;
3385
            case DC:
3386
              tmpreg = 1;
3387
              break;
3388
            case IC:
3389
              tmpreg = 2;
3390
              break;
3391
            case BC:
3392
              tmpreg = 3;
3393
              break;
3394
            default:
3395
              as_fatal (_("failed sanity check"));
3396
            }                   /* switch on cache token.  */
3397
          install_operand (s[1], tmpreg);
3398
          break;
3399
#ifndef NO_68851
3400
          /* JF: These are out of order, I fear.  */
3401
        case 'f':
3402
          switch (opP->reg)
3403
            {
3404
            case SFC:
3405
              tmpreg = 0;
3406
              break;
3407
            case DFC:
3408
              tmpreg = 1;
3409
              break;
3410
            default:
3411
              abort ();
3412
            }
3413
          install_operand (s[1], tmpreg);
3414
          break;
3415
 
3416
        case '0':
3417
        case '1':
3418
        case '2':
3419
          switch (opP->reg)
3420
            {
3421
            case TC:
3422
              tmpreg = 0;
3423
              break;
3424
            case CAL:
3425
              tmpreg = 4;
3426
              break;
3427
            case VAL:
3428
              tmpreg = 5;
3429
              break;
3430
            case SCC:
3431
              tmpreg = 6;
3432
              break;
3433
            case AC:
3434
              tmpreg = 7;
3435
              break;
3436
            default:
3437
              abort ();
3438
            }
3439
          install_operand (s[1], tmpreg);
3440
          break;
3441
 
3442
        case 'V':
3443
          if (opP->reg == VAL)
3444
            break;
3445
          abort ();
3446
 
3447
        case 'W':
3448
          switch (opP->reg)
3449
            {
3450
            case DRP:
3451
              tmpreg = 1;
3452
              break;
3453
            case SRP:
3454
              tmpreg = 2;
3455
              break;
3456
            case CRP:
3457
              tmpreg = 3;
3458
              break;
3459
            default:
3460
              abort ();
3461
            }
3462
          install_operand (s[1], tmpreg);
3463
          break;
3464
 
3465
        case 'X':
3466
          switch (opP->reg)
3467
            {
3468
            case BAD:
3469
            case BAD + 1:
3470
            case BAD + 2:
3471
            case BAD + 3:
3472
            case BAD + 4:
3473
            case BAD + 5:
3474
            case BAD + 6:
3475
            case BAD + 7:
3476
              tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3477
              break;
3478
 
3479
            case BAC:
3480
            case BAC + 1:
3481
            case BAC + 2:
3482
            case BAC + 3:
3483
            case BAC + 4:
3484
            case BAC + 5:
3485
            case BAC + 6:
3486
            case BAC + 7:
3487
              tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3488
              break;
3489
 
3490
            default:
3491
              abort ();
3492
            }
3493
          install_operand (s[1], tmpreg);
3494
          break;
3495
        case 'Y':
3496
          know (opP->reg == PSR);
3497
          break;
3498
        case 'Z':
3499
          know (opP->reg == PCSR);
3500
          break;
3501
#endif /* m68851 */
3502
        case '3':
3503
          switch (opP->reg)
3504
            {
3505
            case TT0:
3506
              tmpreg = 2;
3507
              break;
3508
            case TT1:
3509
              tmpreg = 3;
3510
              break;
3511
            default:
3512
              abort ();
3513
            }
3514
          install_operand (s[1], tmpreg);
3515
          break;
3516
        case 't':
3517
          tmpreg = get_num (&opP->disp, 20);
3518
          install_operand (s[1], tmpreg);
3519
          break;
3520
        case '_':       /* used only for move16 absolute 32-bit address.  */
3521
          if (isvar (&opP->disp))
3522
            add_fix ('l', &opP->disp, 0, 0);
3523
          tmpreg = get_num (&opP->disp, 90);
3524
          addword (tmpreg >> 16);
3525
          addword (tmpreg & 0xFFFF);
3526
          break;
3527
        case 'u':
3528
          install_operand (s[1], opP->reg - DATA0L);
3529
          opP->reg -= (DATA0L);
3530
          opP->reg &= 0x0F;     /* remove upper/lower bit.  */
3531
          break;
3532
        case 'x':
3533
          tmpreg = get_num (&opP->disp, 80);
3534
          if (tmpreg == -1)
3535
            tmpreg = 0;
3536
          install_operand (s[1], tmpreg);
3537
          break;
3538
        case 'j':
3539
          tmpreg = get_num (&opP->disp, 10);
3540
          install_operand (s[1], tmpreg - 1);
3541
          break;
3542
        case 'K':
3543
          tmpreg = get_num (&opP->disp, 65);
3544
          install_operand (s[1], tmpreg);
3545
          break;
3546
        default:
3547
          abort ();
3548
        }
3549
    }
3550
 
3551
  /* By the time whe get here (FINALLY) the_ins contains the complete
3552
     instruction, ready to be emitted. . .  */
3553
}
3554
 
3555
static int
3556
reverse_16_bits (int in)
3557
{
3558
  int out = 0;
3559
  int n;
3560
 
3561
  static int mask[16] =
3562
  {
3563
    0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3564
    0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3565
  };
3566
  for (n = 0; n < 16; n++)
3567
    {
3568
      if (in & mask[n])
3569
        out |= mask[15 - n];
3570
    }
3571
  return out;
3572
}                               /* reverse_16_bits() */
3573
 
3574
static int
3575
reverse_8_bits (int in)
3576
{
3577
  int out = 0;
3578
  int n;
3579
 
3580
  static int mask[8] =
3581
  {
3582
    0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3583
  };
3584
 
3585
  for (n = 0; n < 8; n++)
3586
    {
3587
      if (in & mask[n])
3588
        out |= mask[7 - n];
3589
    }
3590
  return out;
3591
}                               /* reverse_8_bits() */
3592
 
3593
/* Cause an extra frag to be generated here, inserting up to
3594
   FRAG_VAR_SIZE bytes.  TYPE is the subtype of the frag to be
3595
   generated; its primary type is rs_machine_dependent.
3596
 
3597
   The TYPE parameter is also used by md_convert_frag_1 and
3598
   md_estimate_size_before_relax.  The appropriate type of fixup will
3599
   be emitted by md_convert_frag_1.
3600
 
3601
   ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET.  */
3602
static void
3603
install_operand (int mode, int val)
3604
{
3605
  switch (mode)
3606
    {
3607
    case 's':
3608
      the_ins.opcode[0] |= val & 0xFF;   /* JF FF is for M kludge.  */
3609
      break;
3610
    case 'd':
3611
      the_ins.opcode[0] |= val << 9;
3612
      break;
3613
    case 'E':
3614
      the_ins.opcode[1] |= val << 9;
3615
      break;
3616
    case '1':
3617
      the_ins.opcode[1] |= val << 12;
3618
      break;
3619
    case '2':
3620
      the_ins.opcode[1] |= val << 6;
3621
      break;
3622
    case '3':
3623
      the_ins.opcode[1] |= val;
3624
      break;
3625
    case '4':
3626
      the_ins.opcode[2] |= val << 12;
3627
      break;
3628
    case '5':
3629
      the_ins.opcode[2] |= val << 6;
3630
      break;
3631
    case '6':
3632
      /* DANGER!  This is a hack to force cas2l and cas2w cmds to be
3633
         three words long! */
3634
      the_ins.numo++;
3635
      the_ins.opcode[2] |= val;
3636
      break;
3637
    case '7':
3638
      the_ins.opcode[1] |= val << 7;
3639
      break;
3640
    case '8':
3641
      the_ins.opcode[1] |= val << 10;
3642
      break;
3643
#ifndef NO_68851
3644
    case '9':
3645
      the_ins.opcode[1] |= val << 5;
3646
      break;
3647
#endif
3648
 
3649
    case 't':
3650
      the_ins.opcode[1] |= (val << 10) | (val << 7);
3651
      break;
3652
    case 'D':
3653
      the_ins.opcode[1] |= (val << 12) | val;
3654
      break;
3655
    case 'g':
3656
      the_ins.opcode[0] |= val = 0xff;
3657
      break;
3658
    case 'i':
3659
      the_ins.opcode[0] |= val << 9;
3660
      break;
3661
    case 'C':
3662
      the_ins.opcode[1] |= val;
3663
      break;
3664
    case 'j':
3665
      the_ins.opcode[1] |= val;
3666
      the_ins.numo++;           /* What a hack.  */
3667
      break;
3668
    case 'k':
3669
      the_ins.opcode[1] |= val << 4;
3670
      break;
3671
    case 'b':
3672
    case 'w':
3673
    case 'W':
3674
    case 'l':
3675
      break;
3676
    case 'e':
3677
      the_ins.opcode[0] |= (val << 6);
3678
      break;
3679
    case 'L':
3680
      the_ins.opcode[1] = (val >> 16);
3681
      the_ins.opcode[2] = val & 0xffff;
3682
      break;
3683
    case 'm':
3684
      the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3685
      the_ins.opcode[0] |= ((val & 0x7) << 9);
3686
      the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3687
      break;
3688
    case 'n': /* MAC/EMAC Rx on !load.  */
3689
      the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3690
      the_ins.opcode[0] |= ((val & 0x7) << 9);
3691
      the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3692
      break;
3693
    case 'o': /* MAC/EMAC Rx on load.  */
3694
      the_ins.opcode[1] |= val << 12;
3695
      the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3696
      break;
3697
    case 'M': /* MAC/EMAC Ry on !load.  */
3698
      the_ins.opcode[0] |= (val & 0xF);
3699
      the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3700
      break;
3701
    case 'N': /* MAC/EMAC Ry on load.  */
3702
      the_ins.opcode[1] |= (val & 0xF);
3703
      the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3704
      break;
3705
    case 'h':
3706
      the_ins.opcode[1] |= ((val != 1) << 10);
3707
      break;
3708
    case 'F':
3709
      the_ins.opcode[0] |= ((val & 0x3) << 9);
3710
      break;
3711
    case 'f':
3712
      the_ins.opcode[0] |= ((val & 0x3) << 0);
3713
      break;
3714
    case 'G':  /* EMAC accumulator in a EMAC load instruction.  */
3715
      the_ins.opcode[0] |= ((~val & 0x1) << 7);
3716
      the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3717
      break;
3718
    case 'H':  /* EMAC accumulator in a EMAC non-load instruction.  */
3719
      the_ins.opcode[0] |= ((val & 0x1) << 7);
3720
      the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3721
      break;
3722
    case 'I':
3723
      the_ins.opcode[1] |= ((val & 0x3) << 9);
3724
      break;
3725
    case ']':
3726
      the_ins.opcode[0] |= (val & 0x1) <<10;
3727
      break;
3728
    case 'c':
3729
    default:
3730
      as_fatal (_("failed sanity check."));
3731
    }
3732
}
3733
 
3734
static void
3735
install_gen_operand (int mode, int val)
3736
{
3737
  switch (mode)
3738
    {
3739
    case '/':  /* Special for mask loads for mac/msac insns with
3740
                  possible mask; trailing_ampersend set in bit 8.  */
3741
      the_ins.opcode[0] |= (val & 0x3f);
3742
      the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3743
      break;
3744
    case 's':
3745
      the_ins.opcode[0] |= val;
3746
      break;
3747
    case 'd':
3748
      /* This is a kludge!!! */
3749
      the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3750
      break;
3751
    case 'b':
3752
    case 'w':
3753
    case 'l':
3754
    case 'f':
3755
    case 'F':
3756
    case 'x':
3757
    case 'p':
3758
      the_ins.opcode[0] |= val;
3759
      break;
3760
      /* more stuff goes here.  */
3761
    default:
3762
      as_fatal (_("failed sanity check."));
3763
    }
3764
}
3765
 
3766
/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3767
   then deal with the bitfield hack.  */
3768
 
3769
static char *
3770
crack_operand (char *str, struct m68k_op *opP)
3771
{
3772
  register int parens;
3773
  register int c;
3774
  register char *beg_str;
3775
  int inquote = 0;
3776
 
3777
  if (!str)
3778
    {
3779
      return str;
3780
    }
3781
  beg_str = str;
3782
  for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3783
    {
3784
      if (! inquote)
3785
        {
3786
          if (*str == '(')
3787
            parens++;
3788
          else if (*str == ')')
3789
            {
3790
              if (!parens)
3791
                {                       /* ERROR.  */
3792
                  opP->error = _("Extra )");
3793
                  return str;
3794
                }
3795
              --parens;
3796
            }
3797
        }
3798
      if (flag_mri && *str == '\'')
3799
        inquote = ! inquote;
3800
    }
3801
  if (!*str && parens)
3802
    {                           /* ERROR.  */
3803
      opP->error = _("Missing )");
3804
      return str;
3805
    }
3806
  c = *str;
3807
  *str = '\0';
3808
  if (m68k_ip_op (beg_str, opP) != 0)
3809
    {
3810
      *str = c;
3811
      return str;
3812
    }
3813
  *str = c;
3814
  if (c == '}')
3815
    c = *++str;                 /* JF bitfield hack.  */
3816
  if (c)
3817
    {
3818
      c = *++str;
3819
      if (!c)
3820
        as_bad (_("Missing operand"));
3821
    }
3822
 
3823
  /* Detect MRI REG symbols and convert them to REGLSTs.  */
3824
  if (opP->mode == CONTROL && (int)opP->reg < 0)
3825
    {
3826
      opP->mode = REGLST;
3827
      opP->mask = ~(int)opP->reg;
3828
      opP->reg = 0;
3829
    }
3830
 
3831
  return str;
3832
}
3833
 
3834
/* This is the guts of the machine-dependent assembler.  STR points to a
3835
   machine dependent instruction.  This function is supposed to emit
3836
   the frags/bytes it assembles to.
3837
   */
3838
 
3839
static void
3840
insert_reg (const char *regname, int regnum)
3841
{
3842
  char buf[100];
3843
  int i;
3844
 
3845
#ifdef REGISTER_PREFIX
3846
  if (!flag_reg_prefix_optional)
3847
    {
3848
      buf[0] = REGISTER_PREFIX;
3849
      strcpy (buf + 1, regname);
3850
      regname = buf;
3851
    }
3852
#endif
3853
 
3854
  symbol_table_insert (symbol_new (regname, reg_section, regnum,
3855
                                   &zero_address_frag));
3856
 
3857
  for (i = 0; regname[i]; i++)
3858
    buf[i] = TOUPPER (regname[i]);
3859
  buf[i] = '\0';
3860
 
3861
  symbol_table_insert (symbol_new (buf, reg_section, regnum,
3862
                                   &zero_address_frag));
3863
}
3864
 
3865
struct init_entry
3866
  {
3867
    const char *name;
3868
    int number;
3869
  };
3870
 
3871
static const struct init_entry init_table[] =
3872
{
3873
  { "d0", DATA0 },
3874
  { "d1", DATA1 },
3875
  { "d2", DATA2 },
3876
  { "d3", DATA3 },
3877
  { "d4", DATA4 },
3878
  { "d5", DATA5 },
3879
  { "d6", DATA6 },
3880
  { "d7", DATA7 },
3881
  { "a0", ADDR0 },
3882
  { "a1", ADDR1 },
3883
  { "a2", ADDR2 },
3884
  { "a3", ADDR3 },
3885
  { "a4", ADDR4 },
3886
  { "a5", ADDR5 },
3887
  { "a6", ADDR6 },
3888
  { "fp", ADDR6 },
3889
  { "a7", ADDR7 },
3890
  { "sp", ADDR7 },
3891
  { "ssp", ADDR7 },
3892
  { "fp0", FP0 },
3893
  { "fp1", FP1 },
3894
  { "fp2", FP2 },
3895
  { "fp3", FP3 },
3896
  { "fp4", FP4 },
3897
  { "fp5", FP5 },
3898
  { "fp6", FP6 },
3899
  { "fp7", FP7 },
3900
  { "fpi", FPI },
3901
  { "fpiar", FPI },
3902
  { "fpc", FPI },
3903
  { "fps", FPS },
3904
  { "fpsr", FPS },
3905
  { "fpc", FPC },
3906
  { "fpcr", FPC },
3907
  { "control", FPC },
3908
  { "status", FPS },
3909
  { "iaddr", FPI },
3910
 
3911
  { "cop0", COP0 },
3912
  { "cop1", COP1 },
3913
  { "cop2", COP2 },
3914
  { "cop3", COP3 },
3915
  { "cop4", COP4 },
3916
  { "cop5", COP5 },
3917
  { "cop6", COP6 },
3918
  { "cop7", COP7 },
3919
  { "pc", PC },
3920
  { "zpc", ZPC },
3921
  { "sr", SR },
3922
 
3923
  { "ccr", CCR },
3924
  { "cc", CCR },
3925
 
3926
  { "acc", ACC },
3927
  { "acc0", ACC },
3928
  { "acc1", ACC1 },
3929
  { "acc2", ACC2 },
3930
  { "acc3", ACC3 },
3931
  { "accext01", ACCEXT01 },
3932
  { "accext23", ACCEXT23 },
3933
  { "macsr", MACSR },
3934
  { "mask", MASK },
3935
 
3936
  /* Control registers.  */
3937
  { "sfc", SFC },               /* Source Function Code.  */
3938
  { "sfcr", SFC },
3939
  { "dfc", DFC },               /* Destination Function Code.  */
3940
  { "dfcr", DFC },
3941
  { "cacr", CACR },             /* Cache Control Register.  */
3942
  { "caar", CAAR },             /* Cache Address Register.  */
3943
 
3944
  { "usp", USP },               /* User Stack Pointer.  */
3945
  { "vbr", VBR },               /* Vector Base Register.  */
3946
  { "msp", MSP },               /* Master Stack Pointer.  */
3947
  { "isp", ISP },               /* Interrupt Stack Pointer.  */
3948
 
3949
  { "itt0", ITT0 },             /* Instruction Transparent Translation Reg 0.  */
3950
  { "itt1", ITT1 },             /* Instruction Transparent Translation Reg 1.  */
3951
  { "dtt0", DTT0 },             /* Data Transparent Translation Register 0.  */
3952
  { "dtt1", DTT1 },             /* Data Transparent Translation Register 1.  */
3953
 
3954
  /* 68ec040 versions of same */
3955
  { "iacr0", ITT0 },            /* Instruction Access Control Register 0.  */
3956
  { "iacr1", ITT1 },            /* Instruction Access Control Register 0.  */
3957
  { "dacr0", DTT0 },            /* Data Access Control Register 0.  */
3958
  { "dacr1", DTT1 },            /* Data Access Control Register 0.  */
3959
 
3960
  /* Coldfire versions of same.  The ColdFire programmer's reference
3961
     manual indicated that the order is 2,3,0,1, but Ken Rose
3962
     <rose@netcom.com> says that 0,1,2,3 is the correct order.  */
3963
  { "acr0", ACR0 },             /* Access Control Unit 0.  */
3964
  { "acr1", ACR1 },             /* Access Control Unit 1.  */
3965
  { "acr2", ACR2 },             /* Access Control Unit 2.  */
3966
  { "acr3", ACR3 },             /* Access Control Unit 3.  */
3967
 
3968
  { "tc", TC },                 /* MMU Translation Control Register.  */
3969
  { "tcr", TC },
3970
  { "asid", ASID },
3971
 
3972
  { "mmusr", MMUSR },           /* MMU Status Register.  */
3973
  { "srp", SRP },               /* User Root Pointer.  */
3974
  { "urp", URP },               /* Supervisor Root Pointer.  */
3975
 
3976
  { "buscr", BUSCR },
3977
  { "mmubar", MMUBAR },
3978
  { "pcr", PCR },
3979
 
3980
  { "rombar", ROMBAR },         /* ROM Base Address Register.  */
3981
  { "rambar0", RAMBAR0 },       /* ROM Base Address Register.  */
3982
  { "rambar1", RAMBAR1 },       /* ROM Base Address Register.  */
3983
  { "mbar", MBAR },             /* Module Base Address Register.  */
3984
 
3985
  { "mbar0",    MBAR0 },        /* mcfv4e registers.  */
3986
  { "mbar1",    MBAR1 },        /* mcfv4e registers.  */
3987
  { "rombar0",  ROMBAR0 },      /* mcfv4e registers.  */
3988
  { "rombar1",  ROMBAR1 },      /* mcfv4e registers.  */
3989
  { "mpcr",     MPCR },         /* mcfv4e registers.  */
3990
  { "edrambar", EDRAMBAR },     /* mcfv4e registers.  */
3991
  { "secmbar",  SECMBAR },      /* mcfv4e registers.  */
3992
  { "asid",     TC },           /* mcfv4e registers.  */
3993
  { "mmubar",   BUSCR },        /* mcfv4e registers.  */
3994
  { "pcr1u0",   PCR1U0 },       /* mcfv4e registers.  */
3995
  { "pcr1l0",   PCR1L0 },       /* mcfv4e registers.  */
3996
  { "pcr2u0",   PCR2U0 },       /* mcfv4e registers.  */
3997
  { "pcr2l0",   PCR2L0 },       /* mcfv4e registers.  */
3998
  { "pcr3u0",   PCR3U0 },       /* mcfv4e registers.  */
3999
  { "pcr3l0",   PCR3L0 },       /* mcfv4e registers.  */
4000
  { "pcr1u1",   PCR1U1 },       /* mcfv4e registers.  */
4001
  { "pcr1l1",   PCR1L1 },       /* mcfv4e registers.  */
4002
  { "pcr2u1",   PCR2U1 },       /* mcfv4e registers.  */
4003
  { "pcr2l1",   PCR2L1 },       /* mcfv4e registers.  */
4004
  { "pcr3u1",   PCR3U1 },       /* mcfv4e registers.  */
4005
  { "pcr3l1",   PCR3L1 },       /* mcfv4e registers.  */
4006
 
4007
  { "flashbar", FLASHBAR },     /* mcf528x registers.  */
4008
  { "rambar",   RAMBAR },       /* mcf528x registers.  */
4009
 
4010
  { "mbar2",    MBAR2 },        /* mcf5249 registers.  */
4011
 
4012
  { "cac",    CAC },            /* fido registers.  */
4013
  { "mbb",    MBO },            /* fido registers (obsolete).  */
4014
  { "mbo",    MBO },            /* fido registers.  */
4015
  /* End of control registers.  */
4016
 
4017
  { "ac", AC },
4018
  { "bc", BC },
4019
  { "cal", CAL },
4020
  { "crp", CRP },
4021
  { "drp", DRP },
4022
  { "pcsr", PCSR },
4023
  { "psr", PSR },
4024
  { "scc", SCC },
4025
  { "val", VAL },
4026
  { "bad0", BAD0 },
4027
  { "bad1", BAD1 },
4028
  { "bad2", BAD2 },
4029
  { "bad3", BAD3 },
4030
  { "bad4", BAD4 },
4031
  { "bad5", BAD5 },
4032
  { "bad6", BAD6 },
4033
  { "bad7", BAD7 },
4034
  { "bac0", BAC0 },
4035
  { "bac1", BAC1 },
4036
  { "bac2", BAC2 },
4037
  { "bac3", BAC3 },
4038
  { "bac4", BAC4 },
4039
  { "bac5", BAC5 },
4040
  { "bac6", BAC6 },
4041
  { "bac7", BAC7 },
4042
 
4043
  { "ic", IC },
4044
  { "dc", DC },
4045
  { "nc", NC },
4046
 
4047
  { "tt0", TT0 },
4048
  { "tt1", TT1 },
4049
  /* 68ec030 versions of same.  */
4050
  { "ac0", TT0 },
4051
  { "ac1", TT1 },
4052
  /* 68ec030 access control unit, identical to 030 MMU status reg.  */
4053
  { "acusr", PSR },
4054
 
4055
  /* Suppressed data and address registers.  */
4056
  { "zd0", ZDATA0 },
4057
  { "zd1", ZDATA1 },
4058
  { "zd2", ZDATA2 },
4059
  { "zd3", ZDATA3 },
4060
  { "zd4", ZDATA4 },
4061
  { "zd5", ZDATA5 },
4062
  { "zd6", ZDATA6 },
4063
  { "zd7", ZDATA7 },
4064
  { "za0", ZADDR0 },
4065
  { "za1", ZADDR1 },
4066
  { "za2", ZADDR2 },
4067
  { "za3", ZADDR3 },
4068
  { "za4", ZADDR4 },
4069
  { "za5", ZADDR5 },
4070
  { "za6", ZADDR6 },
4071
  { "za7", ZADDR7 },
4072
 
4073
  /* Upper and lower data and address registers, used by macw and msacw.  */
4074
  { "d0l", DATA0L },
4075
  { "d1l", DATA1L },
4076
  { "d2l", DATA2L },
4077
  { "d3l", DATA3L },
4078
  { "d4l", DATA4L },
4079
  { "d5l", DATA5L },
4080
  { "d6l", DATA6L },
4081
  { "d7l", DATA7L },
4082
 
4083
  { "a0l", ADDR0L },
4084
  { "a1l", ADDR1L },
4085
  { "a2l", ADDR2L },
4086
  { "a3l", ADDR3L },
4087
  { "a4l", ADDR4L },
4088
  { "a5l", ADDR5L },
4089
  { "a6l", ADDR6L },
4090
  { "a7l", ADDR7L },
4091
 
4092
  { "d0u", DATA0U },
4093
  { "d1u", DATA1U },
4094
  { "d2u", DATA2U },
4095
  { "d3u", DATA3U },
4096
  { "d4u", DATA4U },
4097
  { "d5u", DATA5U },
4098
  { "d6u", DATA6U },
4099
  { "d7u", DATA7U },
4100
 
4101
  { "a0u", ADDR0U },
4102
  { "a1u", ADDR1U },
4103
  { "a2u", ADDR2U },
4104
  { "a3u", ADDR3U },
4105
  { "a4u", ADDR4U },
4106
  { "a5u", ADDR5U },
4107
  { "a6u", ADDR6U },
4108
  { "a7u", ADDR7U },
4109
 
4110
  { 0, 0 }
4111
};
4112
 
4113
static void
4114
init_regtable (void)
4115
{
4116
  int i;
4117
  for (i = 0; init_table[i].name; i++)
4118
    insert_reg (init_table[i].name, init_table[i].number);
4119
}
4120
 
4121
void
4122
md_assemble (char *str)
4123
{
4124
  const char *er;
4125
  short *fromP;
4126
  char *toP = NULL;
4127
  int m, n = 0;
4128
  char *to_beg_P;
4129
  int shorts_this_frag;
4130
  fixS *fixP;
4131
 
4132
  if (!selected_cpu && !selected_arch)
4133
    {
4134
      /* We've not selected an architecture yet.  Set the default
4135
         now.  We do this lazily so that an initial .cpu or .arch directive
4136
         can specify.  */
4137
      if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4138
        as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4139
    }
4140
  if (!initialized)
4141
    m68k_init_arch ();
4142
 
4143
  /* In MRI mode, the instruction and operands are separated by a
4144
     space.  Anything following the operands is a comment.  The label
4145
     has already been removed.  */
4146
  if (flag_mri)
4147
    {
4148
      char *s;
4149
      int fields = 0;
4150
      int infield = 0;
4151
      int inquote = 0;
4152
 
4153
      for (s = str; *s != '\0'; s++)
4154
        {
4155
          if ((*s == ' ' || *s == '\t') && ! inquote)
4156
            {
4157
              if (infield)
4158
                {
4159
                  ++fields;
4160
                  if (fields >= 2)
4161
                    {
4162
                      *s = '\0';
4163
                      break;
4164
                    }
4165
                  infield = 0;
4166
                }
4167
            }
4168
          else
4169
            {
4170
              if (! infield)
4171
                infield = 1;
4172
              if (*s == '\'')
4173
                inquote = ! inquote;
4174
            }
4175
        }
4176
    }
4177
 
4178
  memset (&the_ins, '\0', sizeof (the_ins));
4179
  m68k_ip (str);
4180
  er = the_ins.error;
4181
  if (!er)
4182
    {
4183
      for (n = 0; n < the_ins.numargs; n++)
4184
        if (the_ins.operands[n].error)
4185
          {
4186
            er = the_ins.operands[n].error;
4187
            break;
4188
          }
4189
    }
4190
  if (er)
4191
    {
4192
      as_bad (_("%s -- statement `%s' ignored"), er, str);
4193
      return;
4194
    }
4195
 
4196
  /* If there is a current label, record that it marks an instruction.  */
4197
  if (current_label != NULL)
4198
    {
4199
      current_label->text = 1;
4200
      current_label = NULL;
4201
    }
4202
 
4203
#ifdef OBJ_ELF
4204
  /* Tie dwarf2 debug info to the address at the start of the insn.  */
4205
  dwarf2_emit_insn (0);
4206
#endif
4207
 
4208
  if (the_ins.nfrag == 0)
4209
    {
4210
      /* No frag hacking involved; just put it out.  */
4211
      toP = frag_more (2 * the_ins.numo);
4212
      fromP = &the_ins.opcode[0];
4213
      for (m = the_ins.numo; m; --m)
4214
        {
4215
          md_number_to_chars (toP, (long) (*fromP), 2);
4216
          toP += 2;
4217
          fromP++;
4218
        }
4219
      /* Put out symbol-dependent info.  */
4220
      for (m = 0; m < the_ins.nrel; m++)
4221
        {
4222
          switch (the_ins.reloc[m].wid)
4223
            {
4224
            case 'B':
4225
              n = 1;
4226
              break;
4227
            case 'b':
4228
              n = 1;
4229
              break;
4230
            case '3':
4231
              n = 1;
4232
              break;
4233
            case 'w':
4234
            case 'W':
4235
              n = 2;
4236
              break;
4237
            case 'l':
4238
              n = 4;
4239
              break;
4240
            default:
4241
              as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4242
                        the_ins.reloc[m].wid);
4243
            }
4244
 
4245
          fixP = fix_new_exp (frag_now,
4246
                              ((toP - frag_now->fr_literal)
4247
                               - the_ins.numo * 2 + the_ins.reloc[m].n),
4248
                              n,
4249
                              &the_ins.reloc[m].exp,
4250
                              the_ins.reloc[m].pcrel,
4251
                              get_reloc_code (n, the_ins.reloc[m].pcrel,
4252
                                              the_ins.reloc[m].pic_reloc));
4253
          fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4254
          if (the_ins.reloc[m].wid == 'B')
4255
            fixP->fx_signed = 1;
4256
        }
4257
      return;
4258
    }
4259
 
4260
  /* There's some frag hacking.  */
4261
  {
4262
    /* Calculate the max frag size.  */
4263
    int wid;
4264
 
4265
    wid = 2 * the_ins.fragb[0].fragoff;
4266
    for (n = 1; n < the_ins.nfrag; n++)
4267
      wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4268
    /* frag_var part.  */
4269
    wid += FRAG_VAR_SIZE;
4270
    /* Make sure the whole insn fits in one chunk, in particular that
4271
       the var part is attached, as we access one byte before the
4272
       variable frag for byte branches.  */
4273
    frag_grow (wid);
4274
  }
4275
 
4276
  for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4277
    {
4278
      int wid;
4279
 
4280
      if (n == 0)
4281
        wid = 2 * the_ins.fragb[n].fragoff;
4282
      else
4283
        wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4284
      toP = frag_more (wid);
4285
      to_beg_P = toP;
4286
      shorts_this_frag = 0;
4287
      for (m = wid / 2; m; --m)
4288
        {
4289
          md_number_to_chars (toP, (long) (*fromP), 2);
4290
          toP += 2;
4291
          fromP++;
4292
          shorts_this_frag++;
4293
        }
4294
      for (m = 0; m < the_ins.nrel; m++)
4295
        {
4296
          if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4297
            {
4298
              the_ins.reloc[m].n -= 2 * shorts_this_frag;
4299
              break;
4300
            }
4301
          wid = the_ins.reloc[m].wid;
4302
          if (wid == 0)
4303
            continue;
4304
          the_ins.reloc[m].wid = 0;
4305
          wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4306
 
4307
          fixP = fix_new_exp (frag_now,
4308
                              ((toP - frag_now->fr_literal)
4309
                               - the_ins.numo * 2 + the_ins.reloc[m].n),
4310
                              wid,
4311
                              &the_ins.reloc[m].exp,
4312
                              the_ins.reloc[m].pcrel,
4313
                              get_reloc_code (wid, the_ins.reloc[m].pcrel,
4314
                                              the_ins.reloc[m].pic_reloc));
4315
          fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4316
        }
4317
      (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
4318
                       (relax_substateT) (the_ins.fragb[n].fragty),
4319
                       the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4320
    }
4321
  n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4322
  shorts_this_frag = 0;
4323
  if (n)
4324
    {
4325
      toP = frag_more (n * 2);
4326
      while (n--)
4327
        {
4328
          md_number_to_chars (toP, (long) (*fromP), 2);
4329
          toP += 2;
4330
          fromP++;
4331
          shorts_this_frag++;
4332
        }
4333
    }
4334
  for (m = 0; m < the_ins.nrel; m++)
4335
    {
4336
      int wid;
4337
 
4338
      wid = the_ins.reloc[m].wid;
4339
      if (wid == 0)
4340
        continue;
4341
      the_ins.reloc[m].wid = 0;
4342
      wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4343
 
4344
      fixP = fix_new_exp (frag_now,
4345
                          ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4346
                           - shorts_this_frag * 2),
4347
                          wid,
4348
                          &the_ins.reloc[m].exp,
4349
                          the_ins.reloc[m].pcrel,
4350
                          get_reloc_code (wid, the_ins.reloc[m].pcrel,
4351
                                          the_ins.reloc[m].pic_reloc));
4352
      fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4353
    }
4354
}
4355
 
4356
/* Comparison function used by qsort to rank the opcode entries by name.  */
4357
 
4358
static int
4359
m68k_compare_opcode (const void * v1, const void * v2)
4360
{
4361
  struct m68k_opcode * op1, * op2;
4362
  int ret;
4363
 
4364
  if (v1 == v2)
4365
    return 0;
4366
 
4367
  op1 = *(struct m68k_opcode **) v1;
4368
  op2 = *(struct m68k_opcode **) v2;
4369
 
4370
  /* Compare the two names.  If different, return the comparison.
4371
     If the same, return the order they are in the opcode table.  */
4372
  ret = strcmp (op1->name, op2->name);
4373
  if (ret)
4374
    return ret;
4375
  if (op1 < op2)
4376
    return -1;
4377
  return 1;
4378
}
4379
 
4380
void
4381
md_begin (void)
4382
{
4383
  const struct m68k_opcode *ins;
4384
  struct m68k_incant *hack, *slak;
4385
  const char *retval = 0;        /* Empty string, or error msg text.  */
4386
  int i;
4387
 
4388
  /* Set up hash tables with 68000 instructions.
4389
     similar to what the vax assembler does.  */
4390
  /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4391
     a copy of it at runtime, adding in the information we want but isn't
4392
     there.  I think it'd be better to have an awk script hack the table
4393
     at compile time.  Or even just xstr the table and use it as-is.  But
4394
     my lord ghod hath spoken, so we do it this way.  Excuse the ugly var
4395
     names.  */
4396
 
4397
  if (flag_mri)
4398
    {
4399
      flag_reg_prefix_optional = 1;
4400
      m68k_abspcadd = 1;
4401
      if (! m68k_rel32_from_cmdline)
4402
        m68k_rel32 = 0;
4403
    }
4404
 
4405
  /* First sort the opcode table into alphabetical order to seperate
4406
     the order that the assembler wants to see the opcodes from the
4407
     order that the disassembler wants to see them.  */
4408
  m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4409
  if (!m68k_sorted_opcodes)
4410
    as_fatal (_("Internal Error:  Can't allocate m68k_sorted_opcodes of size %d"),
4411
              m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4412
 
4413
  for (i = m68k_numopcodes; i--;)
4414
    m68k_sorted_opcodes[i] = m68k_opcodes + i;
4415
 
4416
  qsort (m68k_sorted_opcodes, m68k_numopcodes,
4417
         sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4418
 
4419
  op_hash = hash_new ();
4420
 
4421
  obstack_begin (&robyn, 4000);
4422
  for (i = 0; i < m68k_numopcodes; i++)
4423
    {
4424
      hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4425
      do
4426
        {
4427
          ins = m68k_sorted_opcodes[i];
4428
 
4429
          /* We must enter all insns into the table, because .arch and
4430
             .cpu directives can change things.  */
4431
          slak->m_operands = ins->args;
4432
          slak->m_arch = ins->arch;
4433
          slak->m_opcode = ins->opcode;
4434
 
4435
          /* In most cases we can determine the number of opcode words
4436
             by checking the second word of the mask.  Unfortunately
4437
             some instructions have 2 opcode words, but no fixed bits
4438
             in the second word.  A leading dot in the operands
4439
             string also indicates 2 opcodes.  */
4440
          if (*slak->m_operands == '.')
4441
            {
4442
              slak->m_operands++;
4443
              slak->m_codenum = 2;
4444
            }
4445
          else if (ins->match & 0xffffL)
4446
            slak->m_codenum = 2;
4447
          else
4448
            slak->m_codenum = 1;
4449
          slak->m_opnum = strlen (slak->m_operands) / 2;
4450
 
4451
          if (i + 1 != m68k_numopcodes
4452
              && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4453
            {
4454
              slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4455
              i++;
4456
            }
4457
          else
4458
            slak->m_next = 0;
4459
          slak = slak->m_next;
4460
        }
4461
      while (slak);
4462
 
4463
      retval = hash_insert (op_hash, ins->name, (char *) hack);
4464
      if (retval)
4465
        as_fatal (_("Internal Error:  Can't hash %s: %s"), ins->name, retval);
4466
    }
4467
 
4468
  for (i = 0; i < m68k_numaliases; i++)
4469
    {
4470
      const char *name = m68k_opcode_aliases[i].primary;
4471
      const char *alias = m68k_opcode_aliases[i].alias;
4472
      PTR val = hash_find (op_hash, name);
4473
 
4474
      if (!val)
4475
        as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4476
      retval = hash_insert (op_hash, alias, val);
4477
      if (retval)
4478
        as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4479
    }
4480
 
4481
  /* In MRI mode, all unsized branches are variable sized.  Normally,
4482
     they are word sized.  */
4483
  if (flag_mri)
4484
    {
4485
      static struct m68k_opcode_alias mri_aliases[] =
4486
        {
4487
          { "bhi",      "jhi", },
4488
          { "bls",      "jls", },
4489
          { "bcc",      "jcc", },
4490
          { "bcs",      "jcs", },
4491
          { "bne",      "jne", },
4492
          { "beq",      "jeq", },
4493
          { "bvc",      "jvc", },
4494
          { "bvs",      "jvs", },
4495
          { "bpl",      "jpl", },
4496
          { "bmi",      "jmi", },
4497
          { "bge",      "jge", },
4498
          { "blt",      "jlt", },
4499
          { "bgt",      "jgt", },
4500
          { "ble",      "jle", },
4501
          { "bra",      "jra", },
4502
          { "bsr",      "jbsr", },
4503
        };
4504
 
4505
      for (i = 0;
4506
           i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4507
           i++)
4508
        {
4509
          const char *name = mri_aliases[i].primary;
4510
          const char *alias = mri_aliases[i].alias;
4511
          PTR val = hash_find (op_hash, name);
4512
 
4513
          if (!val)
4514
            as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4515
          retval = hash_jam (op_hash, alias, val);
4516
          if (retval)
4517
            as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4518
        }
4519
    }
4520
 
4521
  for (i = 0; i < (int) sizeof (notend_table); i++)
4522
    {
4523
      notend_table[i] = 0;
4524
      alt_notend_table[i] = 0;
4525
    }
4526
 
4527
  notend_table[','] = 1;
4528
  notend_table['{'] = 1;
4529
  notend_table['}'] = 1;
4530
  alt_notend_table['a'] = 1;
4531
  alt_notend_table['A'] = 1;
4532
  alt_notend_table['d'] = 1;
4533
  alt_notend_table['D'] = 1;
4534
  alt_notend_table['#'] = 1;
4535
  alt_notend_table['&'] = 1;
4536
  alt_notend_table['f'] = 1;
4537
  alt_notend_table['F'] = 1;
4538
#ifdef REGISTER_PREFIX
4539
  alt_notend_table[REGISTER_PREFIX] = 1;
4540
#endif
4541
 
4542
  /* We need to put '(' in alt_notend_table to handle
4543
       cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)  */
4544
  alt_notend_table['('] = 1;
4545
 
4546
  /* We need to put '@' in alt_notend_table to handle
4547
       cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)  */
4548
  alt_notend_table['@'] = 1;
4549
 
4550
  /* We need to put digits in alt_notend_table to handle
4551
       bfextu %d0{24:1},%d0  */
4552
  alt_notend_table['0'] = 1;
4553
  alt_notend_table['1'] = 1;
4554
  alt_notend_table['2'] = 1;
4555
  alt_notend_table['3'] = 1;
4556
  alt_notend_table['4'] = 1;
4557
  alt_notend_table['5'] = 1;
4558
  alt_notend_table['6'] = 1;
4559
  alt_notend_table['7'] = 1;
4560
  alt_notend_table['8'] = 1;
4561
  alt_notend_table['9'] = 1;
4562
 
4563
#ifndef MIT_SYNTAX_ONLY
4564
  /* Insert pseudo ops, these have to go into the opcode table since
4565
     gas expects pseudo ops to start with a dot.  */
4566
  {
4567
    int n = 0;
4568
 
4569
    while (mote_pseudo_table[n].poc_name)
4570
      {
4571
        hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4572
        hash_insert (op_hash,
4573
                     mote_pseudo_table[n].poc_name, (char *) hack);
4574
        hack->m_operands = 0;
4575
        hack->m_opnum = n;
4576
        n++;
4577
      }
4578
  }
4579
#endif
4580
 
4581
  init_regtable ();
4582
 
4583
#ifdef OBJ_ELF
4584
  record_alignment (text_section, 2);
4585
  record_alignment (data_section, 2);
4586
  record_alignment (bss_section, 2);
4587
#endif
4588
}
4589
 
4590
 
4591
/* This is called when a label is defined.  */
4592
 
4593
void
4594
m68k_frob_label (symbolS *sym)
4595
{
4596
  struct label_line *n;
4597
 
4598
  n = (struct label_line *) xmalloc (sizeof *n);
4599
  n->next = labels;
4600
  n->label = sym;
4601
  as_where (&n->file, &n->line);
4602
  n->text = 0;
4603
  labels = n;
4604
  current_label = n;
4605
 
4606
#ifdef OBJ_ELF
4607
  dwarf2_emit_label (sym);
4608
#endif
4609
}
4610
 
4611
/* This is called when a value that is not an instruction is emitted.  */
4612
 
4613
void
4614
m68k_flush_pending_output (void)
4615
{
4616
  current_label = NULL;
4617
}
4618
 
4619
/* This is called at the end of the assembly, when the final value of
4620
   the label is known.  We warn if this is a text symbol aligned at an
4621
   odd location.  */
4622
 
4623
void
4624
m68k_frob_symbol (symbolS *sym)
4625
{
4626
  if (S_GET_SEGMENT (sym) == reg_section
4627
      && (int) S_GET_VALUE (sym) < 0)
4628
    {
4629
      S_SET_SEGMENT (sym, absolute_section);
4630
      S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4631
    }
4632
  else if ((S_GET_VALUE (sym) & 1) != 0)
4633
    {
4634
      struct label_line *l;
4635
 
4636
      for (l = labels; l != NULL; l = l->next)
4637
        {
4638
          if (l->label == sym)
4639
            {
4640
              if (l->text)
4641
                as_warn_where (l->file, l->line,
4642
                               _("text label `%s' aligned to odd boundary"),
4643
                               S_GET_NAME (sym));
4644
              break;
4645
            }
4646
        }
4647
    }
4648
}
4649
 
4650
/* This is called if we go in or out of MRI mode because of the .mri
4651
   pseudo-op.  */
4652
 
4653
void
4654
m68k_mri_mode_change (int on)
4655
{
4656
  if (on)
4657
    {
4658
      if (! flag_reg_prefix_optional)
4659
        {
4660
          flag_reg_prefix_optional = 1;
4661
#ifdef REGISTER_PREFIX
4662
          init_regtable ();
4663
#endif
4664
        }
4665
      m68k_abspcadd = 1;
4666
      if (! m68k_rel32_from_cmdline)
4667
        m68k_rel32 = 0;
4668
    }
4669
  else
4670
    {
4671
      if (! reg_prefix_optional_seen)
4672
        {
4673
#ifdef REGISTER_PREFIX_OPTIONAL
4674
          flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4675
#else
4676
          flag_reg_prefix_optional = 0;
4677
#endif
4678
#ifdef REGISTER_PREFIX
4679
          init_regtable ();
4680
#endif
4681
        }
4682
      m68k_abspcadd = 0;
4683
      if (! m68k_rel32_from_cmdline)
4684
        m68k_rel32 = 1;
4685
    }
4686
}
4687
 
4688
char *
4689
md_atof (int type, char *litP, int *sizeP)
4690
{
4691
  return ieee_md_atof (type, litP, sizeP, TRUE);
4692
}
4693
 
4694
void
4695
md_number_to_chars (char *buf, valueT val, int n)
4696
{
4697
  number_to_chars_bigendian (buf, val, n);
4698
}
4699
 
4700
void
4701
md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4702
{
4703
  offsetT val = *valP;
4704
  addressT upper_limit;
4705
  offsetT lower_limit;
4706
 
4707
  /* This is unnecessary but it convinces the native rs6000 compiler
4708
     to generate the code we want.  */
4709
  char *buf = fixP->fx_frag->fr_literal;
4710
  buf += fixP->fx_where;
4711
  /* End ibm compiler workaround.  */
4712
 
4713
  val = SEXT (val);
4714
 
4715
  if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4716
    fixP->fx_done = 1;
4717
 
4718
#ifdef OBJ_ELF
4719
  if (fixP->fx_addsy)
4720
    {
4721
      memset (buf, 0, fixP->fx_size);
4722
      fixP->fx_addnumber = val; /* Remember value for emit_reloc.  */
4723
 
4724
      if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4725
          && !S_IS_DEFINED (fixP->fx_addsy)
4726
          && !S_IS_WEAK (fixP->fx_addsy))
4727
        S_SET_WEAK (fixP->fx_addsy);
4728
      return;
4729
    }
4730
#elif defined(OBJ_AOUT)
4731
  /* PR gas/3041 Do not fix frags referencing a weak symbol.  */
4732
  if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4733
    {
4734
      memset (buf, 0, fixP->fx_size);
4735
      fixP->fx_addnumber = val; /* Remember value for emit_reloc.  */
4736
      return;
4737
    }
4738
#endif
4739
 
4740
  if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4741
      || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4742
    return;
4743
 
4744
  switch (fixP->fx_size)
4745
    {
4746
      /* The cast to offsetT below are necessary to make code
4747
         correct for machines where ints are smaller than offsetT.  */
4748
    case 1:
4749
      *buf++ = val;
4750
      upper_limit = 0x7f;
4751
      lower_limit = - (offsetT) 0x80;
4752
      break;
4753
    case 2:
4754
      *buf++ = (val >> 8);
4755
      *buf++ = val;
4756
      upper_limit = 0x7fff;
4757
      lower_limit = - (offsetT) 0x8000;
4758
      break;
4759
    case 4:
4760
      *buf++ = (val >> 24);
4761
      *buf++ = (val >> 16);
4762
      *buf++ = (val >> 8);
4763
      *buf++ = val;
4764
      upper_limit = 0x7fffffff;
4765
      lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow.  */
4766
      break;
4767
    default:
4768
      BAD_CASE (fixP->fx_size);
4769
    }
4770
 
4771
  /* Fix up a negative reloc.  */
4772
  if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4773
    {
4774
      fixP->fx_addsy = fixP->fx_subsy;
4775
      fixP->fx_subsy = NULL;
4776
      fixP->fx_tcbit = 1;
4777
    }
4778
 
4779
  /* For non-pc-relative values, it's conceivable we might get something
4780
     like "0xff" for a byte field.  So extend the upper part of the range
4781
     to accept such numbers.  We arbitrarily disallow "-0xff" or "0xff+0xff",
4782
     so that we can do any range checking at all.  */
4783
  if (! fixP->fx_pcrel && ! fixP->fx_signed)
4784
    upper_limit = upper_limit * 2 + 1;
4785
 
4786
  if ((addressT) val > upper_limit
4787
      && (val > 0 || val < lower_limit))
4788
    as_bad_where (fixP->fx_file, fixP->fx_line,
4789
                  _("value %ld out of range"), (long)val);
4790
 
4791
  /* A one byte PC-relative reloc means a short branch.  We can't use
4792
     a short branch with a value of 0 or -1, because those indicate
4793
     different opcodes (branches with longer offsets).  fixup_segment
4794
     in write.c may have clobbered fx_pcrel, so we need to examine the
4795
     reloc type.  */
4796
  if ((fixP->fx_pcrel
4797
       || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4798
      && fixP->fx_size == 1
4799
      && (fixP->fx_addsy == NULL
4800
          || S_IS_DEFINED (fixP->fx_addsy))
4801
      && (val == 0 || val == -1))
4802
    as_bad_where (fixP->fx_file, fixP->fx_line,
4803
                  _("invalid byte branch offset"));
4804
}
4805
 
4806
/* *fragP has been relaxed to its final size, and now needs to have
4807
   the bytes inside it modified to conform to the new size  There is UGLY
4808
   MAGIC here. ..
4809
   */
4810
static void
4811
md_convert_frag_1 (fragS *fragP)
4812
{
4813
  long disp;
4814
  fixS *fixP = NULL;
4815
 
4816
  /* Address in object code of the displacement.  */
4817
  register int object_address = fragP->fr_fix + fragP->fr_address;
4818
 
4819
  /* Address in gas core of the place to store the displacement.  */
4820
  /* This convinces the native rs6000 compiler to generate the code we
4821
     want.  */
4822
  register char *buffer_address = fragP->fr_literal;
4823
  buffer_address += fragP->fr_fix;
4824
  /* End ibm compiler workaround.  */
4825
 
4826
  /* The displacement of the address, from current location.  */
4827
  disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4828
  disp = (disp + fragP->fr_offset) - object_address;
4829
 
4830
  switch (fragP->fr_subtype)
4831
    {
4832
    case TAB (BRANCHBWL, BYTE):
4833
    case TAB (BRABSJUNC, BYTE):
4834
    case TAB (BRABSJCOND, BYTE):
4835
    case TAB (BRANCHBW, BYTE):
4836
    case TAB (BRANCHBWPL, BYTE):
4837
      know (issbyte (disp));
4838
      if (disp == 0)
4839
        as_bad_where (fragP->fr_file, fragP->fr_line,
4840
                      _("short branch with zero offset: use :w"));
4841
      fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4842
                      fragP->fr_offset, 1, RELAX_RELOC_PC8);
4843
      fixP->fx_pcrel_adjust = -1;
4844
      break;
4845
    case TAB (BRANCHBWL, SHORT):
4846
    case TAB (BRABSJUNC, SHORT):
4847
    case TAB (BRABSJCOND, SHORT):
4848
    case TAB (BRANCHBW, SHORT):
4849
    case TAB (BRANCHBWPL, SHORT):
4850
      fragP->fr_opcode[1] = 0x00;
4851
      fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4852
                      fragP->fr_offset, 1, RELAX_RELOC_PC16);
4853
      fragP->fr_fix += 2;
4854
      break;
4855
    case TAB (BRANCHBWL, LONG):
4856
      fragP->fr_opcode[1] = (char) 0xFF;
4857
      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4858
                      fragP->fr_offset, 1, RELAX_RELOC_PC32);
4859
      fragP->fr_fix += 4;
4860
      break;
4861
    case TAB (BRANCHBWPL, LONG):
4862
      /* Here we are converting an unconditional branch into a pair of
4863
         conditional branches, in order to get the range.  */
4864
      fragP->fr_opcode[0] = 0x66; /* bne */
4865
      fragP->fr_opcode[1] = 0xFF;
4866
      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4867
                      fragP->fr_offset, 1, RELAX_RELOC_PC32);
4868
      fixP->fx_file = fragP->fr_file;
4869
      fixP->fx_line = fragP->fr_line;
4870
      fragP->fr_fix += 4;  /* Skip first offset */
4871
      buffer_address += 4;
4872
      *buffer_address++ = 0x67; /* beq */
4873
      *buffer_address++ = 0xff;
4874
      fragP->fr_fix += 2;  /* Skip second branch opcode */
4875
      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4876
                      fragP->fr_offset, 1, RELAX_RELOC_PC32);
4877
      fragP->fr_fix += 4;
4878
      break;
4879
    case TAB (BRABSJUNC, LONG):
4880
      if (fragP->fr_opcode[0] == 0x61)           /* jbsr */
4881
        {
4882
          if (flag_keep_pcrel)
4883
            as_bad_where (fragP->fr_file, fragP->fr_line,
4884
                          _("Conversion of PC relative BSR to absolute JSR"));
4885
          fragP->fr_opcode[0] = 0x4E;
4886
          fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand.  */
4887
          fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4888
                          fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4889
          fragP->fr_fix += 4;
4890
        }
4891
      else if (fragP->fr_opcode[0] == 0x60)      /* jbra */
4892
        {
4893
          if (flag_keep_pcrel)
4894
            as_bad_where (fragP->fr_file, fragP->fr_line,
4895
                      _("Conversion of PC relative branch to absolute jump"));
4896
          fragP->fr_opcode[0] = 0x4E;
4897
          fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand.  */
4898
          fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4899
                          fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4900
          fragP->fr_fix += 4;
4901
        }
4902
      else
4903
        {
4904
          /* This cannot happen, because jbsr and jbra are the only two
4905
             unconditional branches.  */
4906
          abort ();
4907
        }
4908
      break;
4909
    case TAB (BRABSJCOND, LONG):
4910
      if (flag_keep_pcrel)
4911
        as_bad_where (fragP->fr_file, fragP->fr_line,
4912
                  _("Conversion of PC relative conditional branch to absolute jump"));
4913
 
4914
      /* Only Bcc 68000 instructions can come here
4915
         Change bcc into b!cc/jmp absl long.  */
4916
      fragP->fr_opcode[0] ^= 0x01;       /* Invert bcc.  */
4917
      fragP->fr_opcode[1]  = 0x06;      /* Branch offset = 6.  */
4918
 
4919
      /* JF: these used to be fr_opcode[2,3], but they may be in a
4920
           different frag, in which case referring to them is a no-no.
4921
           Only fr_opcode[0,1] are guaranteed to work.  */
4922
      *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4923
      *buffer_address++ = (char) 0xf9;
4924
      fragP->fr_fix += 2;       /* Account for jmp instruction.  */
4925
      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4926
                      fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4927
      fragP->fr_fix += 4;
4928
      break;
4929
    case TAB (FBRANCH, SHORT):
4930
      know ((fragP->fr_opcode[1] & 0x40) == 0);
4931
      fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4932
                      fragP->fr_offset, 1, RELAX_RELOC_PC16);
4933
      fragP->fr_fix += 2;
4934
      break;
4935
    case TAB (FBRANCH, LONG):
4936
      fragP->fr_opcode[1] |= 0x40;      /* Turn on LONG bit.  */
4937
      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4938
                      fragP->fr_offset, 1, RELAX_RELOC_PC32);
4939
      fragP->fr_fix += 4;
4940
      break;
4941
    case TAB (DBCCLBR, SHORT):
4942
    case TAB (DBCCABSJ, SHORT):
4943
      fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4944
                      fragP->fr_offset, 1, RELAX_RELOC_PC16);
4945
      fragP->fr_fix += 2;
4946
      break;
4947
    case TAB (DBCCLBR, LONG):
4948
      /* Only DBcc instructions can come here.
4949
         Change dbcc into dbcc/bral.
4950
         JF: these used to be fr_opcode[2-7], but that's wrong.  */
4951
      if (flag_keep_pcrel)
4952
        as_bad_where (fragP->fr_file, fragP->fr_line,
4953
                  _("Conversion of DBcc to absolute jump"));
4954
 
4955
      *buffer_address++ = 0x00; /* Branch offset = 4.  */
4956
      *buffer_address++ = 0x04;
4957
      *buffer_address++ = 0x60; /* Put in bra pc+6.  */
4958
      *buffer_address++ = 0x06;
4959
      *buffer_address++ = 0x60;     /* Put in bral (0x60ff).  */
4960
      *buffer_address++ = (char) 0xff;
4961
 
4962
      fragP->fr_fix += 6;       /* Account for bra/jmp instructions.  */
4963
      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4964
                      fragP->fr_offset, 1, RELAX_RELOC_PC32);
4965
      fragP->fr_fix += 4;
4966
      break;
4967
    case TAB (DBCCABSJ, LONG):
4968
      /* Only DBcc instructions can come here.
4969
         Change dbcc into dbcc/jmp.
4970
         JF: these used to be fr_opcode[2-7], but that's wrong.  */
4971
      if (flag_keep_pcrel)
4972
        as_bad_where (fragP->fr_file, fragP->fr_line,
4973
                      _("Conversion of PC relative conditional branch to absolute jump"));
4974
 
4975
      *buffer_address++ = 0x00;         /* Branch offset = 4.  */
4976
      *buffer_address++ = 0x04;
4977
      *buffer_address++ = 0x60;         /* Put in bra pc + 6.  */
4978
      *buffer_address++ = 0x06;
4979
      *buffer_address++ = 0x4e;         /* Put in jmp long (0x4ef9).  */
4980
      *buffer_address++ = (char) 0xf9;
4981
 
4982
      fragP->fr_fix += 6;               /* Account for bra/jmp instructions.  */
4983
      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4984
                      fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4985
      fragP->fr_fix += 4;
4986
      break;
4987
    case TAB (PCREL1632, SHORT):
4988
      fragP->fr_opcode[1] &= ~0x3F;
4989
      fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4990
      fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4991
                      fragP->fr_offset, 1, RELAX_RELOC_PC16);
4992
      fragP->fr_fix += 2;
4993
      break;
4994
    case TAB (PCREL1632, LONG):
4995
      /* Already set to mode 7.3; this indicates: PC indirect with
4996
         suppressed index, 32-bit displacement.  */
4997
      *buffer_address++ = 0x01;
4998
      *buffer_address++ = 0x70;
4999
      fragP->fr_fix += 2;
5000
      fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5001
                      fragP->fr_offset, 1, RELAX_RELOC_PC32);
5002
      fixP->fx_pcrel_adjust = 2;
5003
      fragP->fr_fix += 4;
5004
      break;
5005
    case TAB (PCINDEX, BYTE):
5006
      assert (fragP->fr_fix >= 2);
5007
      buffer_address[-2] &= ~1;
5008
      fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5009
                      fragP->fr_offset, 1, RELAX_RELOC_PC8);
5010
      fixP->fx_pcrel_adjust = 1;
5011
      break;
5012
    case TAB (PCINDEX, SHORT):
5013
      assert (fragP->fr_fix >= 2);
5014
      buffer_address[-2] |= 0x1;
5015
      buffer_address[-1] = 0x20;
5016
      fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5017
                      fragP->fr_offset, 1, RELAX_RELOC_PC16);
5018
      fixP->fx_pcrel_adjust = 2;
5019
      fragP->fr_fix += 2;
5020
      break;
5021
    case TAB (PCINDEX, LONG):
5022
      assert (fragP->fr_fix >= 2);
5023
      buffer_address[-2] |= 0x1;
5024
      buffer_address[-1] = 0x30;
5025
      fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5026
                      fragP->fr_offset, 1, RELAX_RELOC_PC32);
5027
      fixP->fx_pcrel_adjust = 2;
5028
      fragP->fr_fix += 4;
5029
      break;
5030
    case TAB (ABSTOPCREL, SHORT):
5031
      fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5032
                      fragP->fr_offset, 1, RELAX_RELOC_PC16);
5033
      fragP->fr_fix += 2;
5034
      break;
5035
    case TAB (ABSTOPCREL, LONG):
5036
      if (flag_keep_pcrel)
5037
        as_bad_where (fragP->fr_file, fragP->fr_line,
5038
                      _("Conversion of PC relative displacement to absolute"));
5039
      /* The thing to do here is force it to ABSOLUTE LONG, since
5040
         ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway.  */
5041
      if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5042
        abort ();
5043
      fragP->fr_opcode[1] &= ~0x3F;
5044
      fragP->fr_opcode[1] |= 0x39;      /* Mode 7.1 */
5045
      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5046
                      fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5047
      fragP->fr_fix += 4;
5048
      break;
5049
    }
5050
  if (fixP)
5051
    {
5052
      fixP->fx_file = fragP->fr_file;
5053
      fixP->fx_line = fragP->fr_line;
5054
    }
5055
}
5056
 
5057
void
5058
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5059
                 segT sec ATTRIBUTE_UNUSED,
5060
                 fragS *fragP)
5061
{
5062
  md_convert_frag_1 (fragP);
5063
}
5064
 
5065
/* Force truly undefined symbols to their maximum size, and generally set up
5066
   the frag list to be relaxed
5067
   */
5068
int
5069
md_estimate_size_before_relax (fragS *fragP, segT segment)
5070
{
5071
  /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT.  */
5072
  switch (fragP->fr_subtype)
5073
    {
5074
    case TAB (BRANCHBWL, SZ_UNDEF):
5075
    case TAB (BRANCHBWPL, SZ_UNDEF):
5076
    case TAB (BRABSJUNC, SZ_UNDEF):
5077
    case TAB (BRABSJCOND, SZ_UNDEF):
5078
      {
5079
        if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5080
            && relaxable_symbol (fragP->fr_symbol))
5081
          {
5082
            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5083
          }
5084
        else if (flag_short_refs)
5085
          {
5086
            /* Symbol is undefined and we want short ref.  */
5087
            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5088
          }
5089
        else
5090
          {
5091
            /* Symbol is still undefined.  Make it LONG.  */
5092
            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5093
          }
5094
        break;
5095
      }
5096
 
5097
    case TAB (BRANCHBW, SZ_UNDEF):
5098
      {
5099
        if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5100
            && relaxable_symbol (fragP->fr_symbol))
5101
          {
5102
            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5103
          }
5104
        else
5105
          {
5106
            /* Symbol is undefined and we don't have long branches.  */
5107
            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5108
          }
5109
        break;
5110
      }
5111
 
5112
    case TAB (FBRANCH, SZ_UNDEF):
5113
    case TAB (DBCCLBR, SZ_UNDEF):
5114
    case TAB (DBCCABSJ, SZ_UNDEF):
5115
    case TAB (PCREL1632, SZ_UNDEF):
5116
      {
5117
        if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5118
             && relaxable_symbol (fragP->fr_symbol))
5119
            || flag_short_refs)
5120
          {
5121
            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5122
          }
5123
        else
5124
          {
5125
            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5126
          }
5127
        break;
5128
      }
5129
 
5130
    case TAB (PCINDEX, SZ_UNDEF):
5131
      if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5132
           && relaxable_symbol (fragP->fr_symbol)))
5133
        {
5134
          fragP->fr_subtype = TAB (PCINDEX, BYTE);
5135
        }
5136
      else
5137
        {
5138
          fragP->fr_subtype = TAB (PCINDEX, LONG);
5139
        }
5140
      break;
5141
 
5142
    case TAB (ABSTOPCREL, SZ_UNDEF):
5143
      {
5144
        if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5145
             && relaxable_symbol (fragP->fr_symbol)))
5146
          {
5147
            fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5148
          }
5149
        else
5150
          {
5151
            fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5152
          }
5153
        break;
5154
      }
5155
 
5156
    default:
5157
      break;
5158
    }
5159
 
5160
  /* Now that SZ_UNDEF are taken care of, check others.  */
5161
  switch (fragP->fr_subtype)
5162
    {
5163
    case TAB (BRANCHBWL, BYTE):
5164
    case TAB (BRABSJUNC, BYTE):
5165
    case TAB (BRABSJCOND, BYTE):
5166
    case TAB (BRANCHBW, BYTE):
5167
      /* We can't do a short jump to the next instruction, so in that
5168
         case we force word mode.  If the symbol is at the start of a
5169
         frag, and it is the next frag with any data in it (usually
5170
         this is just the next frag, but assembler listings may
5171
         introduce empty frags), we must use word mode.  */
5172
      if (fragP->fr_symbol)
5173
        {
5174
          fragS *sym_frag;
5175
 
5176
          sym_frag = symbol_get_frag (fragP->fr_symbol);
5177
          if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5178
            {
5179
              fragS *l;
5180
 
5181
              for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5182
                if (l->fr_fix != 0)
5183
                  break;
5184
              if (l == sym_frag)
5185
                fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5186
            }
5187
        }
5188
      break;
5189
    default:
5190
      break;
5191
    }
5192
  return md_relax_table[fragP->fr_subtype].rlx_length;
5193
}
5194
 
5195
#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5196
/* the bit-field entries in the relocation_info struct plays hell
5197
   with the byte-order problems of cross-assembly.  So as a hack,
5198
   I added this mach. dependent ri twiddler.  Ugly, but it gets
5199
   you there. -KWK  */
5200
/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5201
   are symbolnum, most sig. byte first.  Last byte is broken up with
5202
   bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5203
   nibble as nuthin. (on Sun 3 at least) */
5204
/* Translate the internal relocation information into target-specific
5205
   format.  */
5206
#ifdef comment
5207
void
5208
md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5209
{
5210
  /* This is easy.  */
5211
  md_number_to_chars (the_bytes, ri->r_address, 4);
5212
  /* Now the fun stuff.  */
5213
  the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5214
  the_bytes[5] = (ri->r_symbolnum >>  8) & 0x0ff;
5215
  the_bytes[6] =  ri->r_symbolnum        & 0x0ff;
5216
  the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5217
                  | ((ri->r_length << 5) & 0x60)
5218
                  | ((ri->r_extern << 4) & 0x10));
5219
}
5220
 
5221
#endif
5222
 
5223
#endif /* OBJ_AOUT or OBJ_BOUT */
5224
 
5225
#ifndef WORKING_DOT_WORD
5226
int md_short_jump_size = 4;
5227
int md_long_jump_size = 6;
5228
 
5229
void
5230
md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5231
                      fragS *frag ATTRIBUTE_UNUSED,
5232
                      symbolS *to_symbol ATTRIBUTE_UNUSED)
5233
{
5234
  valueT offset;
5235
 
5236
  offset = to_addr - (from_addr + 2);
5237
 
5238
  md_number_to_chars (ptr, (valueT) 0x6000, 2);
5239
  md_number_to_chars (ptr + 2, (valueT) offset, 2);
5240
}
5241
 
5242
void
5243
md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5244
                     fragS *frag, symbolS *to_symbol)
5245
{
5246
  valueT offset;
5247
 
5248
  if (!HAVE_LONG_BRANCH (current_architecture))
5249
    {
5250
      if (flag_keep_pcrel)
5251
        as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5252
      offset = to_addr - S_GET_VALUE (to_symbol);
5253
      md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5254
      md_number_to_chars (ptr + 2, (valueT) offset, 4);
5255
      fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5256
               0, NO_RELOC);
5257
    }
5258
  else
5259
    {
5260
      offset = to_addr - (from_addr + 2);
5261
      md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5262
      md_number_to_chars (ptr + 2, (valueT) offset, 4);
5263
    }
5264
}
5265
 
5266
#endif
5267
 
5268
/* Different values of OK tell what its OK to return.  Things that
5269
   aren't OK are an error (what a shock, no?)
5270
 
5271
   0:  Everything is OK
5272
   10:  Absolute 1:8       only
5273
   20:  Absolute 0:7       only
5274
   30:  absolute 0:15      only
5275
   40:  Absolute 0:31      only
5276
   50:  absolute 0:127     only
5277
   55:  absolute -64:63    only
5278
   60:  absolute -128:127  only
5279
   65:  absolute 0:511     only
5280
   70:  absolute 0:4095    only
5281
   80:  absolute -1, 1:7   only
5282
   90:  No bignums.          */
5283
 
5284
static int
5285
get_num (struct m68k_exp *exp, int ok)
5286
{
5287
  if (exp->exp.X_op == O_absent)
5288
    {
5289
      /* Do the same thing the VAX asm does.  */
5290
      op (exp) = O_constant;
5291
      adds (exp) = 0;
5292
      subs (exp) = 0;
5293
      offs (exp) = 0;
5294
      if (ok == 10)
5295
        {
5296
          as_warn (_("expression out of range: defaulting to 1"));
5297
          offs (exp) = 1;
5298
        }
5299
    }
5300
  else if (exp->exp.X_op == O_constant)
5301
    {
5302
      switch (ok)
5303
        {
5304
        case 10:
5305
          if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5306
            {
5307
              as_warn (_("expression out of range: defaulting to 1"));
5308
              offs (exp) = 1;
5309
            }
5310
          break;
5311
        case 20:
5312
          if ((valueT) TRUNC (offs (exp)) > 7)
5313
            goto outrange;
5314
          break;
5315
        case 30:
5316
          if ((valueT) TRUNC (offs (exp)) > 15)
5317
            goto outrange;
5318
          break;
5319
        case 40:
5320
          if ((valueT) TRUNC (offs (exp)) > 32)
5321
            goto outrange;
5322
          break;
5323
        case 50:
5324
          if ((valueT) TRUNC (offs (exp)) > 127)
5325
            goto outrange;
5326
          break;
5327
        case 55:
5328
          if ((valueT) SEXT (offs (exp)) + 64 > 127)
5329
            goto outrange;
5330
          break;
5331
        case 60:
5332
          if ((valueT) SEXT (offs (exp)) + 128 > 255)
5333
            goto outrange;
5334
          break;
5335
        case 65:
5336
          if ((valueT) TRUNC (offs (exp)) > 511)
5337
            goto outrange;
5338
          break;
5339
        case 70:
5340
          if ((valueT) TRUNC (offs (exp)) > 4095)
5341
            {
5342
            outrange:
5343
              as_warn (_("expression out of range: defaulting to 0"));
5344
              offs (exp) = 0;
5345
            }
5346
          break;
5347
        case 80:
5348
          if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5349
              && (valueT) TRUNC (offs (exp)) - 1 > 6)
5350
            {
5351
              as_warn (_("expression out of range: defaulting to 1"));
5352
              offs (exp) = 1;
5353
            }
5354
          break;
5355
        default:
5356
          break;
5357
        }
5358
    }
5359
  else if (exp->exp.X_op == O_big)
5360
    {
5361
      if (offs (exp) <= 0        /* flonum.  */
5362
          && (ok == 90          /* no bignums */
5363
              || (ok > 10       /* Small-int ranges including 0 ok.  */
5364
                  /* If we have a flonum zero, a zero integer should
5365
                     do as well (e.g., in moveq).  */
5366
                  && generic_floating_point_number.exponent == 0
5367
                  && generic_floating_point_number.low[0] == 0)))
5368
        {
5369
          /* HACK! Turn it into a long.  */
5370
          LITTLENUM_TYPE words[6];
5371
 
5372
          gen_to_words (words, 2, 8L);  /* These numbers are magic!  */
5373
          op (exp) = O_constant;
5374
          adds (exp) = 0;
5375
          subs (exp) = 0;
5376
          offs (exp) = words[1] | (words[0] << 16);
5377
        }
5378
      else if (ok != 0)
5379
        {
5380
          op (exp) = O_constant;
5381
          adds (exp) = 0;
5382
          subs (exp) = 0;
5383
          offs (exp) = (ok == 10) ? 1 : 0;
5384
          as_warn (_("Can't deal with expression; defaulting to %ld"),
5385
                   (long) offs (exp));
5386
        }
5387
    }
5388
  else
5389
    {
5390
      if (ok >= 10 && ok <= 80)
5391
        {
5392
          op (exp) = O_constant;
5393
          adds (exp) = 0;
5394
          subs (exp) = 0;
5395
          offs (exp) = (ok == 10) ? 1 : 0;
5396
          as_warn (_("Can't deal with expression; defaulting to %ld"),
5397
                   (long) offs (exp));
5398
        }
5399
    }
5400
 
5401
  if (exp->size != SIZE_UNSPEC)
5402
    {
5403
      switch (exp->size)
5404
        {
5405
        case SIZE_UNSPEC:
5406
        case SIZE_LONG:
5407
          break;
5408
        case SIZE_BYTE:
5409
          if (!isbyte (offs (exp)))
5410
            as_warn (_("expression doesn't fit in BYTE"));
5411
          break;
5412
        case SIZE_WORD:
5413
          if (!isword (offs (exp)))
5414
            as_warn (_("expression doesn't fit in WORD"));
5415
          break;
5416
        }
5417
    }
5418
 
5419
  return offs (exp);
5420
}
5421
 
5422
/* These are the back-ends for the various machine dependent pseudo-ops.  */
5423
 
5424
static void
5425
s_data1 (int ignore ATTRIBUTE_UNUSED)
5426
{
5427
  subseg_set (data_section, 1);
5428
  demand_empty_rest_of_line ();
5429
}
5430
 
5431
static void
5432
s_data2 (int ignore ATTRIBUTE_UNUSED)
5433
{
5434
  subseg_set (data_section, 2);
5435
  demand_empty_rest_of_line ();
5436
}
5437
 
5438
static void
5439
s_bss (int ignore ATTRIBUTE_UNUSED)
5440
{
5441
  /* We don't support putting frags in the BSS segment, we fake it
5442
     by marking in_bss, then looking at s_skip for clues.  */
5443
 
5444
  subseg_set (bss_section, 0);
5445
  demand_empty_rest_of_line ();
5446
}
5447
 
5448
static void
5449
s_even (int ignore ATTRIBUTE_UNUSED)
5450
{
5451
  register int temp;
5452
  register long temp_fill;
5453
 
5454
  temp = 1;                     /* JF should be 2? */
5455
  temp_fill = get_absolute_expression ();
5456
  if (!need_pass_2)             /* Never make frag if expect extra pass.  */
5457
    frag_align (temp, (int) temp_fill, 0);
5458
  demand_empty_rest_of_line ();
5459
  record_alignment (now_seg, temp);
5460
}
5461
 
5462
static void
5463
s_proc (int ignore ATTRIBUTE_UNUSED)
5464
{
5465
  demand_empty_rest_of_line ();
5466
}
5467
 
5468
/* Pseudo-ops handled for MRI compatibility.  */
5469
 
5470
/* This function returns non-zero if the argument is a conditional
5471
   pseudo-op.  This is called when checking whether a pending
5472
   alignment is needed.  */
5473
 
5474
int
5475
m68k_conditional_pseudoop (pseudo_typeS *pop)
5476
{
5477
  return (pop->poc_handler == s_mri_if
5478
          || pop->poc_handler == s_mri_else);
5479
}
5480
 
5481
/* Handle an MRI style chip specification.  */
5482
 
5483
static void
5484
mri_chip (void)
5485
{
5486
  char *s;
5487
  char c;
5488
  int i;
5489
 
5490
  s = input_line_pointer;
5491
  /* We can't use get_symbol_end since the processor names are not proper
5492
     symbols.  */
5493
  while (is_part_of_name (c = *input_line_pointer++))
5494
    ;
5495
  *--input_line_pointer = 0;
5496
  for (i = 0; m68k_cpus[i].name; i++)
5497
    if (strcasecmp (s, m68k_cpus[i].name) == 0)
5498
      break;
5499
  if (!m68k_cpus[i].name)
5500
    {
5501
      as_bad (_("%s: unrecognized processor name"), s);
5502
      *input_line_pointer = c;
5503
      ignore_rest_of_line ();
5504
      return;
5505
    }
5506
  *input_line_pointer = c;
5507
 
5508
  if (*input_line_pointer == '/')
5509
    current_architecture = 0;
5510
  else
5511
    current_architecture &= m68881 | m68851;
5512
  current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5513
  control_regs = m68k_cpus[i].control_regs;
5514
 
5515
  while (*input_line_pointer == '/')
5516
    {
5517
      ++input_line_pointer;
5518
      s = input_line_pointer;
5519
      /* We can't use get_symbol_end since the processor names are not
5520
         proper symbols.  */
5521
      while (is_part_of_name (c = *input_line_pointer++))
5522
        ;
5523
      *--input_line_pointer = 0;
5524
      if (strcmp (s, "68881") == 0)
5525
        current_architecture |= m68881;
5526
      else if (strcmp (s, "68851") == 0)
5527
        current_architecture |= m68851;
5528
      *input_line_pointer = c;
5529
    }
5530
}
5531
 
5532
/* The MRI CHIP pseudo-op.  */
5533
 
5534
static void
5535
s_chip (int ignore ATTRIBUTE_UNUSED)
5536
{
5537
  char *stop = NULL;
5538
  char stopc;
5539
 
5540
  if (flag_mri)
5541
    stop = mri_comment_field (&stopc);
5542
  mri_chip ();
5543
  if (flag_mri)
5544
    mri_comment_end (stop, stopc);
5545
  demand_empty_rest_of_line ();
5546
}
5547
 
5548
/* The MRI FOPT pseudo-op.  */
5549
 
5550
static void
5551
s_fopt (int ignore ATTRIBUTE_UNUSED)
5552
{
5553
  SKIP_WHITESPACE ();
5554
 
5555
  if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5556
    {
5557
      int temp;
5558
 
5559
      input_line_pointer += 3;
5560
      temp = get_absolute_expression ();
5561
      if (temp < 0 || temp > 7)
5562
        as_bad (_("bad coprocessor id"));
5563
      else
5564
        m68k_float_copnum = COP0 + temp;
5565
    }
5566
  else
5567
    {
5568
      as_bad (_("unrecognized fopt option"));
5569
      ignore_rest_of_line ();
5570
      return;
5571
    }
5572
 
5573
  demand_empty_rest_of_line ();
5574
}
5575
 
5576
/* The structure used to handle the MRI OPT pseudo-op.  */
5577
 
5578
struct opt_action
5579
{
5580
  /* The name of the option.  */
5581
  const char *name;
5582
 
5583
  /* If this is not NULL, just call this function.  The first argument
5584
     is the ARG field of this structure, the second argument is
5585
     whether the option was negated.  */
5586
  void (*pfn) (int arg, int on);
5587
 
5588
  /* If this is not NULL, and the PFN field is NULL, set the variable
5589
     this points to.  Set it to the ARG field if the option was not
5590
     negated, and the NOTARG field otherwise.  */
5591
  int *pvar;
5592
 
5593
  /* The value to pass to PFN or to assign to *PVAR.  */
5594
  int arg;
5595
 
5596
  /* The value to assign to *PVAR if the option is negated.  If PFN is
5597
     NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5598
     the option may not be negated.  */
5599
  int notarg;
5600
};
5601
 
5602
/* The table used to handle the MRI OPT pseudo-op.  */
5603
 
5604
static void skip_to_comma (int, int);
5605
static void opt_nest (int, int);
5606
static void opt_chip (int, int);
5607
static void opt_list (int, int);
5608
static void opt_list_symbols (int, int);
5609
 
5610
static const struct opt_action opt_table[] =
5611
{
5612
  { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5613
 
5614
  /* We do relaxing, so there is little use for these options.  */
5615
  { "b", 0, 0, 0, 0 },
5616
  { "brs", 0, 0, 0, 0 },
5617
  { "brb", 0, 0, 0, 0 },
5618
  { "brl", 0, 0, 0, 0 },
5619
  { "brw", 0, 0, 0, 0 },
5620
 
5621
  { "c", 0, 0, 0, 0 },
5622
  { "cex", 0, 0, 0, 0 },
5623
  { "case", 0, &symbols_case_sensitive, 1, 0 },
5624
  { "cl", 0, 0, 0, 0 },
5625
  { "cre", 0, 0, 0, 0 },
5626
  { "d", 0, &flag_keep_locals, 1, 0 },
5627
  { "e", 0, 0, 0, 0 },
5628
  { "f", 0, &flag_short_refs, 1, 0 },
5629
  { "frs", 0, &flag_short_refs, 1, 0 },
5630
  { "frl", 0, &flag_short_refs, 0, 1 },
5631
  { "g", 0, 0, 0, 0 },
5632
  { "i", 0, 0, 0, 0 },
5633
  { "m", 0, 0, 0, 0 },
5634
  { "mex", 0, 0, 0, 0 },
5635
  { "mc", 0, 0, 0, 0 },
5636
  { "md", 0, 0, 0, 0 },
5637
  { "nest", opt_nest, 0, 0, 0 },
5638
  { "next", skip_to_comma, 0, 0, 0 },
5639
  { "o", 0, 0, 0, 0 },
5640
  { "old", 0, 0, 0, 0 },
5641
  { "op", skip_to_comma, 0, 0, 0 },
5642
  { "pco", 0, 0, 0, 0 },
5643
  { "p", opt_chip, 0, 0, 0 },
5644
  { "pcr", 0, 0, 0, 0 },
5645
  { "pcs", 0, 0, 0, 0 },
5646
  { "r", 0, 0, 0, 0 },
5647
  { "quick", 0, &m68k_quick, 1, 0 },
5648
  { "rel32", 0, &m68k_rel32, 1, 0 },
5649
  { "s", opt_list, 0, 0, 0 },
5650
  { "t", opt_list_symbols, 0, 0, 0 },
5651
  { "w", 0, &flag_no_warnings, 0, 1 },
5652
  { "x", 0, 0, 0, 0 }
5653
};
5654
 
5655
#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5656
 
5657
/* The MRI OPT pseudo-op.  */
5658
 
5659
static void
5660
s_opt (int ignore ATTRIBUTE_UNUSED)
5661
{
5662
  do
5663
    {
5664
      int t;
5665
      char *s;
5666
      char c;
5667
      int i;
5668
      const struct opt_action *o;
5669
 
5670
      SKIP_WHITESPACE ();
5671
 
5672
      t = 1;
5673
      if (*input_line_pointer == '-')
5674
        {
5675
          ++input_line_pointer;
5676
          t = 0;
5677
        }
5678
      else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5679
        {
5680
          input_line_pointer += 2;
5681
          t = 0;
5682
        }
5683
 
5684
      s = input_line_pointer;
5685
      c = get_symbol_end ();
5686
 
5687
      for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5688
        {
5689
          if (strcasecmp (s, o->name) == 0)
5690
            {
5691
              if (o->pfn)
5692
                {
5693
                  /* Restore input_line_pointer now in case the option
5694
                     takes arguments.  */
5695
                  *input_line_pointer = c;
5696
                  (*o->pfn) (o->arg, t);
5697
                }
5698
              else if (o->pvar != NULL)
5699
                {
5700
                  if (! t && o->arg == o->notarg)
5701
                    as_bad (_("option `%s' may not be negated"), s);
5702
                  *input_line_pointer = c;
5703
                  *o->pvar = t ? o->arg : o->notarg;
5704
                }
5705
              else
5706
                *input_line_pointer = c;
5707
              break;
5708
            }
5709
        }
5710
      if (i >= OPTCOUNT)
5711
        {
5712
          as_bad (_("option `%s' not recognized"), s);
5713
          *input_line_pointer = c;
5714
        }
5715
    }
5716
  while (*input_line_pointer++ == ',');
5717
 
5718
  /* Move back to terminating character.  */
5719
  --input_line_pointer;
5720
  demand_empty_rest_of_line ();
5721
}
5722
 
5723
/* Skip ahead to a comma.  This is used for OPT options which we do
5724
   not support and which take arguments.  */
5725
 
5726
static void
5727
skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5728
{
5729
  while (*input_line_pointer != ','
5730
         && ! is_end_of_line[(unsigned char) *input_line_pointer])
5731
    ++input_line_pointer;
5732
}
5733
 
5734
/* Handle the OPT NEST=depth option.  */
5735
 
5736
static void
5737
opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5738
{
5739
  if (*input_line_pointer != '=')
5740
    {
5741
      as_bad (_("bad format of OPT NEST=depth"));
5742
      return;
5743
    }
5744
 
5745
  ++input_line_pointer;
5746
  max_macro_nest = get_absolute_expression ();
5747
}
5748
 
5749
/* Handle the OPT P=chip option.  */
5750
 
5751
static void
5752
opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5753
{
5754
  if (*input_line_pointer != '=')
5755
    {
5756
      /* This is just OPT P, which we do not support.  */
5757
      return;
5758
    }
5759
 
5760
  ++input_line_pointer;
5761
  mri_chip ();
5762
}
5763
 
5764
/* Handle the OPT S option.  */
5765
 
5766
static void
5767
opt_list (int arg ATTRIBUTE_UNUSED, int on)
5768
{
5769
  listing_list (on);
5770
}
5771
 
5772
/* Handle the OPT T option.  */
5773
 
5774
static void
5775
opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5776
{
5777
  if (on)
5778
    listing |= LISTING_SYMBOLS;
5779
  else
5780
    listing &= ~LISTING_SYMBOLS;
5781
}
5782
 
5783
/* Handle the MRI REG pseudo-op.  */
5784
 
5785
static void
5786
s_reg (int ignore ATTRIBUTE_UNUSED)
5787
{
5788
  char *s;
5789
  int c;
5790
  struct m68k_op rop;
5791
  int mask;
5792
  char *stop = NULL;
5793
  char stopc;
5794
 
5795
  if (line_label == NULL)
5796
    {
5797
      as_bad (_("missing label"));
5798
      ignore_rest_of_line ();
5799
      return;
5800
    }
5801
 
5802
  if (flag_mri)
5803
    stop = mri_comment_field (&stopc);
5804
 
5805
  SKIP_WHITESPACE ();
5806
 
5807
  s = input_line_pointer;
5808
  while (ISALNUM (*input_line_pointer)
5809
#ifdef REGISTER_PREFIX
5810
         || *input_line_pointer == REGISTER_PREFIX
5811
#endif
5812
         || *input_line_pointer == '/'
5813
         || *input_line_pointer == '-')
5814
    ++input_line_pointer;
5815
  c = *input_line_pointer;
5816
  *input_line_pointer = '\0';
5817
 
5818
  if (m68k_ip_op (s, &rop) != 0)
5819
    {
5820
      if (rop.error == NULL)
5821
        as_bad (_("bad register list"));
5822
      else
5823
        as_bad (_("bad register list: %s"), rop.error);
5824
      *input_line_pointer = c;
5825
      ignore_rest_of_line ();
5826
      return;
5827
    }
5828
 
5829
  *input_line_pointer = c;
5830
 
5831
  if (rop.mode == REGLST)
5832
    mask = rop.mask;
5833
  else if (rop.mode == DREG)
5834
    mask = 1 << (rop.reg - DATA0);
5835
  else if (rop.mode == AREG)
5836
    mask = 1 << (rop.reg - ADDR0 + 8);
5837
  else if (rop.mode == FPREG)
5838
    mask = 1 << (rop.reg - FP0 + 16);
5839
  else if (rop.mode == CONTROL
5840
           && rop.reg == FPI)
5841
    mask = 1 << 24;
5842
  else if (rop.mode == CONTROL
5843
           && rop.reg == FPS)
5844
    mask = 1 << 25;
5845
  else if (rop.mode == CONTROL
5846
           && rop.reg == FPC)
5847
    mask = 1 << 26;
5848
  else
5849
    {
5850
      as_bad (_("bad register list"));
5851
      ignore_rest_of_line ();
5852
      return;
5853
    }
5854
 
5855
  S_SET_SEGMENT (line_label, reg_section);
5856
  S_SET_VALUE (line_label, ~mask);
5857
  symbol_set_frag (line_label, &zero_address_frag);
5858
 
5859
  if (flag_mri)
5860
    mri_comment_end (stop, stopc);
5861
 
5862
  demand_empty_rest_of_line ();
5863
}
5864
 
5865
/* This structure is used for the MRI SAVE and RESTORE pseudo-ops.  */
5866
 
5867
struct save_opts
5868
{
5869
  struct save_opts *next;
5870
  int abspcadd;
5871
  int symbols_case_sensitive;
5872
  int keep_locals;
5873
  int short_refs;
5874
  int architecture;
5875
  const enum m68k_register *control_regs;
5876
  int quick;
5877
  int rel32;
5878
  int listing;
5879
  int no_warnings;
5880
  /* FIXME: We don't save OPT S.  */
5881
};
5882
 
5883
/* This variable holds the stack of saved options.  */
5884
 
5885
static struct save_opts *save_stack;
5886
 
5887
/* The MRI SAVE pseudo-op.  */
5888
 
5889
static void
5890
s_save (int ignore ATTRIBUTE_UNUSED)
5891
{
5892
  struct save_opts *s;
5893
 
5894
  s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5895
  s->abspcadd = m68k_abspcadd;
5896
  s->symbols_case_sensitive = symbols_case_sensitive;
5897
  s->keep_locals = flag_keep_locals;
5898
  s->short_refs = flag_short_refs;
5899
  s->architecture = current_architecture;
5900
  s->control_regs = control_regs;
5901
  s->quick = m68k_quick;
5902
  s->rel32 = m68k_rel32;
5903
  s->listing = listing;
5904
  s->no_warnings = flag_no_warnings;
5905
 
5906
  s->next = save_stack;
5907
  save_stack = s;
5908
 
5909
  demand_empty_rest_of_line ();
5910
}
5911
 
5912
/* The MRI RESTORE pseudo-op.  */
5913
 
5914
static void
5915
s_restore (int ignore ATTRIBUTE_UNUSED)
5916
{
5917
  struct save_opts *s;
5918
 
5919
  if (save_stack == NULL)
5920
    {
5921
      as_bad (_("restore without save"));
5922
      ignore_rest_of_line ();
5923
      return;
5924
    }
5925
 
5926
  s = save_stack;
5927
  save_stack = s->next;
5928
 
5929
  m68k_abspcadd = s->abspcadd;
5930
  symbols_case_sensitive = s->symbols_case_sensitive;
5931
  flag_keep_locals = s->keep_locals;
5932
  flag_short_refs = s->short_refs;
5933
  current_architecture = s->architecture;
5934
  control_regs = s->control_regs;
5935
  m68k_quick = s->quick;
5936
  m68k_rel32 = s->rel32;
5937
  listing = s->listing;
5938
  flag_no_warnings = s->no_warnings;
5939
 
5940
  free (s);
5941
 
5942
  demand_empty_rest_of_line ();
5943
}
5944
 
5945
/* Types of MRI structured control directives.  */
5946
 
5947
enum mri_control_type
5948
{
5949
  mri_for,
5950
  mri_if,
5951
  mri_repeat,
5952
  mri_while
5953
};
5954
 
5955
/* This structure is used to stack the MRI structured control
5956
   directives.  */
5957
 
5958
struct mri_control_info
5959
{
5960
  /* The directive within which this one is enclosed.  */
5961
  struct mri_control_info *outer;
5962
 
5963
  /* The type of directive.  */
5964
  enum mri_control_type type;
5965
 
5966
  /* Whether an ELSE has been in an IF.  */
5967
  int else_seen;
5968
 
5969
  /* The add or sub statement at the end of a FOR.  */
5970
  char *incr;
5971
 
5972
  /* The label of the top of a FOR or REPEAT loop.  */
5973
  char *top;
5974
 
5975
  /* The label to jump to for the next iteration, or the else
5976
     expression of a conditional.  */
5977
  char *next;
5978
 
5979
  /* The label to jump to to break out of the loop, or the label past
5980
     the end of a conditional.  */
5981
  char *bottom;
5982
};
5983
 
5984
/* The stack of MRI structured control directives.  */
5985
 
5986
static struct mri_control_info *mri_control_stack;
5987
 
5988
/* The current MRI structured control directive index number, used to
5989
   generate label names.  */
5990
 
5991
static int mri_control_index;
5992
 
5993
/* Assemble an instruction for an MRI structured control directive.  */
5994
 
5995
static void
5996
mri_assemble (char *str)
5997
{
5998
  char *s;
5999
 
6000
  /* md_assemble expects the opcode to be in lower case.  */
6001
  for (s = str; *s != ' ' && *s != '\0'; s++)
6002
    *s = TOLOWER (*s);
6003
 
6004
  md_assemble (str);
6005
}
6006
 
6007
/* Generate a new MRI label structured control directive label name.  */
6008
 
6009
static char *
6010
mri_control_label (void)
6011
{
6012
  char *n;
6013
 
6014
  n = (char *) xmalloc (20);
6015
  sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6016
  ++mri_control_index;
6017
  return n;
6018
}
6019
 
6020
/* Create a new MRI structured control directive.  */
6021
 
6022
static struct mri_control_info *
6023
push_mri_control (enum mri_control_type type)
6024
{
6025
  struct mri_control_info *n;
6026
 
6027
  n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6028
 
6029
  n->type = type;
6030
  n->else_seen = 0;
6031
  if (type == mri_if || type == mri_while)
6032
    n->top = NULL;
6033
  else
6034
    n->top = mri_control_label ();
6035
  n->next = mri_control_label ();
6036
  n->bottom = mri_control_label ();
6037
 
6038
  n->outer = mri_control_stack;
6039
  mri_control_stack = n;
6040
 
6041
  return n;
6042
}
6043
 
6044
/* Pop off the stack of MRI structured control directives.  */
6045
 
6046
static void
6047
pop_mri_control (void)
6048
{
6049
  struct mri_control_info *n;
6050
 
6051
  n = mri_control_stack;
6052
  mri_control_stack = n->outer;
6053
  if (n->top != NULL)
6054
    free (n->top);
6055
  free (n->next);
6056
  free (n->bottom);
6057
  free (n);
6058
}
6059
 
6060
/* Recognize a condition code in an MRI structured control expression.  */
6061
 
6062
static int
6063
parse_mri_condition (int *pcc)
6064
{
6065
  char c1, c2;
6066
 
6067
  know (*input_line_pointer == '<');
6068
 
6069
  ++input_line_pointer;
6070
  c1 = *input_line_pointer++;
6071
  c2 = *input_line_pointer++;
6072
 
6073
  if (*input_line_pointer != '>')
6074
    {
6075
      as_bad (_("syntax error in structured control directive"));
6076
      return 0;
6077
    }
6078
 
6079
  ++input_line_pointer;
6080
  SKIP_WHITESPACE ();
6081
 
6082
  c1 = TOLOWER (c1);
6083
  c2 = TOLOWER (c2);
6084
 
6085
  *pcc = (c1 << 8) | c2;
6086
 
6087
  return 1;
6088
}
6089
 
6090
/* Parse a single operand in an MRI structured control expression.  */
6091
 
6092
static int
6093
parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6094
                           char **rightstart, char **rightstop)
6095
{
6096
  char *s;
6097
 
6098
  SKIP_WHITESPACE ();
6099
 
6100
  *pcc = -1;
6101
  *leftstart = NULL;
6102
  *leftstop = NULL;
6103
  *rightstart = NULL;
6104
  *rightstop = NULL;
6105
 
6106
  if (*input_line_pointer == '<')
6107
    {
6108
      /* It's just a condition code.  */
6109
      return parse_mri_condition (pcc);
6110
    }
6111
 
6112
  /* Look ahead for the condition code.  */
6113
  for (s = input_line_pointer; *s != '\0'; ++s)
6114
    {
6115
      if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6116
        break;
6117
    }
6118
  if (*s == '\0')
6119
    {
6120
      as_bad (_("missing condition code in structured control directive"));
6121
      return 0;
6122
    }
6123
 
6124
  *leftstart = input_line_pointer;
6125
  *leftstop = s;
6126
  if (*leftstop > *leftstart
6127
      && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6128
    --*leftstop;
6129
 
6130
  input_line_pointer = s;
6131
  if (! parse_mri_condition (pcc))
6132
    return 0;
6133
 
6134
  /* Look ahead for AND or OR or end of line.  */
6135
  for (s = input_line_pointer; *s != '\0'; ++s)
6136
    {
6137
      /* We must make sure we don't misinterpret AND/OR at the end of labels!
6138
         if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6139
                        ^^^                 ^^ */
6140
      if ((s == input_line_pointer
6141
           || *(s-1) == ' '
6142
           || *(s-1) == '\t')
6143
          && ((strncasecmp (s, "AND", 3) == 0
6144
               && (s[3] == '.' || ! is_part_of_name (s[3])))
6145
              || (strncasecmp (s, "OR", 2) == 0
6146
                  && (s[2] == '.' || ! is_part_of_name (s[2])))))
6147
        break;
6148
    }
6149
 
6150
  *rightstart = input_line_pointer;
6151
  *rightstop = s;
6152
  if (*rightstop > *rightstart
6153
      && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6154
    --*rightstop;
6155
 
6156
  input_line_pointer = s;
6157
 
6158
  return 1;
6159
}
6160
 
6161
#define MCC(b1, b2) (((b1) << 8) | (b2))
6162
 
6163
/* Swap the sense of a condition.  This changes the condition so that
6164
   it generates the same result when the operands are swapped.  */
6165
 
6166
static int
6167
swap_mri_condition (int cc)
6168
{
6169
  switch (cc)
6170
    {
6171
    case MCC ('h', 'i'): return MCC ('c', 's');
6172
    case MCC ('l', 's'): return MCC ('c', 'c');
6173
    /* <HS> is an alias for <CC>.  */
6174
    case MCC ('h', 's'):
6175
    case MCC ('c', 'c'): return MCC ('l', 's');
6176
    /* <LO> is an alias for <CS>.  */
6177
    case MCC ('l', 'o'):
6178
    case MCC ('c', 's'): return MCC ('h', 'i');
6179
    case MCC ('p', 'l'): return MCC ('m', 'i');
6180
    case MCC ('m', 'i'): return MCC ('p', 'l');
6181
    case MCC ('g', 'e'): return MCC ('l', 'e');
6182
    case MCC ('l', 't'): return MCC ('g', 't');
6183
    case MCC ('g', 't'): return MCC ('l', 't');
6184
    case MCC ('l', 'e'): return MCC ('g', 'e');
6185
    /* Issue a warning for conditions we can not swap.  */
6186
    case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6187
    case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6188
    case MCC ('v', 'c'):
6189
    case MCC ('v', 's'):
6190
    default :
6191
           as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6192
                         (char) (cc >> 8), (char) (cc));
6193
      break;
6194
    }
6195
  return cc;
6196
}
6197
 
6198
/* Reverse the sense of a condition.  */
6199
 
6200
static int
6201
reverse_mri_condition (int cc)
6202
{
6203
  switch (cc)
6204
    {
6205
    case MCC ('h', 'i'): return MCC ('l', 's');
6206
    case MCC ('l', 's'): return MCC ('h', 'i');
6207
    /* <HS> is an alias for <CC> */
6208
    case MCC ('h', 's'): return MCC ('l', 'o');
6209
    case MCC ('c', 'c'): return MCC ('c', 's');
6210
    /* <LO> is an alias for <CS> */
6211
    case MCC ('l', 'o'): return MCC ('h', 's');
6212
    case MCC ('c', 's'): return MCC ('c', 'c');
6213
    case MCC ('n', 'e'): return MCC ('e', 'q');
6214
    case MCC ('e', 'q'): return MCC ('n', 'e');
6215
    case MCC ('v', 'c'): return MCC ('v', 's');
6216
    case MCC ('v', 's'): return MCC ('v', 'c');
6217
    case MCC ('p', 'l'): return MCC ('m', 'i');
6218
    case MCC ('m', 'i'): return MCC ('p', 'l');
6219
    case MCC ('g', 'e'): return MCC ('l', 't');
6220
    case MCC ('l', 't'): return MCC ('g', 'e');
6221
    case MCC ('g', 't'): return MCC ('l', 'e');
6222
    case MCC ('l', 'e'): return MCC ('g', 't');
6223
    }
6224
  return cc;
6225
}
6226
 
6227
/* Build an MRI structured control expression.  This generates test
6228
   and branch instructions.  It goes to TRUELAB if the condition is
6229
   true, and to FALSELAB if the condition is false.  Exactly one of
6230
   TRUELAB and FALSELAB will be NULL, meaning to fall through.  QUAL
6231
   is the size qualifier for the expression.  EXTENT is the size to
6232
   use for the branch.  */
6233
 
6234
static void
6235
build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6236
                           char *rightstart, char *rightstop,
6237
                           const char *truelab, const char *falselab,
6238
                           int extent)
6239
{
6240
  char *buf;
6241
  char *s;
6242
 
6243
  if (leftstart != NULL)
6244
    {
6245
      struct m68k_op leftop, rightop;
6246
      char c;
6247
 
6248
      /* Swap the compare operands, if necessary, to produce a legal
6249
         m68k compare instruction.  Comparing a register operand with
6250
         a non-register operand requires the register to be on the
6251
         right (cmp, cmpa).  Comparing an immediate value with
6252
         anything requires the immediate value to be on the left
6253
         (cmpi).  */
6254
 
6255
      c = *leftstop;
6256
      *leftstop = '\0';
6257
      (void) m68k_ip_op (leftstart, &leftop);
6258
      *leftstop = c;
6259
 
6260
      c = *rightstop;
6261
      *rightstop = '\0';
6262
      (void) m68k_ip_op (rightstart, &rightop);
6263
      *rightstop = c;
6264
 
6265
      if (rightop.mode == IMMED
6266
          || ((leftop.mode == DREG || leftop.mode == AREG)
6267
              && (rightop.mode != DREG && rightop.mode != AREG)))
6268
        {
6269
          char *temp;
6270
 
6271
          /* Correct conditional handling:
6272
             if #1 <lt> d0 then  ;means if (1 < d0)
6273
                ...
6274
             endi
6275
 
6276
             should assemble to:
6277
 
6278
                cmp #1,d0        if we do *not* swap the operands
6279
                bgt true         we need the swapped condition!
6280
                ble false
6281
             true:
6282
                ...
6283
             false:
6284
          */
6285
          temp = leftstart;
6286
          leftstart = rightstart;
6287
          rightstart = temp;
6288
          temp = leftstop;
6289
          leftstop = rightstop;
6290
          rightstop = temp;
6291
        }
6292
      else
6293
        {
6294
          cc = swap_mri_condition (cc);
6295
        }
6296
    }
6297
 
6298
  if (truelab == NULL)
6299
    {
6300
      cc = reverse_mri_condition (cc);
6301
      truelab = falselab;
6302
    }
6303
 
6304
  if (leftstart != NULL)
6305
    {
6306
      buf = (char *) xmalloc (20
6307
                              + (leftstop - leftstart)
6308
                              + (rightstop - rightstart));
6309
      s = buf;
6310
      *s++ = 'c';
6311
      *s++ = 'm';
6312
      *s++ = 'p';
6313
      if (qual != '\0')
6314
        *s++ = TOLOWER (qual);
6315
      *s++ = ' ';
6316
      memcpy (s, leftstart, leftstop - leftstart);
6317
      s += leftstop - leftstart;
6318
      *s++ = ',';
6319
      memcpy (s, rightstart, rightstop - rightstart);
6320
      s += rightstop - rightstart;
6321
      *s = '\0';
6322
      mri_assemble (buf);
6323
      free (buf);
6324
    }
6325
 
6326
  buf = (char *) xmalloc (20 + strlen (truelab));
6327
  s = buf;
6328
  *s++ = 'b';
6329
  *s++ = cc >> 8;
6330
  *s++ = cc & 0xff;
6331
  if (extent != '\0')
6332
    *s++ = TOLOWER (extent);
6333
  *s++ = ' ';
6334
  strcpy (s, truelab);
6335
  mri_assemble (buf);
6336
  free (buf);
6337
}
6338
 
6339
/* Parse an MRI structured control expression.  This generates test
6340
   and branch instructions.  STOP is where the expression ends.  It
6341
   goes to TRUELAB if the condition is true, and to FALSELAB if the
6342
   condition is false.  Exactly one of TRUELAB and FALSELAB will be
6343
   NULL, meaning to fall through.  QUAL is the size qualifier for the
6344
   expression.  EXTENT is the size to use for the branch.  */
6345
 
6346
static void
6347
parse_mri_control_expression (char *stop, int qual, const char *truelab,
6348
                              const char *falselab, int extent)
6349
{
6350
  int c;
6351
  int cc;
6352
  char *leftstart;
6353
  char *leftstop;
6354
  char *rightstart;
6355
  char *rightstop;
6356
 
6357
  c = *stop;
6358
  *stop = '\0';
6359
 
6360
  if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6361
                                   &rightstart, &rightstop))
6362
    {
6363
      *stop = c;
6364
      return;
6365
    }
6366
 
6367
  if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6368
    {
6369
      const char *flab;
6370
 
6371
      if (falselab != NULL)
6372
        flab = falselab;
6373
      else
6374
        flab = mri_control_label ();
6375
 
6376
      build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6377
                                 rightstop, (const char *) NULL, flab, extent);
6378
 
6379
      input_line_pointer += 3;
6380
      if (*input_line_pointer != '.'
6381
          || input_line_pointer[1] == '\0')
6382
        qual = '\0';
6383
      else
6384
        {
6385
          qual = input_line_pointer[1];
6386
          input_line_pointer += 2;
6387
        }
6388
 
6389
      if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6390
                                       &rightstart, &rightstop))
6391
        {
6392
          *stop = c;
6393
          return;
6394
        }
6395
 
6396
      build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6397
                                 rightstop, truelab, falselab, extent);
6398
 
6399
      if (falselab == NULL)
6400
        colon (flab);
6401
    }
6402
  else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6403
    {
6404
      const char *tlab;
6405
 
6406
      if (truelab != NULL)
6407
        tlab = truelab;
6408
      else
6409
        tlab = mri_control_label ();
6410
 
6411
      build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6412
                                 rightstop, tlab, (const char *) NULL, extent);
6413
 
6414
      input_line_pointer += 2;
6415
      if (*input_line_pointer != '.'
6416
          || input_line_pointer[1] == '\0')
6417
        qual = '\0';
6418
      else
6419
        {
6420
          qual = input_line_pointer[1];
6421
          input_line_pointer += 2;
6422
        }
6423
 
6424
      if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6425
                                       &rightstart, &rightstop))
6426
        {
6427
          *stop = c;
6428
          return;
6429
        }
6430
 
6431
      build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6432
                                 rightstop, truelab, falselab, extent);
6433
 
6434
      if (truelab == NULL)
6435
        colon (tlab);
6436
    }
6437
  else
6438
    {
6439
      build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6440
                                 rightstop, truelab, falselab, extent);
6441
    }
6442
 
6443
  *stop = c;
6444
  if (input_line_pointer != stop)
6445
    as_bad (_("syntax error in structured control directive"));
6446
}
6447
 
6448
/* Handle the MRI IF pseudo-op.  This may be a structured control
6449
   directive, or it may be a regular assembler conditional, depending
6450
   on its operands.  */
6451
 
6452
static void
6453
s_mri_if (int qual)
6454
{
6455
  char *s;
6456
  int c;
6457
  struct mri_control_info *n;
6458
 
6459
  /* A structured control directive must end with THEN with an
6460
     optional qualifier.  */
6461
  s = input_line_pointer;
6462
  /* We only accept '*' as introduction of comments if preceded by white space
6463
     or at first column of a line (I think this can't actually happen here?)
6464
     This is important when assembling:
6465
       if d0 <ne> 12(a0,d0*2) then
6466
       if d0 <ne> #CONST*20   then.  */
6467
  while (! (is_end_of_line[(unsigned char) *s]
6468
            || (flag_mri
6469
                && *s == '*'
6470
                && (s == input_line_pointer
6471
                    || *(s-1) == ' '
6472
                    || *(s-1) == '\t'))))
6473
    ++s;
6474
  --s;
6475
  while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6476
    --s;
6477
 
6478
  if (s - input_line_pointer > 1
6479
      && s[-1] == '.')
6480
    s -= 2;
6481
 
6482
  if (s - input_line_pointer < 3
6483
      || strncasecmp (s - 3, "THEN", 4) != 0)
6484
    {
6485
      if (qual != '\0')
6486
        {
6487
          as_bad (_("missing then"));
6488
          ignore_rest_of_line ();
6489
          return;
6490
        }
6491
 
6492
      /* It's a conditional.  */
6493
      s_if (O_ne);
6494
      return;
6495
    }
6496
 
6497
  /* Since this might be a conditional if, this pseudo-op will be
6498
     called even if we are supported to be ignoring input.  Double
6499
     check now.  Clobber *input_line_pointer so that ignore_input
6500
     thinks that this is not a special pseudo-op.  */
6501
  c = *input_line_pointer;
6502
  *input_line_pointer = 0;
6503
  if (ignore_input ())
6504
    {
6505
      *input_line_pointer = c;
6506
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
6507
        ++input_line_pointer;
6508
      demand_empty_rest_of_line ();
6509
      return;
6510
    }
6511
  *input_line_pointer = c;
6512
 
6513
  n = push_mri_control (mri_if);
6514
 
6515
  parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6516
                                n->next, s[1] == '.' ? s[2] : '\0');
6517
 
6518
  if (s[1] == '.')
6519
    input_line_pointer = s + 3;
6520
  else
6521
    input_line_pointer = s + 1;
6522
 
6523
  if (flag_mri)
6524
    {
6525
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
6526
        ++input_line_pointer;
6527
    }
6528
 
6529
  demand_empty_rest_of_line ();
6530
}
6531
 
6532
/* Handle the MRI else pseudo-op.  If we are currently doing an MRI
6533
   structured IF, associate the ELSE with the IF.  Otherwise, assume
6534
   it is a conditional else.  */
6535
 
6536
static void
6537
s_mri_else (int qual)
6538
{
6539
  int c;
6540
  char *buf;
6541
  char q[2];
6542
 
6543
  if (qual == '\0'
6544
      && (mri_control_stack == NULL
6545
          || mri_control_stack->type != mri_if
6546
          || mri_control_stack->else_seen))
6547
    {
6548
      s_else (0);
6549
      return;
6550
    }
6551
 
6552
  c = *input_line_pointer;
6553
  *input_line_pointer = 0;
6554
  if (ignore_input ())
6555
    {
6556
      *input_line_pointer = c;
6557
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
6558
        ++input_line_pointer;
6559
      demand_empty_rest_of_line ();
6560
      return;
6561
    }
6562
  *input_line_pointer = c;
6563
 
6564
  if (mri_control_stack == NULL
6565
      || mri_control_stack->type != mri_if
6566
      || mri_control_stack->else_seen)
6567
    {
6568
      as_bad (_("else without matching if"));
6569
      ignore_rest_of_line ();
6570
      return;
6571
    }
6572
 
6573
  mri_control_stack->else_seen = 1;
6574
 
6575
  buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6576
  q[0] = TOLOWER (qual);
6577
  q[1] = '\0';
6578
  sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6579
  mri_assemble (buf);
6580
  free (buf);
6581
 
6582
  colon (mri_control_stack->next);
6583
 
6584
  if (flag_mri)
6585
    {
6586
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
6587
        ++input_line_pointer;
6588
    }
6589
 
6590
  demand_empty_rest_of_line ();
6591
}
6592
 
6593
/* Handle the MRI ENDI pseudo-op.  */
6594
 
6595
static void
6596
s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6597
{
6598
  if (mri_control_stack == NULL
6599
      || mri_control_stack->type != mri_if)
6600
    {
6601
      as_bad (_("endi without matching if"));
6602
      ignore_rest_of_line ();
6603
      return;
6604
    }
6605
 
6606
  /* ignore_input will not return true for ENDI, so we don't need to
6607
     worry about checking it again here.  */
6608
 
6609
  if (! mri_control_stack->else_seen)
6610
    colon (mri_control_stack->next);
6611
  colon (mri_control_stack->bottom);
6612
 
6613
  pop_mri_control ();
6614
 
6615
  if (flag_mri)
6616
    {
6617
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
6618
        ++input_line_pointer;
6619
    }
6620
 
6621
  demand_empty_rest_of_line ();
6622
}
6623
 
6624
/* Handle the MRI BREAK pseudo-op.  */
6625
 
6626
static void
6627
s_mri_break (int extent)
6628
{
6629
  struct mri_control_info *n;
6630
  char *buf;
6631
  char ex[2];
6632
 
6633
  n = mri_control_stack;
6634
  while (n != NULL
6635
         && n->type != mri_for
6636
         && n->type != mri_repeat
6637
         && n->type != mri_while)
6638
    n = n->outer;
6639
  if (n == NULL)
6640
    {
6641
      as_bad (_("break outside of structured loop"));
6642
      ignore_rest_of_line ();
6643
      return;
6644
    }
6645
 
6646
  buf = (char *) xmalloc (20 + strlen (n->bottom));
6647
  ex[0] = TOLOWER (extent);
6648
  ex[1] = '\0';
6649
  sprintf (buf, "bra%s %s", ex, n->bottom);
6650
  mri_assemble (buf);
6651
  free (buf);
6652
 
6653
  if (flag_mri)
6654
    {
6655
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
6656
        ++input_line_pointer;
6657
    }
6658
 
6659
  demand_empty_rest_of_line ();
6660
}
6661
 
6662
/* Handle the MRI NEXT pseudo-op.  */
6663
 
6664
static void
6665
s_mri_next (int extent)
6666
{
6667
  struct mri_control_info *n;
6668
  char *buf;
6669
  char ex[2];
6670
 
6671
  n = mri_control_stack;
6672
  while (n != NULL
6673
         && n->type != mri_for
6674
         && n->type != mri_repeat
6675
         && n->type != mri_while)
6676
    n = n->outer;
6677
  if (n == NULL)
6678
    {
6679
      as_bad (_("next outside of structured loop"));
6680
      ignore_rest_of_line ();
6681
      return;
6682
    }
6683
 
6684
  buf = (char *) xmalloc (20 + strlen (n->next));
6685
  ex[0] = TOLOWER (extent);
6686
  ex[1] = '\0';
6687
  sprintf (buf, "bra%s %s", ex, n->next);
6688
  mri_assemble (buf);
6689
  free (buf);
6690
 
6691
  if (flag_mri)
6692
    {
6693
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
6694
        ++input_line_pointer;
6695
    }
6696
 
6697
  demand_empty_rest_of_line ();
6698
}
6699
 
6700
/* Handle the MRI FOR pseudo-op.  */
6701
 
6702
static void
6703
s_mri_for (int qual)
6704
{
6705
  const char *varstart, *varstop;
6706
  const char *initstart, *initstop;
6707
  const char *endstart, *endstop;
6708
  const char *bystart, *bystop;
6709
  int up;
6710
  int by;
6711
  int extent;
6712
  struct mri_control_info *n;
6713
  char *buf;
6714
  char *s;
6715
  char ex[2];
6716
 
6717
  /* The syntax is
6718
       FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6719
     */
6720
 
6721
  SKIP_WHITESPACE ();
6722
  varstart = input_line_pointer;
6723
 
6724
  /* Look for the '='.  */
6725
  while (! is_end_of_line[(unsigned char) *input_line_pointer]
6726
         && *input_line_pointer != '=')
6727
    ++input_line_pointer;
6728
  if (*input_line_pointer != '=')
6729
    {
6730
      as_bad (_("missing ="));
6731
      ignore_rest_of_line ();
6732
      return;
6733
    }
6734
 
6735
  varstop = input_line_pointer;
6736
  if (varstop > varstart
6737
      && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6738
    --varstop;
6739
 
6740
  ++input_line_pointer;
6741
 
6742
  initstart = input_line_pointer;
6743
 
6744
  /* Look for TO or DOWNTO.  */
6745
  up = 1;
6746
  initstop = NULL;
6747
  while (! is_end_of_line[(unsigned char) *input_line_pointer])
6748
    {
6749
      if (strncasecmp (input_line_pointer, "TO", 2) == 0
6750
          && ! is_part_of_name (input_line_pointer[2]))
6751
        {
6752
          initstop = input_line_pointer;
6753
          input_line_pointer += 2;
6754
          break;
6755
        }
6756
      if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6757
          && ! is_part_of_name (input_line_pointer[6]))
6758
        {
6759
          initstop = input_line_pointer;
6760
          up = 0;
6761
          input_line_pointer += 6;
6762
          break;
6763
        }
6764
      ++input_line_pointer;
6765
    }
6766
  if (initstop == NULL)
6767
    {
6768
      as_bad (_("missing to or downto"));
6769
      ignore_rest_of_line ();
6770
      return;
6771
    }
6772
  if (initstop > initstart
6773
      && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6774
    --initstop;
6775
 
6776
  SKIP_WHITESPACE ();
6777
  endstart = input_line_pointer;
6778
 
6779
  /* Look for BY or DO.  */
6780
  by = 0;
6781
  endstop = NULL;
6782
  while (! is_end_of_line[(unsigned char) *input_line_pointer])
6783
    {
6784
      if (strncasecmp (input_line_pointer, "BY", 2) == 0
6785
          && ! is_part_of_name (input_line_pointer[2]))
6786
        {
6787
          endstop = input_line_pointer;
6788
          by = 1;
6789
          input_line_pointer += 2;
6790
          break;
6791
        }
6792
      if (strncasecmp (input_line_pointer, "DO", 2) == 0
6793
          && (input_line_pointer[2] == '.'
6794
              || ! is_part_of_name (input_line_pointer[2])))
6795
        {
6796
          endstop = input_line_pointer;
6797
          input_line_pointer += 2;
6798
          break;
6799
        }
6800
      ++input_line_pointer;
6801
    }
6802
  if (endstop == NULL)
6803
    {
6804
      as_bad (_("missing do"));
6805
      ignore_rest_of_line ();
6806
      return;
6807
    }
6808
  if (endstop > endstart
6809
      && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6810
    --endstop;
6811
 
6812
  if (! by)
6813
    {
6814
      bystart = "#1";
6815
      bystop = bystart + 2;
6816
    }
6817
  else
6818
    {
6819
      SKIP_WHITESPACE ();
6820
      bystart = input_line_pointer;
6821
 
6822
      /* Look for DO.  */
6823
      bystop = NULL;
6824
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
6825
        {
6826
          if (strncasecmp (input_line_pointer, "DO", 2) == 0
6827
              && (input_line_pointer[2] == '.'
6828
                  || ! is_part_of_name (input_line_pointer[2])))
6829
            {
6830
              bystop = input_line_pointer;
6831
              input_line_pointer += 2;
6832
              break;
6833
            }
6834
          ++input_line_pointer;
6835
        }
6836
      if (bystop == NULL)
6837
        {
6838
          as_bad (_("missing do"));
6839
          ignore_rest_of_line ();
6840
          return;
6841
        }
6842
      if (bystop > bystart
6843
          && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6844
        --bystop;
6845
    }
6846
 
6847
  if (*input_line_pointer != '.')
6848
    extent = '\0';
6849
  else
6850
    {
6851
      extent = input_line_pointer[1];
6852
      input_line_pointer += 2;
6853
    }
6854
 
6855
  /* We have fully parsed the FOR operands.  Now build the loop.  */
6856
  n = push_mri_control (mri_for);
6857
 
6858
  buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6859
 
6860
  /* Move init,var.  */
6861
  s = buf;
6862
  *s++ = 'm';
6863
  *s++ = 'o';
6864
  *s++ = 'v';
6865
  *s++ = 'e';
6866
  if (qual != '\0')
6867
    *s++ = TOLOWER (qual);
6868
  *s++ = ' ';
6869
  memcpy (s, initstart, initstop - initstart);
6870
  s += initstop - initstart;
6871
  *s++ = ',';
6872
  memcpy (s, varstart, varstop - varstart);
6873
  s += varstop - varstart;
6874
  *s = '\0';
6875
  mri_assemble (buf);
6876
 
6877
  colon (n->top);
6878
 
6879
  /* cmp end,var.  */
6880
  s = buf;
6881
  *s++ = 'c';
6882
  *s++ = 'm';
6883
  *s++ = 'p';
6884
  if (qual != '\0')
6885
    *s++ = TOLOWER (qual);
6886
  *s++ = ' ';
6887
  memcpy (s, endstart, endstop - endstart);
6888
  s += endstop - endstart;
6889
  *s++ = ',';
6890
  memcpy (s, varstart, varstop - varstart);
6891
  s += varstop - varstart;
6892
  *s = '\0';
6893
  mri_assemble (buf);
6894
 
6895
  /* bcc bottom.  */
6896
  ex[0] = TOLOWER (extent);
6897
  ex[1] = '\0';
6898
  if (up)
6899
    sprintf (buf, "blt%s %s", ex, n->bottom);
6900
  else
6901
    sprintf (buf, "bgt%s %s", ex, n->bottom);
6902
  mri_assemble (buf);
6903
 
6904
  /* Put together the add or sub instruction used by ENDF.  */
6905
  s = buf;
6906
  if (up)
6907
    strcpy (s, "add");
6908
  else
6909
    strcpy (s, "sub");
6910
  s += 3;
6911
  if (qual != '\0')
6912
    *s++ = TOLOWER (qual);
6913
  *s++ = ' ';
6914
  memcpy (s, bystart, bystop - bystart);
6915
  s += bystop - bystart;
6916
  *s++ = ',';
6917
  memcpy (s, varstart, varstop - varstart);
6918
  s += varstop - varstart;
6919
  *s = '\0';
6920
  n->incr = buf;
6921
 
6922
  if (flag_mri)
6923
    {
6924
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
6925
        ++input_line_pointer;
6926
    }
6927
 
6928
  demand_empty_rest_of_line ();
6929
}
6930
 
6931
/* Handle the MRI ENDF pseudo-op.  */
6932
 
6933
static void
6934
s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6935
{
6936
  if (mri_control_stack == NULL
6937
      || mri_control_stack->type != mri_for)
6938
    {
6939
      as_bad (_("endf without for"));
6940
      ignore_rest_of_line ();
6941
      return;
6942
    }
6943
 
6944
  colon (mri_control_stack->next);
6945
 
6946
  mri_assemble (mri_control_stack->incr);
6947
 
6948
  sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6949
  mri_assemble (mri_control_stack->incr);
6950
 
6951
  free (mri_control_stack->incr);
6952
 
6953
  colon (mri_control_stack->bottom);
6954
 
6955
  pop_mri_control ();
6956
 
6957
  if (flag_mri)
6958
    {
6959
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
6960
        ++input_line_pointer;
6961
    }
6962
 
6963
  demand_empty_rest_of_line ();
6964
}
6965
 
6966
/* Handle the MRI REPEAT pseudo-op.  */
6967
 
6968
static void
6969
s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6970
{
6971
  struct mri_control_info *n;
6972
 
6973
  n = push_mri_control (mri_repeat);
6974
  colon (n->top);
6975
  if (flag_mri)
6976
    {
6977
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
6978
        ++input_line_pointer;
6979
    }
6980
  demand_empty_rest_of_line ();
6981
}
6982
 
6983
/* Handle the MRI UNTIL pseudo-op.  */
6984
 
6985
static void
6986
s_mri_until (int qual)
6987
{
6988
  char *s;
6989
 
6990
  if (mri_control_stack == NULL
6991
      || mri_control_stack->type != mri_repeat)
6992
    {
6993
      as_bad (_("until without repeat"));
6994
      ignore_rest_of_line ();
6995
      return;
6996
    }
6997
 
6998
  colon (mri_control_stack->next);
6999
 
7000
  for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7001
    ;
7002
 
7003
  parse_mri_control_expression (s, qual, (const char *) NULL,
7004
                                mri_control_stack->top, '\0');
7005
 
7006
  colon (mri_control_stack->bottom);
7007
 
7008
  input_line_pointer = s;
7009
 
7010
  pop_mri_control ();
7011
 
7012
  if (flag_mri)
7013
    {
7014
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
7015
        ++input_line_pointer;
7016
    }
7017
 
7018
  demand_empty_rest_of_line ();
7019
}
7020
 
7021
/* Handle the MRI WHILE pseudo-op.  */
7022
 
7023
static void
7024
s_mri_while (int qual)
7025
{
7026
  char *s;
7027
 
7028
  struct mri_control_info *n;
7029
 
7030
  s = input_line_pointer;
7031
  /* We only accept '*' as introduction of comments if preceded by white space
7032
     or at first column of a line (I think this can't actually happen here?)
7033
     This is important when assembling:
7034
       while d0 <ne> 12(a0,d0*2) do
7035
       while d0 <ne> #CONST*20   do.  */
7036
  while (! (is_end_of_line[(unsigned char) *s]
7037
            || (flag_mri
7038
                && *s == '*'
7039
                && (s == input_line_pointer
7040
                    || *(s-1) == ' '
7041
                    || *(s-1) == '\t'))))
7042
    s++;
7043
  --s;
7044
  while (*s == ' ' || *s == '\t')
7045
    --s;
7046
  if (s - input_line_pointer > 1
7047
      && s[-1] == '.')
7048
    s -= 2;
7049
  if (s - input_line_pointer < 2
7050
      || strncasecmp (s - 1, "DO", 2) != 0)
7051
    {
7052
      as_bad (_("missing do"));
7053
      ignore_rest_of_line ();
7054
      return;
7055
    }
7056
 
7057
  n = push_mri_control (mri_while);
7058
 
7059
  colon (n->next);
7060
 
7061
  parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7062
                                s[1] == '.' ? s[2] : '\0');
7063
 
7064
  input_line_pointer = s + 1;
7065
  if (*input_line_pointer == '.')
7066
    input_line_pointer += 2;
7067
 
7068
  if (flag_mri)
7069
    {
7070
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
7071
        ++input_line_pointer;
7072
    }
7073
 
7074
  demand_empty_rest_of_line ();
7075
}
7076
 
7077
/* Handle the MRI ENDW pseudo-op.  */
7078
 
7079
static void
7080
s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7081
{
7082
  char *buf;
7083
 
7084
  if (mri_control_stack == NULL
7085
      || mri_control_stack->type != mri_while)
7086
    {
7087
      as_bad (_("endw without while"));
7088
      ignore_rest_of_line ();
7089
      return;
7090
    }
7091
 
7092
  buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7093
  sprintf (buf, "bra %s", mri_control_stack->next);
7094
  mri_assemble (buf);
7095
  free (buf);
7096
 
7097
  colon (mri_control_stack->bottom);
7098
 
7099
  pop_mri_control ();
7100
 
7101
  if (flag_mri)
7102
    {
7103
      while (! is_end_of_line[(unsigned char) *input_line_pointer])
7104
        ++input_line_pointer;
7105
    }
7106
 
7107
  demand_empty_rest_of_line ();
7108
}
7109
 
7110
/* Parse a .cpu directive.  */
7111
 
7112
static void
7113
s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7114
{
7115
  char saved_char;
7116
  char *name;
7117
 
7118
  if (initialized)
7119
    {
7120
      as_bad (_("already assembled instructions"));
7121
      ignore_rest_of_line ();
7122
      return;
7123
    }
7124
 
7125
  name = input_line_pointer;
7126
  while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7127
    input_line_pointer++;
7128
  saved_char = *input_line_pointer;
7129
  *input_line_pointer = 0;
7130
 
7131
  m68k_set_cpu (name, 1, 0);
7132
 
7133
  *input_line_pointer = saved_char;
7134
  demand_empty_rest_of_line ();
7135
  return;
7136
}
7137
 
7138
/* Parse a .arch directive.  */
7139
 
7140
static void
7141
s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7142
{
7143
  char saved_char;
7144
  char *name;
7145
 
7146
  if (initialized)
7147
    {
7148
      as_bad (_("already assembled instructions"));
7149
      ignore_rest_of_line ();
7150
      return;
7151
    }
7152
 
7153
  name = input_line_pointer;
7154
  while (*input_line_pointer && *input_line_pointer != ','
7155
         && !ISSPACE (*input_line_pointer))
7156
    input_line_pointer++;
7157
  saved_char = *input_line_pointer;
7158
  *input_line_pointer = 0;
7159
 
7160
  if (m68k_set_arch (name, 1, 0))
7161
    {
7162
      /* Scan extensions. */
7163
      do
7164
        {
7165
          *input_line_pointer++ = saved_char;
7166
          if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7167
            break;
7168
          name = input_line_pointer;
7169
          while (*input_line_pointer && *input_line_pointer != ','
7170
                 && !ISSPACE (*input_line_pointer))
7171
            input_line_pointer++;
7172
          saved_char = *input_line_pointer;
7173
          *input_line_pointer = 0;
7174
        }
7175
      while (m68k_set_extension (name, 1, 0));
7176
    }
7177
 
7178
  *input_line_pointer = saved_char;
7179
  demand_empty_rest_of_line ();
7180
  return;
7181
}
7182
 
7183
/* Lookup a cpu name in TABLE and return the slot found.  Return NULL
7184
   if none is found, the caller is responsible for emitting an error
7185
   message.  If ALLOW_M is non-zero, we allow an initial 'm' on the
7186
   cpu name, if it begins with a '6' (possibly skipping an intervening
7187
   'c'.  We also allow a 'c' in the same place.  if NEGATED is
7188
   non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7189
   the option is indeed negated.  */
7190
 
7191
static const struct m68k_cpu *
7192
m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7193
                 int allow_m, int *negated)
7194
{
7195
  /* allow negated value? */
7196
  if (negated)
7197
    {
7198
      *negated = 0;
7199
 
7200
      if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7201
        {
7202
          arg += 3;
7203
          *negated = 1;
7204
        }
7205
    }
7206
 
7207
  /* Remove 'm' or 'mc' prefix from 68k variants.  */
7208
  if (allow_m)
7209
    {
7210
      if (arg[0] == 'm')
7211
        {
7212
          if (arg[1] == '6')
7213
            arg += 1;
7214
          else if (arg[1] == 'c'  && arg[2] == '6')
7215
            arg += 2;
7216
        }
7217
    }
7218
  else if (arg[0] == 'c' && arg[1] == '6')
7219
    arg += 1;
7220
 
7221
  for (; table->name; table++)
7222
    if (!strcmp (arg, table->name))
7223
      {
7224
        if (table->alias < -1 || table->alias > 1)
7225
          as_bad (_("`%s' is deprecated, use `%s'"),
7226
                  table->name, table[table->alias < 0 ? 1 : -1].name);
7227
        return table;
7228
      }
7229
  return 0;
7230
}
7231
 
7232
/* Set the cpu, issuing errors if it is unrecognized, or invalid */
7233
 
7234
static int
7235
m68k_set_cpu (char const *name, int allow_m, int silent)
7236
{
7237
  const struct m68k_cpu *cpu;
7238
 
7239
  cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7240
 
7241
  if (!cpu)
7242
    {
7243
      if (!silent)
7244
        as_bad (_("cpu `%s' unrecognized"), name);
7245
      return 0;
7246
    }
7247
 
7248
  if (selected_cpu && selected_cpu != cpu)
7249
    {
7250
      as_bad (_("already selected `%s' processor"),
7251
              selected_cpu->name);
7252
      return 0;
7253
    }
7254
  selected_cpu = cpu;
7255
  return 1;
7256
}
7257
 
7258
/* Set the architecture, issuing errors if it is unrecognized, or invalid */
7259
 
7260
static int
7261
m68k_set_arch (char const *name, int allow_m, int silent)
7262
{
7263
  const struct m68k_cpu *arch;
7264
 
7265
  arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7266
 
7267
  if (!arch)
7268
    {
7269
      if (!silent)
7270
        as_bad (_("architecture `%s' unrecognized"), name);
7271
      return 0;
7272
    }
7273
 
7274
  if (selected_arch && selected_arch != arch)
7275
    {
7276
      as_bad (_("already selected `%s' architecture"),
7277
              selected_arch->name);
7278
      return 0;
7279
    }
7280
 
7281
  selected_arch = arch;
7282
  return 1;
7283
}
7284
 
7285
/* Set the architecture extension, issuing errors if it is
7286
   unrecognized, or invalid */
7287
 
7288
static int
7289
m68k_set_extension (char const *name, int allow_m, int silent)
7290
{
7291
  int negated;
7292
  const struct m68k_cpu *ext;
7293
 
7294
  ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7295
 
7296
  if (!ext)
7297
    {
7298
      if (!silent)
7299
        as_bad (_("extension `%s' unrecognized"), name);
7300
      return 0;
7301
    }
7302
 
7303
  if (negated)
7304
    not_current_architecture |= ext->arch;
7305
  else
7306
    current_architecture |= ext->arch;
7307
  return 1;
7308
}
7309
 
7310
/* md_parse_option
7311
   Invocation line includes a switch not recognized by the base assembler.
7312
 */
7313
 
7314
#ifdef OBJ_ELF
7315
const char *md_shortopts = "lSA:m:kQ:V";
7316
#else
7317
const char *md_shortopts = "lSA:m:k";
7318
#endif
7319
 
7320
struct option md_longopts[] = {
7321
#define OPTION_PIC (OPTION_MD_BASE)
7322
  {"pic", no_argument, NULL, OPTION_PIC},
7323
#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7324
  {"register-prefix-optional", no_argument, NULL,
7325
     OPTION_REGISTER_PREFIX_OPTIONAL},
7326
#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7327
  {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7328
#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7329
  {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7330
#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7331
  {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7332
#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7333
  {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7334
#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7335
  {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7336
#define OPTION_PCREL (OPTION_MD_BASE + 7)
7337
  {"pcrel", no_argument, NULL, OPTION_PCREL},
7338
  {NULL, no_argument, NULL, 0}
7339
};
7340
size_t md_longopts_size = sizeof (md_longopts);
7341
 
7342
int
7343
md_parse_option (int c, char *arg)
7344
{
7345
  switch (c)
7346
    {
7347
    case 'l':                   /* -l means keep external to 2 bit offset
7348
                                   rather than 16 bit one.  */
7349
      flag_short_refs = 1;
7350
      break;
7351
 
7352
    case 'S':                   /* -S means that jbsr's always turn into
7353
                                   jsr's.  */
7354
      flag_long_jumps = 1;
7355
      break;
7356
 
7357
    case OPTION_PCREL:          /* --pcrel means never turn PC-relative
7358
                                   branches into absolute jumps.  */
7359
      flag_keep_pcrel = 1;
7360
      break;
7361
 
7362
    case OPTION_PIC:
7363
    case 'k':
7364
      flag_want_pic = 1;
7365
      break;                    /* -pic, Position Independent Code.  */
7366
 
7367
    case OPTION_REGISTER_PREFIX_OPTIONAL:
7368
      flag_reg_prefix_optional = 1;
7369
      reg_prefix_optional_seen = 1;
7370
      break;
7371
 
7372
      /* -V: SVR4 argument to print version ID.  */
7373
    case 'V':
7374
      print_version_id ();
7375
      break;
7376
 
7377
      /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7378
         should be emitted or not.  FIXME: Not implemented.  */
7379
    case 'Q':
7380
      break;
7381
 
7382
    case OPTION_BITWISE_OR:
7383
      {
7384
        char *n, *t;
7385
        const char *s;
7386
 
7387
        n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7388
        t = n;
7389
        for (s = m68k_comment_chars; *s != '\0'; s++)
7390
          if (*s != '|')
7391
            *t++ = *s;
7392
        *t = '\0';
7393
        m68k_comment_chars = n;
7394
      }
7395
      break;
7396
 
7397
    case OPTION_BASE_SIZE_DEFAULT_16:
7398
      m68k_index_width_default = SIZE_WORD;
7399
      break;
7400
 
7401
    case OPTION_BASE_SIZE_DEFAULT_32:
7402
      m68k_index_width_default = SIZE_LONG;
7403
      break;
7404
 
7405
    case OPTION_DISP_SIZE_DEFAULT_16:
7406
      m68k_rel32 = 0;
7407
      m68k_rel32_from_cmdline = 1;
7408
      break;
7409
 
7410
    case OPTION_DISP_SIZE_DEFAULT_32:
7411
      m68k_rel32 = 1;
7412
      m68k_rel32_from_cmdline = 1;
7413
      break;
7414
 
7415
    case 'A':
7416
#if WARN_DEPRECATED
7417
      as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7418
                    arg, arg));
7419
#endif
7420
      /* Intentional fall-through.  */
7421
    case 'm':
7422
      if (!strncmp (arg, "arch=", 5))
7423
        m68k_set_arch (arg + 5, 1, 0);
7424
      else if (!strncmp (arg, "cpu=", 4))
7425
        m68k_set_cpu (arg + 4, 1, 0);
7426
      else if (m68k_set_extension (arg, 0, 1))
7427
        ;
7428
      else if (m68k_set_arch (arg, 0, 1))
7429
        ;
7430
      else if (m68k_set_cpu (arg, 0, 1))
7431
        ;
7432
      else
7433
        return 0;
7434
      break;
7435
 
7436
    default:
7437
      return 0;
7438
    }
7439
 
7440
  return 1;
7441
}
7442
 
7443
/* Setup tables from the selected arch and/or cpu */
7444
 
7445
static void
7446
m68k_init_arch (void)
7447
{
7448
  if (not_current_architecture & current_architecture)
7449
    {
7450
      as_bad (_("architecture features both enabled and disabled"));
7451
      not_current_architecture &= ~current_architecture;
7452
    }
7453
  if (selected_arch)
7454
    {
7455
      current_architecture |= selected_arch->arch;
7456
      control_regs = selected_arch->control_regs;
7457
    }
7458
  else
7459
    current_architecture |= selected_cpu->arch;
7460
 
7461
  current_architecture &= ~not_current_architecture;
7462
 
7463
  if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7464
    {
7465
      /* Determine which float is really meant.  */
7466
      if (current_architecture & (m68k_mask & ~m68881))
7467
        current_architecture ^= cfloat;
7468
      else
7469
        current_architecture ^= m68881;
7470
    }
7471
 
7472
  if (selected_cpu)
7473
    {
7474
      control_regs = selected_cpu->control_regs;
7475
      if (current_architecture & ~selected_cpu->arch)
7476
        {
7477
          as_bad (_("selected processor does not have all features of selected architecture"));
7478
          current_architecture
7479
            = selected_cpu->arch & ~not_current_architecture;
7480
        }
7481
    }
7482
 
7483
  if ((current_architecture & m68k_mask)
7484
      && (current_architecture & ~m68k_mask))
7485
    {
7486
      as_bad (_ ("m68k and cf features both selected"));
7487
      if (current_architecture & m68k_mask)
7488
        current_architecture &= m68k_mask;
7489
      else
7490
        current_architecture &= ~m68k_mask;
7491
    }
7492
 
7493
  /* Permit m68881 specification with all cpus; those that can't work
7494
     with a coprocessor could be doing emulation.  */
7495
  if (current_architecture & m68851)
7496
    {
7497
      if (current_architecture & m68040)
7498
        as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7499
    }
7500
  /* What other incompatibilities could we check for?  */
7501
 
7502
  if (cpu_of_arch (current_architecture) < m68020
7503
      || arch_coldfire_p (current_architecture))
7504
    md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7505
 
7506
  initialized = 1;
7507
}
7508
 
7509
void
7510
md_show_usage (FILE *stream)
7511
{
7512
  const char *default_cpu = TARGET_CPU;
7513
  int i;
7514
  unsigned int default_arch;
7515
 
7516
  /* Get the canonical name for the default target CPU.  */
7517
  if (*default_cpu == 'm')
7518
    default_cpu++;
7519
  for (i = 0; m68k_cpus[i].name; i++)
7520
    {
7521
      if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7522
        {
7523
          default_arch = m68k_cpus[i].arch;
7524
          while (m68k_cpus[i].alias > 0)
7525
            i--;
7526
          while (m68k_cpus[i].alias < 0)
7527
            i++;
7528
          default_cpu = m68k_cpus[i].name;
7529
        }
7530
    }
7531
 
7532
  fprintf (stream, _("\
7533
-march=<arch>           set architecture\n\
7534
-mcpu=<cpu>             set cpu [default %s]\n\
7535
"), default_cpu);
7536
  for (i = 0; m68k_extensions[i].name; i++)
7537
    fprintf (stream, _("\
7538
-m[no-]%-16s enable/disable%s architecture extension\n\
7539
"), m68k_extensions[i].name,
7540
             m68k_extensions[i].alias > 0 ? " ColdFire"
7541
             : m68k_extensions[i].alias < 0 ? " m68k" : "");
7542
 
7543
  fprintf (stream, _("\
7544
-l                      use 1 word for refs to undefined symbols [default 2]\n\
7545
-pic, -k                generate position independent code\n\
7546
-S                      turn jbsr into jsr\n\
7547
--pcrel                 never turn PC-relative branches into absolute jumps\n\
7548
--register-prefix-optional\n\
7549
                        recognize register names without prefix character\n\
7550
--bitwise-or            do not treat `|' as a comment character\n\
7551
--base-size-default-16  base reg without size is 16 bits\n\
7552
--base-size-default-32  base reg without size is 32 bits (default)\n\
7553
--disp-size-default-16  displacement with unknown size is 16 bits\n\
7554
--disp-size-default-32  displacement with unknown size is 32 bits (default)\n\
7555
"));
7556
 
7557
  fprintf (stream, _("Architecture variants are: "));
7558
  for (i = 0; m68k_archs[i].name; i++)
7559
    {
7560
      if (i)
7561
        fprintf (stream, " | ");
7562
      fprintf (stream, m68k_archs[i].name);
7563
    }
7564
  fprintf (stream, "\n");
7565
 
7566
  fprintf (stream, _("Processor variants are: "));
7567
  for (i = 0; m68k_cpus[i].name; i++)
7568
    {
7569
      if (i)
7570
        fprintf (stream, " | ");
7571
      fprintf (stream, m68k_cpus[i].name);
7572
    }
7573
  fprintf (stream, _("\n"));
7574
}
7575
 
7576
#ifdef TEST2
7577
 
7578
/* TEST2:  Test md_assemble() */
7579
/* Warning, this routine probably doesn't work anymore.  */
7580
int
7581
main (void)
7582
{
7583
  struct m68k_it the_ins;
7584
  char buf[120];
7585
  char *cp;
7586
  int n;
7587
 
7588
  m68k_ip_begin ();
7589
  for (;;)
7590
    {
7591
      if (!gets (buf) || !*buf)
7592
        break;
7593
      if (buf[0] == '|' || buf[1] == '.')
7594
        continue;
7595
      for (cp = buf; *cp; cp++)
7596
        if (*cp == '\t')
7597
          *cp = ' ';
7598
      if (is_label (buf))
7599
        continue;
7600
      memset (&the_ins, '\0', sizeof (the_ins));
7601
      m68k_ip (&the_ins, buf);
7602
      if (the_ins.error)
7603
        {
7604
          printf (_("Error %s in %s\n"), the_ins.error, buf);
7605
        }
7606
      else
7607
        {
7608
          printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7609
          for (n = 0; n < the_ins.numo; n++)
7610
            printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7611
          printf ("    ");
7612
          print_the_insn (&the_ins.opcode[0], stdout);
7613
          (void) putchar ('\n');
7614
        }
7615
      for (n = 0; n < strlen (the_ins.args) / 2; n++)
7616
        {
7617
          if (the_ins.operands[n].error)
7618
            {
7619
              printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7620
              continue;
7621
            }
7622
          printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7623
                  the_ins.operands[n].reg);
7624
          if (the_ins.operands[n].b_const)
7625
            printf ("Constant: '%.*s', ",
7626
                    1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7627
                    the_ins.operands[n].b_const);
7628
          printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7629
                  the_ins.operands[n].isiz, the_ins.operands[n].imul);
7630
          if (the_ins.operands[n].b_iadd)
7631
            printf ("Iadd: '%.*s',",
7632
                    1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7633
                    the_ins.operands[n].b_iadd);
7634
          putchar ('\n');
7635
        }
7636
    }
7637
  m68k_ip_end ();
7638
  return 0;
7639
}
7640
 
7641
int
7642
is_label (char *str)
7643
{
7644
  while (*str == ' ')
7645
    str++;
7646
  while (*str && *str != ' ')
7647
    str++;
7648
  if (str[-1] == ':' || str[1] == '=')
7649
    return 1;
7650
  return 0;
7651
}
7652
 
7653
#endif
7654
 
7655
/* Possible states for relaxation:
7656
 
7657
 
7658
 
7659
 
7660
 
7661
   1 0  indexed offsets byte    a0@(32,d4:w:1) etc
7662
   1 1                  word
7663
   1 2                  long
7664
 
7665
   2 0  two-offset index word-word a0@(32,d4)@(45) etc
7666
   2 1                  word-long
7667
   2 2                  long-word
7668
   2 3                  long-long
7669
 
7670
   */
7671
 
7672
/* We have no need to default values of symbols.  */
7673
 
7674
symbolS *
7675
md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7676
{
7677
  return 0;
7678
}
7679
 
7680
/* Round up a section size to the appropriate boundary.  */
7681
valueT
7682
md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7683
{
7684
#ifdef OBJ_AOUT
7685
  /* For a.out, force the section size to be aligned.  If we don't do
7686
     this, BFD will align it for us, but it will not write out the
7687
     final bytes of the section.  This may be a bug in BFD, but it is
7688
     easier to fix it here since that is how the other a.out targets
7689
     work.  */
7690
  int align;
7691
 
7692
  align = bfd_get_section_alignment (stdoutput, segment);
7693
  size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7694
#endif
7695
 
7696
  return size;
7697
}
7698
 
7699
/* Exactly what point is a PC-relative offset relative TO?
7700
   On the 68k, it is relative to the address of the first extension
7701
   word.  The difference between the addresses of the offset and the
7702
   first extension word is stored in fx_pcrel_adjust.  */
7703
long
7704
md_pcrel_from (fixS *fixP)
7705
{
7706
  int adjust;
7707
 
7708
  /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7709
     sign extend the value here.  */
7710
  adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7711
  if (adjust == 64)
7712
    adjust = -1;
7713
  return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7714
}
7715
 
7716
#ifdef OBJ_ELF
7717
void
7718
m68k_elf_final_processing (void)
7719
{
7720
  unsigned flags = 0;
7721
 
7722
  if (arch_coldfire_fpu (current_architecture))
7723
    flags |= EF_M68K_CFV4E;
7724
  /* Set file-specific flags if this is a cpu32 processor.  */
7725
  if (cpu_of_arch (current_architecture) & cpu32)
7726
    flags |= EF_M68K_CPU32;
7727
  else if (cpu_of_arch (current_architecture) & fido_a)
7728
    flags |= EF_M68K_FIDO;
7729
  else if ((cpu_of_arch (current_architecture) & m68000up)
7730
           && !(cpu_of_arch (current_architecture) & m68020up))
7731
    flags |= EF_M68K_M68000;
7732
 
7733
  if (current_architecture & mcfisa_a)
7734
    {
7735
      static const unsigned isa_features[][2] =
7736
      {
7737
        {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7738
        {EF_M68K_CF_ISA_A,      mcfisa_a|mcfhwdiv},
7739
        {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7740
        {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7741
        {EF_M68K_CF_ISA_B,      mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7742
        {EF_M68K_CF_ISA_C,      mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7743
        {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7744
        {0,0},
7745
      };
7746
      static const unsigned mac_features[][2] =
7747
      {
7748
        {EF_M68K_CF_MAC, mcfmac},
7749
        {EF_M68K_CF_EMAC, mcfemac},
7750
        {0,0},
7751
      };
7752
      unsigned ix;
7753
      unsigned pattern;
7754
 
7755
      pattern = (current_architecture
7756
                 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7757
      for (ix = 0; isa_features[ix][1]; ix++)
7758
        {
7759
          if (pattern == isa_features[ix][1])
7760
            {
7761
              flags |= isa_features[ix][0];
7762
              break;
7763
            }
7764
        }
7765
      if (!isa_features[ix][1])
7766
        {
7767
        cf_bad:
7768
          as_warn (_("Not a defined coldfire architecture"));
7769
        }
7770
      else
7771
        {
7772
          if (current_architecture & cfloat)
7773
            flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7774
 
7775
          pattern = current_architecture & (mcfmac|mcfemac);
7776
          if (pattern)
7777
            {
7778
              for (ix = 0; mac_features[ix][1]; ix++)
7779
                {
7780
                  if (pattern == mac_features[ix][1])
7781
                    {
7782
                      flags |= mac_features[ix][0];
7783
                      break;
7784
                    }
7785
                }
7786
              if (!mac_features[ix][1])
7787
                goto cf_bad;
7788
            }
7789
        }
7790
    }
7791
  elf_elfheader (stdoutput)->e_flags |= flags;
7792
}
7793
#endif
7794
 
7795
int
7796
tc_m68k_regname_to_dw2regnum (char *regname)
7797
{
7798
  unsigned int regnum;
7799
  static const char *const regnames[] =
7800
    {
7801
      "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7802
      "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7803
      "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7804
      "pc"
7805
    };
7806
 
7807
  for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7808
    if (strcmp (regname, regnames[regnum]) == 0)
7809
      return regnum;
7810
 
7811
  return -1;
7812
}
7813
 
7814
void
7815
tc_m68k_frame_initial_instructions (void)
7816
{
7817
  static int sp_regno = -1;
7818
 
7819
  if (sp_regno < 0)
7820
    sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7821
 
7822
  cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7823
  cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7824
}

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