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[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [config/] [tc-sparc.c] - Blame information for rev 816

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/* tc-sparc.c -- Assemble for the SPARC
2
   Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3
   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4
   Free Software Foundation, Inc.
5
   This file is part of GAS, the GNU Assembler.
6
 
7
   GAS is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   GAS is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public
18
   License along with GAS; see the file COPYING.  If not, write
19
   to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20
   Boston, MA 02110-1301, USA.  */
21
 
22
#include "as.h"
23
#include "safe-ctype.h"
24
#include "subsegs.h"
25
 
26
#include "opcode/sparc.h"
27
#include "dw2gencfi.h"
28
 
29
#ifdef OBJ_ELF
30
#include "elf/sparc.h"
31
#include "dwarf2dbg.h"
32
#endif
33
 
34
/* Some ancient Sun C compilers would not take such hex constants as
35
   unsigned, and would end up sign-extending them to form an offsetT,
36
   so use these constants instead.  */
37
#define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
38
#define U0x80000000 ((((unsigned long) 1 << 16) << 15))
39
 
40
static struct sparc_arch *lookup_arch PARAMS ((char *));
41
static void init_default_arch PARAMS ((void));
42
static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
43
static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
44
static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
45
static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
46
static int sparc_ffs PARAMS ((unsigned int));
47
static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
48
static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
49
static void synthetize_setx PARAMS ((const struct sparc_opcode *));
50
static bfd_vma BSR PARAMS ((bfd_vma, int));
51
static int cmp_reg_entry PARAMS ((const PTR, const PTR));
52
static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
53
static int parse_const_expr_arg PARAMS ((char **, int *));
54
static int get_expression PARAMS ((char *str));
55
 
56
/* Default architecture.  */
57
/* ??? The default value should be V8, but sparclite support was added
58
   by making it the default.  GCC now passes -Asparclite, so maybe sometime in
59
   the future we can set this to V8.  */
60
#ifndef DEFAULT_ARCH
61
#define DEFAULT_ARCH "sparclite"
62
#endif
63
static char *default_arch = DEFAULT_ARCH;
64
 
65
/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
66
   have been set.  */
67
static int default_init_p;
68
 
69
/* Current architecture.  We don't bump up unless necessary.  */
70
static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
71
 
72
/* The maximum architecture level we can bump up to.
73
   In a 32 bit environment, don't allow bumping up to v9 by default.
74
   The native assembler works this way.  The user is required to pass
75
   an explicit argument before we'll create v9 object files.  However, if
76
   we don't see any v9 insns, a v8plus object file is not created.  */
77
static enum sparc_opcode_arch_val max_architecture;
78
 
79
/* Either 32 or 64, selects file format.  */
80
static int sparc_arch_size;
81
/* Initial (default) value, recorded separately in case a user option
82
   changes the value before md_show_usage is called.  */
83
static int default_arch_size;
84
 
85
#ifdef OBJ_ELF
86
/* The currently selected v9 memory model.  Currently only used for
87
   ELF.  */
88
static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
89
#endif
90
 
91
static int architecture_requested;
92
static int warn_on_bump;
93
 
94
/* If warn_on_bump and the needed architecture is higher than this
95
   architecture, issue a warning.  */
96
static enum sparc_opcode_arch_val warn_after_architecture;
97
 
98
/* Non-zero if as should generate error if an undeclared g[23] register
99
   has been used in -64.  */
100
static int no_undeclared_regs;
101
 
102
/* Non-zero if we should try to relax jumps and calls.  */
103
static int sparc_relax;
104
 
105
/* Non-zero if we are generating PIC code.  */
106
int sparc_pic_code;
107
 
108
/* Non-zero if we should give an error when misaligned data is seen.  */
109
static int enforce_aligned_data;
110
 
111
extern int target_big_endian;
112
 
113
static int target_little_endian_data;
114
 
115
/* Symbols for global registers on v9.  */
116
static symbolS *globals[8];
117
 
118
/* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
119
int sparc_cie_data_alignment;
120
 
121
/* V9 and 86x have big and little endian data, but instructions are always big
122
   endian.  The sparclet has bi-endian support but both data and insns have
123
   the same endianness.  Global `target_big_endian' is used for data.
124
   The following macro is used for instructions.  */
125
#ifndef INSN_BIG_ENDIAN
126
#define INSN_BIG_ENDIAN (target_big_endian \
127
                         || default_arch_type == sparc86x \
128
                         || SPARC_OPCODE_ARCH_V9_P (max_architecture))
129
#endif
130
 
131
/* Handle of the OPCODE hash table.  */
132
static struct hash_control *op_hash;
133
 
134
static int mylog2 PARAMS ((int));
135
static void s_data1 PARAMS ((void));
136
static void s_seg PARAMS ((int));
137
static void s_proc PARAMS ((int));
138
static void s_reserve PARAMS ((int));
139
static void s_common PARAMS ((int));
140
static void s_empty PARAMS ((int));
141
static void s_uacons PARAMS ((int));
142
static void s_ncons PARAMS ((int));
143
#ifdef OBJ_ELF
144
static void s_register PARAMS ((int));
145
#endif
146
 
147
const pseudo_typeS md_pseudo_table[] =
148
{
149
  {"align", s_align_bytes, 0},   /* Defaulting is invalid (0).  */
150
  {"common", s_common, 0},
151
  {"empty", s_empty, 0},
152
  {"global", s_globl, 0},
153
  {"half", cons, 2},
154
  {"nword", s_ncons, 0},
155
  {"optim", s_ignore, 0},
156
  {"proc", s_proc, 0},
157
  {"reserve", s_reserve, 0},
158
  {"seg", s_seg, 0},
159
  {"skip", s_space, 0},
160
  {"word", cons, 4},
161
  {"xword", cons, 8},
162
  {"uahalf", s_uacons, 2},
163
  {"uaword", s_uacons, 4},
164
  {"uaxword", s_uacons, 8},
165
#ifdef OBJ_ELF
166
  /* These are specific to sparc/svr4.  */
167
  {"2byte", s_uacons, 2},
168
  {"4byte", s_uacons, 4},
169
  {"8byte", s_uacons, 8},
170
  {"register", s_register, 0},
171
#endif
172
  {NULL, 0, 0},
173
};
174
 
175
/* This array holds the chars that always start a comment.  If the
176
   pre-processor is disabled, these aren't very useful.  */
177
const char comment_chars[] = "!";       /* JF removed '|' from
178
                                           comment_chars.  */
179
 
180
/* This array holds the chars that only start a comment at the beginning of
181
   a line.  If the line seems to have the form '# 123 filename'
182
   .line and .file directives will appear in the pre-processed output.  */
183
/* Note that input_file.c hand checks for '#' at the beginning of the
184
   first line of the input file.  This is because the compiler outputs
185
   #NO_APP at the beginning of its output.  */
186
/* Also note that comments started like this one will always
187
   work if '/' isn't otherwise defined.  */
188
const char line_comment_chars[] = "#";
189
 
190
const char line_separator_chars[] = ";";
191
 
192
/* Chars that can be used to separate mant from exp in floating point
193
   nums.  */
194
const char EXP_CHARS[] = "eE";
195
 
196
/* Chars that mean this number is a floating point constant.
197
   As in 0f12.456
198
   or    0d1.2345e12  */
199
const char FLT_CHARS[] = "rRsSfFdDxXpP";
200
 
201
/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
202
   changed in read.c.  Ideally it shouldn't have to know about it at all,
203
   but nothing is ideal around here.  */
204
 
205
#define isoctal(c)  ((unsigned) ((c) - '0') < 8)
206
 
207
struct sparc_it
208
  {
209
    char *error;
210
    unsigned long opcode;
211
    struct nlist *nlistp;
212
    expressionS exp;
213
    expressionS exp2;
214
    int pcrel;
215
    bfd_reloc_code_real_type reloc;
216
  };
217
 
218
struct sparc_it the_insn, set_insn;
219
 
220
static void output_insn
221
  PARAMS ((const struct sparc_opcode *, struct sparc_it *));
222
 
223
/* Table of arguments to -A.
224
   The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
225
   for this use.  That table is for opcodes only.  This table is for opcodes
226
   and file formats.  */
227
 
228
enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
229
                       v8plusa, v9, v9a, v9b, v9_64};
230
 
231
static struct sparc_arch {
232
  char *name;
233
  char *opcode_arch;
234
  enum sparc_arch_types arch_type;
235
  /* Default word size, as specified during configuration.
236
     A value of zero means can't be used to specify default architecture.  */
237
  int default_arch_size;
238
  /* Allowable arg to -A?  */
239
  int user_option_p;
240
} sparc_arch_table[] = {
241
  { "v6", "v6", v6, 0, 1 },
242
  { "v7", "v7", v7, 0, 1 },
243
  { "v8", "v8", v8, 32, 1 },
244
  { "sparclet", "sparclet", sparclet, 32, 1 },
245
  { "sparclite", "sparclite", sparclite, 32, 1 },
246
  { "sparc86x", "sparclite", sparc86x, 32, 1 },
247
  { "v8plus", "v9", v9, 0, 1 },
248
  { "v8plusa", "v9a", v9, 0, 1 },
249
  { "v8plusb", "v9b", v9, 0, 1 },
250
  { "v9", "v9", v9, 0, 1 },
251
  { "v9a", "v9a", v9, 0, 1 },
252
  { "v9b", "v9b", v9, 0, 1 },
253
  /* This exists to allow configure.in/Makefile.in to pass one
254
     value to specify both the default machine and default word size.  */
255
  { "v9-64", "v9", v9, 64, 0 },
256
  { NULL, NULL, v8, 0, 0 }
257
};
258
 
259
/* Variant of default_arch */
260
static enum sparc_arch_types default_arch_type;
261
 
262
static struct sparc_arch *
263
lookup_arch (name)
264
     char *name;
265
{
266
  struct sparc_arch *sa;
267
 
268
  for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
269
    if (strcmp (sa->name, name) == 0)
270
      break;
271
  if (sa->name == NULL)
272
    return NULL;
273
  return sa;
274
}
275
 
276
/* Initialize the default opcode arch and word size from the default
277
   architecture name.  */
278
 
279
static void
280
init_default_arch ()
281
{
282
  struct sparc_arch *sa = lookup_arch (default_arch);
283
 
284
  if (sa == NULL
285
      || sa->default_arch_size == 0)
286
    as_fatal (_("Invalid default architecture, broken assembler."));
287
 
288
  max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
289
  if (max_architecture == SPARC_OPCODE_ARCH_BAD)
290
    as_fatal (_("Bad opcode table, broken assembler."));
291
  default_arch_size = sparc_arch_size = sa->default_arch_size;
292
  default_init_p = 1;
293
  default_arch_type = sa->arch_type;
294
}
295
 
296
/* Called by TARGET_FORMAT.  */
297
 
298
const char *
299
sparc_target_format ()
300
{
301
  /* We don't get a chance to initialize anything before we're called,
302
     so handle that now.  */
303
  if (! default_init_p)
304
    init_default_arch ();
305
 
306
#ifdef OBJ_AOUT
307
#ifdef TE_NetBSD
308
  return "a.out-sparc-netbsd";
309
#else
310
#ifdef TE_SPARCAOUT
311
  if (target_big_endian)
312
    return "a.out-sunos-big";
313
  else if (default_arch_type == sparc86x && target_little_endian_data)
314
    return "a.out-sunos-big";
315
  else
316
    return "a.out-sparc-little";
317
#else
318
  return "a.out-sunos-big";
319
#endif
320
#endif
321
#endif
322
 
323
#ifdef OBJ_BOUT
324
  return "b.out.big";
325
#endif
326
 
327
#ifdef OBJ_COFF
328
#ifdef TE_LYNX
329
  return "coff-sparc-lynx";
330
#else
331
  return "coff-sparc";
332
#endif
333
#endif
334
 
335
#ifdef TE_VXWORKS
336
  return "elf32-sparc-vxworks";
337
#endif
338
 
339
#ifdef OBJ_ELF
340
  return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
341
#endif
342
 
343
  abort ();
344
}
345
 
346
/* md_parse_option
347
 *      Invocation line includes a switch not recognized by the base assembler.
348
 *      See if it's a processor-specific option.  These are:
349
 *
350
 *      -bump
351
 *              Warn on architecture bumps.  See also -A.
352
 *
353
 *      -Av6, -Av7, -Av8, -Asparclite, -Asparclet
354
 *              Standard 32 bit architectures.
355
 *      -Av9, -Av9a, -Av9b
356
 *              Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
357
 *              This used to only mean 64 bits, but properly specifying it
358
 *              complicated gcc's ASM_SPECs, so now opcode selection is
359
 *              specified orthogonally to word size (except when specifying
360
 *              the default, but that is an internal implementation detail).
361
 *      -Av8plus, -Av8plusa, -Av8plusb
362
 *              Same as -Av9{,a,b}.
363
 *      -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
364
 *              Same as -Av8plus{,a,b} -32, for compatibility with Sun's
365
 *              assembler.
366
 *      -xarch=v9, -xarch=v9a, -xarch=v9b
367
 *              Same as -Av9{,a,b} -64, for compatibility with Sun's
368
 *              assembler.
369
 *
370
 *              Select the architecture and possibly the file format.
371
 *              Instructions or features not supported by the selected
372
 *              architecture cause fatal errors.
373
 *
374
 *              The default is to start at v6, and bump the architecture up
375
 *              whenever an instruction is seen at a higher level.  In 32 bit
376
 *              environments, v9 is not bumped up to, the user must pass
377
 *              -Av8plus{,a,b}.
378
 *
379
 *              If -bump is specified, a warning is printing when bumping to
380
 *              higher levels.
381
 *
382
 *              If an architecture is specified, all instructions must match
383
 *              that architecture.  Any higher level instructions are flagged
384
 *              as errors.  Note that in the 32 bit environment specifying
385
 *              -Av8plus does not automatically create a v8plus object file, a
386
 *              v9 insn must be seen.
387
 *
388
 *              If both an architecture and -bump are specified, the
389
 *              architecture starts at the specified level, but bumps are
390
 *              warnings.  Note that we can't set `current_architecture' to
391
 *              the requested level in this case: in the 32 bit environment,
392
 *              we still must avoid creating v8plus object files unless v9
393
 *              insns are seen.
394
 *
395
 * Note:
396
 *              Bumping between incompatible architectures is always an
397
 *              error.  For example, from sparclite to v9.
398
 */
399
 
400
#ifdef OBJ_ELF
401
const char *md_shortopts = "A:K:VQ:sq";
402
#else
403
#ifdef OBJ_AOUT
404
const char *md_shortopts = "A:k";
405
#else
406
const char *md_shortopts = "A:";
407
#endif
408
#endif
409
struct option md_longopts[] = {
410
#define OPTION_BUMP (OPTION_MD_BASE)
411
  {"bump", no_argument, NULL, OPTION_BUMP},
412
#define OPTION_SPARC (OPTION_MD_BASE + 1)
413
  {"sparc", no_argument, NULL, OPTION_SPARC},
414
#define OPTION_XARCH (OPTION_MD_BASE + 2)
415
  {"xarch", required_argument, NULL, OPTION_XARCH},
416
#ifdef OBJ_ELF
417
#define OPTION_32 (OPTION_MD_BASE + 3)
418
  {"32", no_argument, NULL, OPTION_32},
419
#define OPTION_64 (OPTION_MD_BASE + 4)
420
  {"64", no_argument, NULL, OPTION_64},
421
#define OPTION_TSO (OPTION_MD_BASE + 5)
422
  {"TSO", no_argument, NULL, OPTION_TSO},
423
#define OPTION_PSO (OPTION_MD_BASE + 6)
424
  {"PSO", no_argument, NULL, OPTION_PSO},
425
#define OPTION_RMO (OPTION_MD_BASE + 7)
426
  {"RMO", no_argument, NULL, OPTION_RMO},
427
#endif
428
#ifdef SPARC_BIENDIAN
429
#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
430
  {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
431
#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
432
  {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
433
#endif
434
#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
435
  {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
436
#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
437
  {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
438
#ifdef OBJ_ELF
439
#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
440
  {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
441
#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
442
  {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
443
#endif
444
#define OPTION_RELAX (OPTION_MD_BASE + 14)
445
  {"relax", no_argument, NULL, OPTION_RELAX},
446
#define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
447
  {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
448
  {NULL, no_argument, NULL, 0}
449
};
450
 
451
size_t md_longopts_size = sizeof (md_longopts);
452
 
453
int
454
md_parse_option (c, arg)
455
     int c;
456
     char *arg;
457
{
458
  /* We don't get a chance to initialize anything before we're called,
459
     so handle that now.  */
460
  if (! default_init_p)
461
    init_default_arch ();
462
 
463
  switch (c)
464
    {
465
    case OPTION_BUMP:
466
      warn_on_bump = 1;
467
      warn_after_architecture = SPARC_OPCODE_ARCH_V6;
468
      break;
469
 
470
    case OPTION_XARCH:
471
#ifdef OBJ_ELF
472
      if (strncmp (arg, "v9", 2) != 0)
473
        md_parse_option (OPTION_32, NULL);
474
      else
475
        md_parse_option (OPTION_64, NULL);
476
#endif
477
      /* Fall through.  */
478
 
479
    case 'A':
480
      {
481
        struct sparc_arch *sa;
482
        enum sparc_opcode_arch_val opcode_arch;
483
 
484
        sa = lookup_arch (arg);
485
        if (sa == NULL
486
            || ! sa->user_option_p)
487
          {
488
            if (c == OPTION_XARCH)
489
              as_bad (_("invalid architecture -xarch=%s"), arg);
490
            else
491
              as_bad (_("invalid architecture -A%s"), arg);
492
            return 0;
493
          }
494
 
495
        opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
496
        if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
497
          as_fatal (_("Bad opcode table, broken assembler."));
498
 
499
        max_architecture = opcode_arch;
500
        architecture_requested = 1;
501
      }
502
      break;
503
 
504
    case OPTION_SPARC:
505
      /* Ignore -sparc, used by SunOS make default .s.o rule.  */
506
      break;
507
 
508
    case OPTION_ENFORCE_ALIGNED_DATA:
509
      enforce_aligned_data = 1;
510
      break;
511
 
512
#ifdef SPARC_BIENDIAN
513
    case OPTION_LITTLE_ENDIAN:
514
      target_big_endian = 0;
515
      if (default_arch_type != sparclet)
516
        as_fatal ("This target does not support -EL");
517
      break;
518
    case OPTION_LITTLE_ENDIAN_DATA:
519
      target_little_endian_data = 1;
520
      target_big_endian = 0;
521
      if (default_arch_type != sparc86x
522
          && default_arch_type != v9)
523
        as_fatal ("This target does not support --little-endian-data");
524
      break;
525
    case OPTION_BIG_ENDIAN:
526
      target_big_endian = 1;
527
      break;
528
#endif
529
 
530
#ifdef OBJ_AOUT
531
    case 'k':
532
      sparc_pic_code = 1;
533
      break;
534
#endif
535
 
536
#ifdef OBJ_ELF
537
    case OPTION_32:
538
    case OPTION_64:
539
      {
540
        const char **list, **l;
541
 
542
        sparc_arch_size = c == OPTION_32 ? 32 : 64;
543
        list = bfd_target_list ();
544
        for (l = list; *l != NULL; l++)
545
          {
546
            if (sparc_arch_size == 32)
547
              {
548
                if (CONST_STRNEQ (*l, "elf32-sparc"))
549
                  break;
550
              }
551
            else
552
              {
553
                if (CONST_STRNEQ (*l, "elf64-sparc"))
554
                  break;
555
              }
556
          }
557
        if (*l == NULL)
558
          as_fatal (_("No compiled in support for %d bit object file format"),
559
                    sparc_arch_size);
560
        free (list);
561
      }
562
      break;
563
 
564
    case OPTION_TSO:
565
      sparc_memory_model = MM_TSO;
566
      break;
567
 
568
    case OPTION_PSO:
569
      sparc_memory_model = MM_PSO;
570
      break;
571
 
572
    case OPTION_RMO:
573
      sparc_memory_model = MM_RMO;
574
      break;
575
 
576
    case 'V':
577
      print_version_id ();
578
      break;
579
 
580
    case 'Q':
581
      /* Qy - do emit .comment
582
         Qn - do not emit .comment.  */
583
      break;
584
 
585
    case 's':
586
      /* Use .stab instead of .stab.excl.  */
587
      break;
588
 
589
    case 'q':
590
      /* quick -- Native assembler does fewer checks.  */
591
      break;
592
 
593
    case 'K':
594
      if (strcmp (arg, "PIC") != 0)
595
        as_warn (_("Unrecognized option following -K"));
596
      else
597
        sparc_pic_code = 1;
598
      break;
599
 
600
    case OPTION_NO_UNDECLARED_REGS:
601
      no_undeclared_regs = 1;
602
      break;
603
 
604
    case OPTION_UNDECLARED_REGS:
605
      no_undeclared_regs = 0;
606
      break;
607
#endif
608
 
609
    case OPTION_RELAX:
610
      sparc_relax = 1;
611
      break;
612
 
613
    case OPTION_NO_RELAX:
614
      sparc_relax = 0;
615
      break;
616
 
617
    default:
618
      return 0;
619
    }
620
 
621
  return 1;
622
}
623
 
624
void
625
md_show_usage (stream)
626
     FILE *stream;
627
{
628
  const struct sparc_arch *arch;
629
  int column;
630
 
631
  /* We don't get a chance to initialize anything before we're called,
632
     so handle that now.  */
633
  if (! default_init_p)
634
    init_default_arch ();
635
 
636
  fprintf (stream, _("SPARC options:\n"));
637
  column = 0;
638
  for (arch = &sparc_arch_table[0]; arch->name; arch++)
639
    {
640
      if (!arch->user_option_p)
641
        continue;
642
      if (arch != &sparc_arch_table[0])
643
        fprintf (stream, " | ");
644
      if (column + strlen (arch->name) > 70)
645
        {
646
          column = 0;
647
          fputc ('\n', stream);
648
        }
649
      column += 5 + 2 + strlen (arch->name);
650
      fprintf (stream, "-A%s", arch->name);
651
    }
652
  for (arch = &sparc_arch_table[0]; arch->name; arch++)
653
    {
654
      if (!arch->user_option_p)
655
        continue;
656
      fprintf (stream, " | ");
657
      if (column + strlen (arch->name) > 65)
658
        {
659
          column = 0;
660
          fputc ('\n', stream);
661
        }
662
      column += 5 + 7 + strlen (arch->name);
663
      fprintf (stream, "-xarch=%s", arch->name);
664
    }
665
  fprintf (stream, _("\n\
666
                        specify variant of SPARC architecture\n\
667
-bump                   warn when assembler switches architectures\n\
668
-sparc                  ignored\n\
669
--enforce-aligned-data  force .long, etc., to be aligned correctly\n\
670
-relax                  relax jumps and branches (default)\n\
671
-no-relax               avoid changing any jumps and branches\n"));
672
#ifdef OBJ_AOUT
673
  fprintf (stream, _("\
674
-k                      generate PIC\n"));
675
#endif
676
#ifdef OBJ_ELF
677
  fprintf (stream, _("\
678
-32                     create 32 bit object file\n\
679
-64                     create 64 bit object file\n"));
680
  fprintf (stream, _("\
681
                        [default is %d]\n"), default_arch_size);
682
  fprintf (stream, _("\
683
-TSO                    use Total Store Ordering\n\
684
-PSO                    use Partial Store Ordering\n\
685
-RMO                    use Relaxed Memory Ordering\n"));
686
  fprintf (stream, _("\
687
                        [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
688
  fprintf (stream, _("\
689
-KPIC                   generate PIC\n\
690
-V                      print assembler version number\n\
691
-undeclared-regs        ignore application global register usage without\n\
692
                        appropriate .register directive (default)\n\
693
-no-undeclared-regs     force error on application global register usage\n\
694
                        without appropriate .register directive\n\
695
-q                      ignored\n\
696
-Qy, -Qn                ignored\n\
697
-s                      ignored\n"));
698
#endif
699
#ifdef SPARC_BIENDIAN
700
  fprintf (stream, _("\
701
-EL                     generate code for a little endian machine\n\
702
-EB                     generate code for a big endian machine\n\
703
--little-endian-data    generate code for a machine having big endian\n\
704
                        instructions and little endian data.\n"));
705
#endif
706
}
707
 
708
/* Native operand size opcode translation.  */
709
struct
710
  {
711
    char *name;
712
    char *name32;
713
    char *name64;
714
  } native_op_table[] =
715
{
716
  {"ldn", "ld", "ldx"},
717
  {"ldna", "lda", "ldxa"},
718
  {"stn", "st", "stx"},
719
  {"stna", "sta", "stxa"},
720
  {"slln", "sll", "sllx"},
721
  {"srln", "srl", "srlx"},
722
  {"sran", "sra", "srax"},
723
  {"casn", "cas", "casx"},
724
  {"casna", "casa", "casxa"},
725
  {"clrn", "clr", "clrx"},
726
  {NULL, NULL, NULL},
727
};
728
 
729
/* sparc64 privileged and hyperprivileged registers.  */
730
 
731
struct priv_reg_entry
732
{
733
  char *name;
734
  int regnum;
735
};
736
 
737
struct priv_reg_entry priv_reg_table[] =
738
{
739
  {"tpc", 0},
740
  {"tnpc", 1},
741
  {"tstate", 2},
742
  {"tt", 3},
743
  {"tick", 4},
744
  {"tba", 5},
745
  {"pstate", 6},
746
  {"tl", 7},
747
  {"pil", 8},
748
  {"cwp", 9},
749
  {"cansave", 10},
750
  {"canrestore", 11},
751
  {"cleanwin", 12},
752
  {"otherwin", 13},
753
  {"wstate", 14},
754
  {"fq", 15},
755
  {"gl", 16},
756
  {"ver", 31},
757
  {"", -1},                     /* End marker.  */
758
};
759
 
760
struct priv_reg_entry hpriv_reg_table[] =
761
{
762
  {"hpstate", 0},
763
  {"htstate", 1},
764
  {"hintp", 3},
765
  {"htba", 5},
766
  {"hver", 6},
767
  {"hstick_cmpr", 31},
768
  {"", -1},                     /* End marker.  */
769
};
770
 
771
/* v9a specific asrs.  This table is ordered by initial
772
   letter, in reverse.  */
773
 
774
struct priv_reg_entry v9a_asr_table[] =
775
{
776
  {"tick_cmpr", 23},
777
  {"sys_tick_cmpr", 25},
778
  {"sys_tick", 24},
779
  {"stick_cmpr", 25},
780
  {"stick", 24},
781
  {"softint_clear", 21},
782
  {"softint_set", 20},
783
  {"softint", 22},
784
  {"set_softint", 20},
785
  {"pic", 17},
786
  {"pcr", 16},
787
  {"gsr", 19},
788
  {"dcr", 18},
789
  {"clear_softint", 21},
790
  {"", -1},                     /* End marker.  */
791
};
792
 
793
static int
794
cmp_reg_entry (parg, qarg)
795
     const PTR parg;
796
     const PTR qarg;
797
{
798
  const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
799
  const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
800
 
801
  return strcmp (q->name, p->name);
802
}
803
 
804
/* This function is called once, at assembler startup time.  It should
805
   set up all the tables, etc. that the MD part of the assembler will
806
   need.  */
807
 
808
void
809
md_begin ()
810
{
811
  register const char *retval = NULL;
812
  int lose = 0;
813
  register unsigned int i = 0;
814
 
815
  /* We don't get a chance to initialize anything before md_parse_option
816
     is called, and it may not be called, so handle default initialization
817
     now if not already done.  */
818
  if (! default_init_p)
819
    init_default_arch ();
820
 
821
  sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
822
  op_hash = hash_new ();
823
 
824
  while (i < (unsigned int) sparc_num_opcodes)
825
    {
826
      const char *name = sparc_opcodes[i].name;
827
      retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
828
      if (retval != NULL)
829
        {
830
          as_bad (_("Internal error: can't hash `%s': %s\n"),
831
                  sparc_opcodes[i].name, retval);
832
          lose = 1;
833
        }
834
      do
835
        {
836
          if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
837
            {
838
              as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
839
                      sparc_opcodes[i].name, sparc_opcodes[i].args);
840
              lose = 1;
841
            }
842
          ++i;
843
        }
844
      while (i < (unsigned int) sparc_num_opcodes
845
             && !strcmp (sparc_opcodes[i].name, name));
846
    }
847
 
848
  for (i = 0; native_op_table[i].name; i++)
849
    {
850
      const struct sparc_opcode *insn;
851
      char *name = ((sparc_arch_size == 32)
852
                    ? native_op_table[i].name32
853
                    : native_op_table[i].name64);
854
      insn = (struct sparc_opcode *) hash_find (op_hash, name);
855
      if (insn == NULL)
856
        {
857
          as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
858
                  name, native_op_table[i].name);
859
          lose = 1;
860
        }
861
      else
862
        {
863
          retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
864
          if (retval != NULL)
865
            {
866
              as_bad (_("Internal error: can't hash `%s': %s\n"),
867
                      sparc_opcodes[i].name, retval);
868
              lose = 1;
869
            }
870
        }
871
    }
872
 
873
  if (lose)
874
    as_fatal (_("Broken assembler.  No assembly attempted."));
875
 
876
  qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
877
         sizeof (priv_reg_table[0]), cmp_reg_entry);
878
 
879
  /* If -bump, record the architecture level at which we start issuing
880
     warnings.  The behaviour is different depending upon whether an
881
     architecture was explicitly specified.  If it wasn't, we issue warnings
882
     for all upwards bumps.  If it was, we don't start issuing warnings until
883
     we need to bump beyond the requested architecture or when we bump between
884
     conflicting architectures.  */
885
 
886
  if (warn_on_bump
887
      && architecture_requested)
888
    {
889
      /* `max_architecture' records the requested architecture.
890
         Issue warnings if we go above it.  */
891
      warn_after_architecture = max_architecture;
892
 
893
      /* Find the highest architecture level that doesn't conflict with
894
         the requested one.  */
895
      for (max_architecture = SPARC_OPCODE_ARCH_MAX;
896
           max_architecture > warn_after_architecture;
897
           --max_architecture)
898
        if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
899
                                       warn_after_architecture))
900
          break;
901
    }
902
}
903
 
904
/* Called after all assembly has been done.  */
905
 
906
void
907
sparc_md_end ()
908
{
909
  unsigned long mach = bfd_mach_sparc;
910
 
911
  if (sparc_arch_size == 64)
912
    switch (current_architecture)
913
      {
914
      case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
915
      case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
916
      default: mach = bfd_mach_sparc_v9; break;
917
      }
918
  else
919
    switch (current_architecture)
920
      {
921
      case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
922
      case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
923
      case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
924
      case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
925
      /* The sparclite is treated like a normal sparc.  Perhaps it shouldn't
926
         be but for now it is (since that's the way it's always been
927
         treated).  */
928
      default: break;
929
      }
930
  bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
931
}
932
 
933
/* Return non-zero if VAL is in the range -(MAX+1) to MAX.  */
934
 
935
static INLINE int
936
in_signed_range (val, max)
937
     bfd_signed_vma val, max;
938
{
939
  if (max <= 0)
940
    abort ();
941
  /* Sign-extend the value from the architecture word size, so that
942
     0xffffffff is always considered -1 on sparc32.  */
943
  if (sparc_arch_size == 32)
944
    {
945
      bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
946
      val = ((val & U0xffffffff) ^ sign) - sign;
947
    }
948
  if (val > max)
949
    return 0;
950
  if (val < ~max)
951
    return 0;
952
  return 1;
953
}
954
 
955
/* Return non-zero if VAL is in the range 0 to MAX.  */
956
 
957
static INLINE int
958
in_unsigned_range (val, max)
959
     bfd_vma val, max;
960
{
961
  if (val > max)
962
    return 0;
963
  return 1;
964
}
965
 
966
/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
967
   (e.g. -15 to +31).  */
968
 
969
static INLINE int
970
in_bitfield_range (val, max)
971
     bfd_signed_vma val, max;
972
{
973
  if (max <= 0)
974
    abort ();
975
  if (val > max)
976
    return 0;
977
  if (val < ~(max >> 1))
978
    return 0;
979
  return 1;
980
}
981
 
982
static int
983
sparc_ffs (mask)
984
     unsigned int mask;
985
{
986
  int i;
987
 
988
  if (mask == 0)
989
    return -1;
990
 
991
  for (i = 0; (mask & 1) == 0; ++i)
992
    mask >>= 1;
993
  return i;
994
}
995
 
996
/* Implement big shift right.  */
997
static bfd_vma
998
BSR (val, amount)
999
     bfd_vma val;
1000
     int amount;
1001
{
1002
  if (sizeof (bfd_vma) <= 4 && amount >= 32)
1003
    as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1004
  return val >> amount;
1005
}
1006
 
1007
/* For communication between sparc_ip and get_expression.  */
1008
static char *expr_end;
1009
 
1010
/* Values for `special_case'.
1011
   Instructions that require wierd handling because they're longer than
1012
   4 bytes.  */
1013
#define SPECIAL_CASE_NONE       0
1014
#define SPECIAL_CASE_SET        1
1015
#define SPECIAL_CASE_SETSW      2
1016
#define SPECIAL_CASE_SETX       3
1017
/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this.  */
1018
#define SPECIAL_CASE_FDIV       4
1019
 
1020
/* Bit masks of various insns.  */
1021
#define NOP_INSN 0x01000000
1022
#define OR_INSN 0x80100000
1023
#define XOR_INSN 0x80180000
1024
#define FMOVS_INSN 0x81A00020
1025
#define SETHI_INSN 0x01000000
1026
#define SLLX_INSN 0x81281000
1027
#define SRA_INSN 0x81380000
1028
 
1029
/* The last instruction to be assembled.  */
1030
static const struct sparc_opcode *last_insn;
1031
/* The assembled opcode of `last_insn'.  */
1032
static unsigned long last_opcode;
1033
 
1034
/* Handle the set and setuw synthetic instructions.  */
1035
 
1036
static void
1037
synthetize_setuw (insn)
1038
     const struct sparc_opcode *insn;
1039
{
1040
  int need_hi22_p = 0;
1041
  int rd = (the_insn.opcode & RD (~0)) >> 25;
1042
 
1043
  if (the_insn.exp.X_op == O_constant)
1044
    {
1045
      if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1046
        {
1047
          if (sizeof (offsetT) > 4
1048
              && (the_insn.exp.X_add_number < 0
1049
                  || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1050
            as_warn (_("set: number not in 0..4294967295 range"));
1051
        }
1052
      else
1053
        {
1054
          if (sizeof (offsetT) > 4
1055
              && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1056
                  || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1057
            as_warn (_("set: number not in -2147483648..4294967295 range"));
1058
          the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1059
        }
1060
    }
1061
 
1062
  /* See if operand is absolute and small; skip sethi if so.  */
1063
  if (the_insn.exp.X_op != O_constant
1064
      || the_insn.exp.X_add_number >= (1 << 12)
1065
      || the_insn.exp.X_add_number < -(1 << 12))
1066
    {
1067
      the_insn.opcode = (SETHI_INSN | RD (rd)
1068
                         | ((the_insn.exp.X_add_number >> 10)
1069
                            & (the_insn.exp.X_op == O_constant
1070
                               ? 0x3fffff : 0)));
1071
      the_insn.reloc = (the_insn.exp.X_op != O_constant
1072
                        ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1073
      output_insn (insn, &the_insn);
1074
      need_hi22_p = 1;
1075
    }
1076
 
1077
  /* See if operand has no low-order bits; skip OR if so.  */
1078
  if (the_insn.exp.X_op != O_constant
1079
      || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1080
      || ! need_hi22_p)
1081
    {
1082
      the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1083
                         | RD (rd) | IMMED
1084
                         | (the_insn.exp.X_add_number
1085
                            & (the_insn.exp.X_op != O_constant
1086
                               ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1087
      the_insn.reloc = (the_insn.exp.X_op != O_constant
1088
                        ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1089
      output_insn (insn, &the_insn);
1090
    }
1091
}
1092
 
1093
/* Handle the setsw synthetic instruction.  */
1094
 
1095
static void
1096
synthetize_setsw (insn)
1097
     const struct sparc_opcode *insn;
1098
{
1099
  int low32, rd, opc;
1100
 
1101
  rd = (the_insn.opcode & RD (~0)) >> 25;
1102
 
1103
  if (the_insn.exp.X_op != O_constant)
1104
    {
1105
      synthetize_setuw (insn);
1106
 
1107
      /* Need to sign extend it.  */
1108
      the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1109
      the_insn.reloc = BFD_RELOC_NONE;
1110
      output_insn (insn, &the_insn);
1111
      return;
1112
    }
1113
 
1114
  if (sizeof (offsetT) > 4
1115
      && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1116
          || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1117
    as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1118
 
1119
  low32 = the_insn.exp.X_add_number;
1120
 
1121
  if (low32 >= 0)
1122
    {
1123
      synthetize_setuw (insn);
1124
      return;
1125
    }
1126
 
1127
  opc = OR_INSN;
1128
 
1129
  the_insn.reloc = BFD_RELOC_NONE;
1130
  /* See if operand is absolute and small; skip sethi if so.  */
1131
  if (low32 < -(1 << 12))
1132
    {
1133
      the_insn.opcode = (SETHI_INSN | RD (rd)
1134
                         | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1135
      output_insn (insn, &the_insn);
1136
      low32 = 0x1c00 | (low32 & 0x3ff);
1137
      opc = RS1 (rd) | XOR_INSN;
1138
    }
1139
 
1140
  the_insn.opcode = (opc | RD (rd) | IMMED
1141
                     | (low32 & 0x1fff));
1142
  output_insn (insn, &the_insn);
1143
}
1144
 
1145
/* Handle the setsw synthetic instruction.  */
1146
 
1147
static void
1148
synthetize_setx (insn)
1149
     const struct sparc_opcode *insn;
1150
{
1151
  int upper32, lower32;
1152
  int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1153
  int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1154
  int upper_dstreg;
1155
  int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1156
  int need_xor10_p = 0;
1157
 
1158
#define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1159
  lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1160
  upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1161
#undef SIGNEXT32
1162
 
1163
  upper_dstreg = tmpreg;
1164
  /* The tmp reg should not be the dst reg.  */
1165
  if (tmpreg == dstreg)
1166
    as_warn (_("setx: temporary register same as destination register"));
1167
 
1168
  /* ??? Obviously there are other optimizations we can do
1169
     (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1170
     doing some of these.  Later.  If you do change things, try to
1171
     change all of this to be table driven as well.  */
1172
  /* What to output depends on the number if it's constant.
1173
     Compute that first, then output what we've decided upon.  */
1174
  if (the_insn.exp.X_op != O_constant)
1175
    {
1176
      if (sparc_arch_size == 32)
1177
        {
1178
          /* When arch size is 32, we want setx to be equivalent
1179
             to setuw for anything but constants.  */
1180
          the_insn.exp.X_add_number &= 0xffffffff;
1181
          synthetize_setuw (insn);
1182
          return;
1183
        }
1184
      need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1185
      lower32 = 0;
1186
      upper32 = 0;
1187
    }
1188
  else
1189
    {
1190
      /* Reset X_add_number, we've extracted it as upper32/lower32.
1191
         Otherwise fixup_segment will complain about not being able to
1192
         write an 8 byte number in a 4 byte field.  */
1193
      the_insn.exp.X_add_number = 0;
1194
 
1195
      /* Only need hh22 if `or' insn can't handle constant.  */
1196
      if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1197
        need_hh22_p = 1;
1198
 
1199
      /* Does bottom part (after sethi) have bits?  */
1200
      if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1201
          /* No hh22, but does upper32 still have bits we can't set
1202
             from lower32?  */
1203
          || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1204
        need_hm10_p = 1;
1205
 
1206
      /* If the lower half is all zero, we build the upper half directly
1207
         into the dst reg.  */
1208
      if (lower32 != 0
1209
          /* Need lower half if number is zero or 0xffffffff00000000.  */
1210
          || (! need_hh22_p && ! need_hm10_p))
1211
        {
1212
          /* No need for sethi if `or' insn can handle constant.  */
1213
          if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1214
              /* Note that we can't use a negative constant in the `or'
1215
                 insn unless the upper 32 bits are all ones.  */
1216
              || (lower32 < 0 && upper32 != -1)
1217
              || (lower32 >= 0 && upper32 == -1))
1218
            need_hi22_p = 1;
1219
 
1220
          if (need_hi22_p && upper32 == -1)
1221
            need_xor10_p = 1;
1222
 
1223
          /* Does bottom part (after sethi) have bits?  */
1224
          else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1225
                   /* No sethi.  */
1226
                   || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1227
                   /* Need `or' if we didn't set anything else.  */
1228
                   || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1229
            need_lo10_p = 1;
1230
        }
1231
      else
1232
        /* Output directly to dst reg if lower 32 bits are all zero.  */
1233
        upper_dstreg = dstreg;
1234
    }
1235
 
1236
  if (!upper_dstreg && dstreg)
1237
    as_warn (_("setx: illegal temporary register g0"));
1238
 
1239
  if (need_hh22_p)
1240
    {
1241
      the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1242
                         | ((upper32 >> 10) & 0x3fffff));
1243
      the_insn.reloc = (the_insn.exp.X_op != O_constant
1244
                        ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1245
      output_insn (insn, &the_insn);
1246
    }
1247
 
1248
  if (need_hi22_p)
1249
    {
1250
      the_insn.opcode = (SETHI_INSN | RD (dstreg)
1251
                         | (((need_xor10_p ? ~lower32 : lower32)
1252
                             >> 10) & 0x3fffff));
1253
      the_insn.reloc = (the_insn.exp.X_op != O_constant
1254
                        ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1255
      output_insn (insn, &the_insn);
1256
    }
1257
 
1258
  if (need_hm10_p)
1259
    {
1260
      the_insn.opcode = (OR_INSN
1261
                         | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1262
                         | RD (upper_dstreg)
1263
                         | IMMED
1264
                         | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1265
      the_insn.reloc = (the_insn.exp.X_op != O_constant
1266
                        ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1267
      output_insn (insn, &the_insn);
1268
    }
1269
 
1270
  if (need_lo10_p)
1271
    {
1272
      /* FIXME: One nice optimization to do here is to OR the low part
1273
         with the highpart if hi22 isn't needed and the low part is
1274
         positive.  */
1275
      the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1276
                         | RD (dstreg)
1277
                         | IMMED
1278
                         | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1279
      the_insn.reloc = (the_insn.exp.X_op != O_constant
1280
                        ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1281
      output_insn (insn, &the_insn);
1282
    }
1283
 
1284
  /* If we needed to build the upper part, shift it into place.  */
1285
  if (need_hh22_p || need_hm10_p)
1286
    {
1287
      the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1288
                         | IMMED | 32);
1289
      the_insn.reloc = BFD_RELOC_NONE;
1290
      output_insn (insn, &the_insn);
1291
    }
1292
 
1293
  /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r.  */
1294
  if (need_xor10_p)
1295
    {
1296
      the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1297
                         | 0x1c00 | (lower32 & 0x3ff));
1298
      the_insn.reloc = BFD_RELOC_NONE;
1299
      output_insn (insn, &the_insn);
1300
    }
1301
 
1302
  /* If we needed to build both upper and lower parts, OR them together.  */
1303
  else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1304
    {
1305
      the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1306
                         | RD (dstreg));
1307
      the_insn.reloc = BFD_RELOC_NONE;
1308
      output_insn (insn, &the_insn);
1309
    }
1310
}
1311
 
1312
/* Main entry point to assemble one instruction.  */
1313
 
1314
void
1315
md_assemble (str)
1316
     char *str;
1317
{
1318
  const struct sparc_opcode *insn;
1319
  int special_case;
1320
 
1321
  know (str);
1322
  special_case = sparc_ip (str, &insn);
1323
  if (insn == NULL)
1324
    return;
1325
 
1326
  /* We warn about attempts to put a floating point branch in a delay slot,
1327
     unless the delay slot has been annulled.  */
1328
  if (last_insn != NULL
1329
      && (insn->flags & F_FBR) != 0
1330
      && (last_insn->flags & F_DELAYED) != 0
1331
      /* ??? This test isn't completely accurate.  We assume anything with
1332
         F_{UNBR,CONDBR,FBR} set is annullable.  */
1333
      && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1334
          || (last_opcode & ANNUL) == 0))
1335
    as_warn (_("FP branch in delay slot"));
1336
 
1337
  /* SPARC before v9 requires a nop instruction between a floating
1338
     point instruction and a floating point branch.  We insert one
1339
     automatically, with a warning.  */
1340
  if (max_architecture < SPARC_OPCODE_ARCH_V9
1341
      && last_insn != NULL
1342
      && (insn->flags & F_FBR) != 0
1343
      && (last_insn->flags & F_FLOAT) != 0)
1344
    {
1345
      struct sparc_it nop_insn;
1346
 
1347
      nop_insn.opcode = NOP_INSN;
1348
      nop_insn.reloc = BFD_RELOC_NONE;
1349
      output_insn (insn, &nop_insn);
1350
      as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1351
    }
1352
 
1353
  switch (special_case)
1354
    {
1355
    case SPECIAL_CASE_NONE:
1356
      /* Normal insn.  */
1357
      output_insn (insn, &the_insn);
1358
      break;
1359
 
1360
    case SPECIAL_CASE_SETSW:
1361
      synthetize_setsw (insn);
1362
      break;
1363
 
1364
    case SPECIAL_CASE_SET:
1365
      synthetize_setuw (insn);
1366
      break;
1367
 
1368
    case SPECIAL_CASE_SETX:
1369
      synthetize_setx (insn);
1370
      break;
1371
 
1372
    case SPECIAL_CASE_FDIV:
1373
      {
1374
        int rd = (the_insn.opcode >> 25) & 0x1f;
1375
 
1376
        output_insn (insn, &the_insn);
1377
 
1378
        /* According to information leaked from Sun, the "fdiv" instructions
1379
           on early SPARC machines would produce incorrect results sometimes.
1380
           The workaround is to add an fmovs of the destination register to
1381
           itself just after the instruction.  This was true on machines
1382
           with Weitek 1165 float chips, such as the Sun-4/260 and /280.  */
1383
        assert (the_insn.reloc == BFD_RELOC_NONE);
1384
        the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1385
        output_insn (insn, &the_insn);
1386
        return;
1387
      }
1388
 
1389
    default:
1390
      as_fatal (_("failed special case insn sanity check"));
1391
    }
1392
}
1393
 
1394
/* Subroutine of md_assemble to do the actual parsing.  */
1395
 
1396
static int
1397
sparc_ip (str, pinsn)
1398
     char *str;
1399
     const struct sparc_opcode **pinsn;
1400
{
1401
  char *error_message = "";
1402
  char *s;
1403
  const char *args;
1404
  char c;
1405
  const struct sparc_opcode *insn;
1406
  char *argsStart;
1407
  unsigned long opcode;
1408
  unsigned int mask = 0;
1409
  int match = 0;
1410
  int comma = 0;
1411
  int v9_arg_p;
1412
  int special_case = SPECIAL_CASE_NONE;
1413
 
1414
  s = str;
1415
  if (ISLOWER (*s))
1416
    {
1417
      do
1418
        ++s;
1419
      while (ISLOWER (*s) || ISDIGIT (*s));
1420
    }
1421
 
1422
  switch (*s)
1423
    {
1424
    case '\0':
1425
      break;
1426
 
1427
    case ',':
1428
      comma = 1;
1429
      /* Fall through.  */
1430
 
1431
    case ' ':
1432
      *s++ = '\0';
1433
      break;
1434
 
1435
    default:
1436
      as_bad (_("Unknown opcode: `%s'"), str);
1437
      *pinsn = NULL;
1438
      return special_case;
1439
    }
1440
  insn = (struct sparc_opcode *) hash_find (op_hash, str);
1441
  *pinsn = insn;
1442
  if (insn == NULL)
1443
    {
1444
      as_bad (_("Unknown opcode: `%s'"), str);
1445
      return special_case;
1446
    }
1447
  if (comma)
1448
    {
1449
      *--s = ',';
1450
    }
1451
 
1452
  argsStart = s;
1453
  for (;;)
1454
    {
1455
      opcode = insn->match;
1456
      memset (&the_insn, '\0', sizeof (the_insn));
1457
      the_insn.reloc = BFD_RELOC_NONE;
1458
      v9_arg_p = 0;
1459
 
1460
      /* Build the opcode, checking as we go to make sure that the
1461
         operands match.  */
1462
      for (args = insn->args;; ++args)
1463
        {
1464
          switch (*args)
1465
            {
1466
            case 'K':
1467
              {
1468
                int kmask = 0;
1469
 
1470
                /* Parse a series of masks.  */
1471
                if (*s == '#')
1472
                  {
1473
                    while (*s == '#')
1474
                      {
1475
                        int mask;
1476
 
1477
                        if (! parse_keyword_arg (sparc_encode_membar, &s,
1478
                                                 &mask))
1479
                          {
1480
                            error_message = _(": invalid membar mask name");
1481
                            goto error;
1482
                          }
1483
                        kmask |= mask;
1484
                        while (*s == ' ')
1485
                          ++s;
1486
                        if (*s == '|' || *s == '+')
1487
                          ++s;
1488
                        while (*s == ' ')
1489
                          ++s;
1490
                      }
1491
                  }
1492
                else
1493
                  {
1494
                    if (! parse_const_expr_arg (&s, &kmask))
1495
                      {
1496
                        error_message = _(": invalid membar mask expression");
1497
                        goto error;
1498
                      }
1499
                    if (kmask < 0 || kmask > 127)
1500
                      {
1501
                        error_message = _(": invalid membar mask number");
1502
                        goto error;
1503
                      }
1504
                  }
1505
 
1506
                opcode |= MEMBAR (kmask);
1507
                continue;
1508
              }
1509
 
1510
            case '3':
1511
              {
1512
                int smask = 0;
1513
 
1514
                if (! parse_const_expr_arg (&s, &smask))
1515
                  {
1516
                    error_message = _(": invalid siam mode expression");
1517
                    goto error;
1518
                  }
1519
                if (smask < 0 || smask > 7)
1520
                  {
1521
                    error_message = _(": invalid siam mode number");
1522
                    goto error;
1523
                  }
1524
                opcode |= smask;
1525
                continue;
1526
              }
1527
 
1528
            case '*':
1529
              {
1530
                int fcn = 0;
1531
 
1532
                /* Parse a prefetch function.  */
1533
                if (*s == '#')
1534
                  {
1535
                    if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1536
                      {
1537
                        error_message = _(": invalid prefetch function name");
1538
                        goto error;
1539
                      }
1540
                  }
1541
                else
1542
                  {
1543
                    if (! parse_const_expr_arg (&s, &fcn))
1544
                      {
1545
                        error_message = _(": invalid prefetch function expression");
1546
                        goto error;
1547
                      }
1548
                    if (fcn < 0 || fcn > 31)
1549
                      {
1550
                        error_message = _(": invalid prefetch function number");
1551
                        goto error;
1552
                      }
1553
                  }
1554
                opcode |= RD (fcn);
1555
                continue;
1556
              }
1557
 
1558
            case '!':
1559
            case '?':
1560
              /* Parse a sparc64 privileged register.  */
1561
              if (*s == '%')
1562
                {
1563
                  struct priv_reg_entry *p = priv_reg_table;
1564
                  unsigned int len = 9999999; /* Init to make gcc happy.  */
1565
 
1566
                  s += 1;
1567
                  while (p->name[0] > s[0])
1568
                    p++;
1569
                  while (p->name[0] == s[0])
1570
                    {
1571
                      len = strlen (p->name);
1572
                      if (strncmp (p->name, s, len) == 0)
1573
                        break;
1574
                      p++;
1575
                    }
1576
                  if (p->name[0] != s[0])
1577
                    {
1578
                      error_message = _(": unrecognizable privileged register");
1579
                      goto error;
1580
                    }
1581
                  if (*args == '?')
1582
                    opcode |= (p->regnum << 14);
1583
                  else
1584
                    opcode |= (p->regnum << 25);
1585
                  s += len;
1586
                  continue;
1587
                }
1588
              else
1589
                {
1590
                  error_message = _(": unrecognizable privileged register");
1591
                  goto error;
1592
                }
1593
 
1594
            case '$':
1595
            case '%':
1596
              /* Parse a sparc64 hyperprivileged register.  */
1597
              if (*s == '%')
1598
                {
1599
                  struct priv_reg_entry *p = hpriv_reg_table;
1600
                  unsigned int len = 9999999; /* Init to make gcc happy.  */
1601
 
1602
                  s += 1;
1603
                  while (p->name[0] > s[0])
1604
                    p++;
1605
                  while (p->name[0] == s[0])
1606
                    {
1607
                      len = strlen (p->name);
1608
                      if (strncmp (p->name, s, len) == 0)
1609
                        break;
1610
                      p++;
1611
                    }
1612
                  if (p->name[0] != s[0])
1613
                    {
1614
                      error_message = _(": unrecognizable hyperprivileged register");
1615
                      goto error;
1616
                    }
1617
                  if (*args == '$')
1618
                    opcode |= (p->regnum << 14);
1619
                  else
1620
                    opcode |= (p->regnum << 25);
1621
                  s += len;
1622
                  continue;
1623
                }
1624
              else
1625
                {
1626
                  error_message = _(": unrecognizable hyperprivileged register");
1627
                  goto error;
1628
                }
1629
 
1630
            case '_':
1631
            case '/':
1632
              /* Parse a v9a/v9b ancillary state register.  */
1633
              if (*s == '%')
1634
                {
1635
                  struct priv_reg_entry *p = v9a_asr_table;
1636
                  unsigned int len = 9999999; /* Init to make gcc happy.  */
1637
 
1638
                  s += 1;
1639
                  while (p->name[0] > s[0])
1640
                    p++;
1641
                  while (p->name[0] == s[0])
1642
                    {
1643
                      len = strlen (p->name);
1644
                      if (strncmp (p->name, s, len) == 0)
1645
                        break;
1646
                      p++;
1647
                    }
1648
                  if (p->name[0] != s[0])
1649
                    {
1650
                      error_message = _(": unrecognizable v9a or v9b ancillary state register");
1651
                      goto error;
1652
                    }
1653
                  if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1654
                    {
1655
                      error_message = _(": rd on write only ancillary state register");
1656
                      goto error;
1657
                    }
1658
                  if (p->regnum >= 24
1659
                      && (insn->architecture
1660
                          & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1661
                    {
1662
                      /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1663
                      error_message = _(": unrecognizable v9a ancillary state register");
1664
                      goto error;
1665
                    }
1666
                  if (*args == '/')
1667
                    opcode |= (p->regnum << 14);
1668
                  else
1669
                    opcode |= (p->regnum << 25);
1670
                  s += len;
1671
                  continue;
1672
                }
1673
              else
1674
                {
1675
                  error_message = _(": unrecognizable v9a or v9b ancillary state register");
1676
                  goto error;
1677
                }
1678
 
1679
            case 'M':
1680
            case 'm':
1681
              if (strncmp (s, "%asr", 4) == 0)
1682
                {
1683
                  s += 4;
1684
 
1685
                  if (ISDIGIT (*s))
1686
                    {
1687
                      long num = 0;
1688
 
1689
                      while (ISDIGIT (*s))
1690
                        {
1691
                          num = num * 10 + *s - '0';
1692
                          ++s;
1693
                        }
1694
 
1695
                      if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1696
                        {
1697
                          if (num < 16 || 31 < num)
1698
                            {
1699
                              error_message = _(": asr number must be between 16 and 31");
1700
                              goto error;
1701
                            }
1702
                        }
1703
                      else
1704
                        {
1705
                          if (num < 0 || 31 < num)
1706
                            {
1707
                              error_message = _(": asr number must be between 0 and 31");
1708
                              goto error;
1709
                            }
1710
                        }
1711
 
1712
                      opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1713
                      continue;
1714
                    }
1715
                  else
1716
                    {
1717
                      error_message = _(": expecting %asrN");
1718
                      goto error;
1719
                    }
1720
                } /* if %asr  */
1721
              break;
1722
 
1723
            case 'I':
1724
              the_insn.reloc = BFD_RELOC_SPARC_11;
1725
              goto immediate;
1726
 
1727
            case 'j':
1728
              the_insn.reloc = BFD_RELOC_SPARC_10;
1729
              goto immediate;
1730
 
1731
            case 'X':
1732
              /* V8 systems don't understand BFD_RELOC_SPARC_5.  */
1733
              if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1734
                the_insn.reloc = BFD_RELOC_SPARC_5;
1735
              else
1736
                the_insn.reloc = BFD_RELOC_SPARC13;
1737
              /* These fields are unsigned, but for upward compatibility,
1738
                 allow negative values as well.  */
1739
              goto immediate;
1740
 
1741
            case 'Y':
1742
              /* V8 systems don't understand BFD_RELOC_SPARC_6.  */
1743
              if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1744
                the_insn.reloc = BFD_RELOC_SPARC_6;
1745
              else
1746
                the_insn.reloc = BFD_RELOC_SPARC13;
1747
              /* These fields are unsigned, but for upward compatibility,
1748
                 allow negative values as well.  */
1749
              goto immediate;
1750
 
1751
            case 'k':
1752
              the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1753
              the_insn.pcrel = 1;
1754
              goto immediate;
1755
 
1756
            case 'G':
1757
              the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1758
              the_insn.pcrel = 1;
1759
              goto immediate;
1760
 
1761
            case 'N':
1762
              if (*s == 'p' && s[1] == 'n')
1763
                {
1764
                  s += 2;
1765
                  continue;
1766
                }
1767
              break;
1768
 
1769
            case 'T':
1770
              if (*s == 'p' && s[1] == 't')
1771
                {
1772
                  s += 2;
1773
                  continue;
1774
                }
1775
              break;
1776
 
1777
            case 'z':
1778
              if (*s == ' ')
1779
                {
1780
                  ++s;
1781
                }
1782
              if (strncmp (s, "%icc", 4) == 0)
1783
                {
1784
                  s += 4;
1785
                  continue;
1786
                }
1787
              break;
1788
 
1789
            case 'Z':
1790
              if (*s == ' ')
1791
                {
1792
                  ++s;
1793
                }
1794
              if (strncmp (s, "%xcc", 4) == 0)
1795
                {
1796
                  s += 4;
1797
                  continue;
1798
                }
1799
              break;
1800
 
1801
            case '6':
1802
              if (*s == ' ')
1803
                {
1804
                  ++s;
1805
                }
1806
              if (strncmp (s, "%fcc0", 5) == 0)
1807
                {
1808
                  s += 5;
1809
                  continue;
1810
                }
1811
              break;
1812
 
1813
            case '7':
1814
              if (*s == ' ')
1815
                {
1816
                  ++s;
1817
                }
1818
              if (strncmp (s, "%fcc1", 5) == 0)
1819
                {
1820
                  s += 5;
1821
                  continue;
1822
                }
1823
              break;
1824
 
1825
            case '8':
1826
              if (*s == ' ')
1827
                {
1828
                  ++s;
1829
                }
1830
              if (strncmp (s, "%fcc2", 5) == 0)
1831
                {
1832
                  s += 5;
1833
                  continue;
1834
                }
1835
              break;
1836
 
1837
            case '9':
1838
              if (*s == ' ')
1839
                {
1840
                  ++s;
1841
                }
1842
              if (strncmp (s, "%fcc3", 5) == 0)
1843
                {
1844
                  s += 5;
1845
                  continue;
1846
                }
1847
              break;
1848
 
1849
            case 'P':
1850
              if (strncmp (s, "%pc", 3) == 0)
1851
                {
1852
                  s += 3;
1853
                  continue;
1854
                }
1855
              break;
1856
 
1857
            case 'W':
1858
              if (strncmp (s, "%tick", 5) == 0)
1859
                {
1860
                  s += 5;
1861
                  continue;
1862
                }
1863
              break;
1864
 
1865
            case '\0':          /* End of args.  */
1866
              if (s[0] == ',' && s[1] == '%')
1867
                {
1868
                  static const struct ops
1869
                  {
1870
                    /* The name as it appears in assembler.  */
1871
                    char *name;
1872
                    /* strlen (name), precomputed for speed */
1873
                    int len;
1874
                    /* The reloc this pseudo-op translates to.  */
1875
                    int reloc;
1876
                    /* 1 if tls call.  */
1877
                    int tls_call;
1878
                  }
1879
                  ops[] =
1880
                  {
1881
                    { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
1882
                    { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
1883
                    { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
1884
                    { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
1885
                    { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
1886
                    { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
1887
                    { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
1888
                    { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
1889
                    { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
1890
                    { NULL, 0, 0, 0 }
1891
                  };
1892
                  const struct ops *o;
1893
                  char *s1;
1894
                  int npar = 0;
1895
 
1896
                  for (o = ops; o->name; o++)
1897
                    if (strncmp (s + 2, o->name, o->len) == 0)
1898
                      break;
1899
                  if (o->name == NULL)
1900
                    break;
1901
 
1902
                  if (s[o->len + 2] != '(')
1903
                    {
1904
                      as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1905
                      return special_case;
1906
                    }
1907
 
1908
                  if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
1909
                    {
1910
                      as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1911
                              o->name);
1912
                      return special_case;
1913
                    }
1914
 
1915
                  if (o->tls_call
1916
                      && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
1917
                          || the_insn.exp.X_add_number != 0
1918
                          || the_insn.exp.X_add_symbol
1919
                             != symbol_find_or_make ("__tls_get_addr")))
1920
                    {
1921
                      as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1922
                              o->name);
1923
                      return special_case;
1924
                    }
1925
 
1926
                  the_insn.reloc = o->reloc;
1927
                  memset (&the_insn.exp, 0, sizeof (the_insn.exp));
1928
                  s += o->len + 3;
1929
 
1930
                  for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
1931
                    if (*s1 == '(')
1932
                      npar++;
1933
                    else if (*s1 == ')')
1934
                      {
1935
                        if (!npar)
1936
                          break;
1937
                        npar--;
1938
                      }
1939
 
1940
                  if (*s1 != ')')
1941
                    {
1942
                      as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1943
                      return special_case;
1944
                    }
1945
 
1946
                  *s1 = '\0';
1947
                  (void) get_expression (s);
1948
                  *s1 = ')';
1949
                  s = s1 + 1;
1950
                }
1951
              if (*s == '\0')
1952
                match = 1;
1953
              break;
1954
 
1955
            case '+':
1956
              if (*s == '+')
1957
                {
1958
                  ++s;
1959
                  continue;
1960
                }
1961
              if (*s == '-')
1962
                {
1963
                  continue;
1964
                }
1965
              break;
1966
 
1967
            case '[':           /* These must match exactly.  */
1968
            case ']':
1969
            case ',':
1970
            case ' ':
1971
              if (*s++ == *args)
1972
                continue;
1973
              break;
1974
 
1975
            case '#':           /* Must be at least one digit.  */
1976
              if (ISDIGIT (*s++))
1977
                {
1978
                  while (ISDIGIT (*s))
1979
                    {
1980
                      ++s;
1981
                    }
1982
                  continue;
1983
                }
1984
              break;
1985
 
1986
            case 'C':           /* Coprocessor state register.  */
1987
              if (strncmp (s, "%csr", 4) == 0)
1988
                {
1989
                  s += 4;
1990
                  continue;
1991
                }
1992
              break;
1993
 
1994
            case 'b':           /* Next operand is a coprocessor register.  */
1995
            case 'c':
1996
            case 'D':
1997
              if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
1998
                {
1999
                  mask = *s++;
2000
                  if (ISDIGIT (*s))
2001
                    {
2002
                      mask = 10 * (mask - '0') + (*s++ - '0');
2003
                      if (mask >= 32)
2004
                        {
2005
                          break;
2006
                        }
2007
                    }
2008
                  else
2009
                    {
2010
                      mask -= '0';
2011
                    }
2012
                  switch (*args)
2013
                    {
2014
 
2015
                    case 'b':
2016
                      opcode |= mask << 14;
2017
                      continue;
2018
 
2019
                    case 'c':
2020
                      opcode |= mask;
2021
                      continue;
2022
 
2023
                    case 'D':
2024
                      opcode |= mask << 25;
2025
                      continue;
2026
                    }
2027
                }
2028
              break;
2029
 
2030
            case 'r':           /* next operand must be a register */
2031
            case 'O':
2032
            case '1':
2033
            case '2':
2034
            case 'd':
2035
              if (*s++ == '%')
2036
                {
2037
                  switch (c = *s++)
2038
                    {
2039
 
2040
                    case 'f':   /* frame pointer */
2041
                      if (*s++ == 'p')
2042
                        {
2043
                          mask = 0x1e;
2044
                          break;
2045
                        }
2046
                      goto error;
2047
 
2048
                    case 'g':   /* global register */
2049
                      c = *s++;
2050
                      if (isoctal (c))
2051
                        {
2052
                          mask = c - '0';
2053
                          break;
2054
                        }
2055
                      goto error;
2056
 
2057
                    case 'i':   /* in register */
2058
                      c = *s++;
2059
                      if (isoctal (c))
2060
                        {
2061
                          mask = c - '0' + 24;
2062
                          break;
2063
                        }
2064
                      goto error;
2065
 
2066
                    case 'l':   /* local register */
2067
                      c = *s++;
2068
                      if (isoctal (c))
2069
                        {
2070
                          mask = (c - '0' + 16);
2071
                          break;
2072
                        }
2073
                      goto error;
2074
 
2075
                    case 'o':   /* out register */
2076
                      c = *s++;
2077
                      if (isoctal (c))
2078
                        {
2079
                          mask = (c - '0' + 8);
2080
                          break;
2081
                        }
2082
                      goto error;
2083
 
2084
                    case 's':   /* stack pointer */
2085
                      if (*s++ == 'p')
2086
                        {
2087
                          mask = 0xe;
2088
                          break;
2089
                        }
2090
                      goto error;
2091
 
2092
                    case 'r':   /* any register */
2093
                      if (!ISDIGIT ((c = *s++)))
2094
                        {
2095
                          goto error;
2096
                        }
2097
                      /* FALLTHROUGH */
2098
                    case '0':
2099
                    case '1':
2100
                    case '2':
2101
                    case '3':
2102
                    case '4':
2103
                    case '5':
2104
                    case '6':
2105
                    case '7':
2106
                    case '8':
2107
                    case '9':
2108
                      if (ISDIGIT (*s))
2109
                        {
2110
                          if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2111
                            {
2112
                              goto error;
2113
                            }
2114
                        }
2115
                      else
2116
                        {
2117
                          c -= '0';
2118
                        }
2119
                      mask = c;
2120
                      break;
2121
 
2122
                    default:
2123
                      goto error;
2124
                    }
2125
 
2126
                  if ((mask & ~1) == 2 && sparc_arch_size == 64
2127
                      && no_undeclared_regs && ! globals[mask])
2128
                    as_bad (_("detected global register use not covered by .register pseudo-op"));
2129
 
2130
                  /* Got the register, now figure out where
2131
                     it goes in the opcode.  */
2132
                  switch (*args)
2133
                    {
2134
                    case '1':
2135
                      opcode |= mask << 14;
2136
                      continue;
2137
 
2138
                    case '2':
2139
                      opcode |= mask;
2140
                      continue;
2141
 
2142
                    case 'd':
2143
                      opcode |= mask << 25;
2144
                      continue;
2145
 
2146
                    case 'r':
2147
                      opcode |= (mask << 25) | (mask << 14);
2148
                      continue;
2149
 
2150
                    case 'O':
2151
                      opcode |= (mask << 25) | (mask << 0);
2152
                      continue;
2153
                    }
2154
                }
2155
              break;
2156
 
2157
            case 'e':           /* next operand is a floating point register */
2158
            case 'v':
2159
            case 'V':
2160
 
2161
            case 'f':
2162
            case 'B':
2163
            case 'R':
2164
 
2165
            case 'g':
2166
            case 'H':
2167
            case 'J':
2168
              {
2169
                char format;
2170
 
2171
                if (*s++ == '%'
2172
                    && ((format = *s) == 'f')
2173
                    && ISDIGIT (*++s))
2174
                  {
2175
                    for (mask = 0; ISDIGIT (*s); ++s)
2176
                      {
2177
                        mask = 10 * mask + (*s - '0');
2178
                      }         /* read the number */
2179
 
2180
                    if ((*args == 'v'
2181
                         || *args == 'B'
2182
                         || *args == 'H')
2183
                        && (mask & 1))
2184
                      {
2185
                        break;
2186
                      }         /* register must be even numbered */
2187
 
2188
                    if ((*args == 'V'
2189
                         || *args == 'R'
2190
                         || *args == 'J')
2191
                        && (mask & 3))
2192
                      {
2193
                        break;
2194
                      }         /* register must be multiple of 4 */
2195
 
2196
                    if (mask >= 64)
2197
                      {
2198
                        if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2199
                          error_message = _(": There are only 64 f registers; [0-63]");
2200
                        else
2201
                          error_message = _(": There are only 32 f registers; [0-31]");
2202
                        goto error;
2203
                      } /* on error */
2204
                    else if (mask >= 32)
2205
                      {
2206
                        if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2207
                          {
2208
                            if (*args == 'e' || *args == 'f' || *args == 'g')
2209
                              {
2210
                                error_message
2211
                                  = _(": There are only 32 single precision f registers; [0-31]");
2212
                                goto error;
2213
                              }
2214
                            v9_arg_p = 1;
2215
                            mask -= 31; /* wrap high bit */
2216
                          }
2217
                        else
2218
                          {
2219
                            error_message = _(": There are only 32 f registers; [0-31]");
2220
                            goto error;
2221
                          }
2222
                      }
2223
                  }
2224
                else
2225
                  {
2226
                    break;
2227
                  }     /* if not an 'f' register.  */
2228
 
2229
                switch (*args)
2230
                  {
2231
                  case 'v':
2232
                  case 'V':
2233
                  case 'e':
2234
                    opcode |= RS1 (mask);
2235
                    continue;
2236
 
2237
                  case 'f':
2238
                  case 'B':
2239
                  case 'R':
2240
                    opcode |= RS2 (mask);
2241
                    continue;
2242
 
2243
                  case 'g':
2244
                  case 'H':
2245
                  case 'J':
2246
                    opcode |= RD (mask);
2247
                    continue;
2248
                  }             /* Pack it in.  */
2249
 
2250
                know (0);
2251
                break;
2252
              }                 /* float arg  */
2253
 
2254
            case 'F':
2255
              if (strncmp (s, "%fsr", 4) == 0)
2256
                {
2257
                  s += 4;
2258
                  continue;
2259
                }
2260
              break;
2261
 
2262
            case '0':           /* 64 bit immediate (set, setsw, setx insn)  */
2263
              the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere  */
2264
              goto immediate;
2265
 
2266
            case 'l':           /* 22 bit PC relative immediate  */
2267
              the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2268
              the_insn.pcrel = 1;
2269
              goto immediate;
2270
 
2271
            case 'L':           /* 30 bit immediate  */
2272
              the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2273
              the_insn.pcrel = 1;
2274
              goto immediate;
2275
 
2276
            case 'h':
2277
            case 'n':           /* 22 bit immediate  */
2278
              the_insn.reloc = BFD_RELOC_SPARC22;
2279
              goto immediate;
2280
 
2281
            case 'i':           /* 13 bit immediate  */
2282
              the_insn.reloc = BFD_RELOC_SPARC13;
2283
 
2284
              /* fallthrough */
2285
 
2286
            immediate:
2287
              if (*s == ' ')
2288
                s++;
2289
 
2290
              {
2291
                char *s1;
2292
                char *op_arg = NULL;
2293
                static expressionS op_exp;
2294
                bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2295
 
2296
                /* Check for %hi, etc.  */
2297
                if (*s == '%')
2298
                  {
2299
                    static const struct ops {
2300
                      /* The name as it appears in assembler.  */
2301
                      char *name;
2302
                      /* strlen (name), precomputed for speed */
2303
                      int len;
2304
                      /* The reloc this pseudo-op translates to.  */
2305
                      int reloc;
2306
                      /* Non-zero if for v9 only.  */
2307
                      int v9_p;
2308
                      /* Non-zero if can be used in pc-relative contexts.  */
2309
                      int pcrel_p;/*FIXME:wip*/
2310
                    } ops[] = {
2311
                      /* hix/lox must appear before hi/lo so %hix won't be
2312
                         mistaken for %hi.  */
2313
                      { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2314
                      { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2315
                      { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2316
                      { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2317
                      { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2318
                      { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
2319
                      { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2320
                      { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2321
                      { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2322
                      { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2323
                      { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2324
                      { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2325
                      { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2326
                      { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2327
                      { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2328
                      { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2329
                      { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2330
                      { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2331
                      { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2332
 
2333
                      { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2334
 
2335
                      { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2336
                      { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2337
                      { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2338
                      { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2339
                      { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2340
                        0, 0 },
2341
                      { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2342
                        0, 0 },
2343
                      { NULL, 0, 0, 0, 0 }
2344
                    };
2345
                    const struct ops *o;
2346
 
2347
                    for (o = ops; o->name; o++)
2348
                      if (strncmp (s + 1, o->name, o->len) == 0)
2349
                        break;
2350
                    if (o->name == NULL)
2351
                      break;
2352
 
2353
                    if (s[o->len + 1] != '(')
2354
                      {
2355
                        as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2356
                        return special_case;
2357
                      }
2358
 
2359
                    op_arg = o->name;
2360
                    the_insn.reloc = o->reloc;
2361
                    s += o->len + 2;
2362
                    v9_arg_p = o->v9_p;
2363
                  }
2364
 
2365
                /* Note that if the get_expression() fails, we will still
2366
                   have created U entries in the symbol table for the
2367
                   'symbols' in the input string.  Try not to create U
2368
                   symbols for registers, etc.  */
2369
 
2370
                /* This stuff checks to see if the expression ends in
2371
                   +%reg.  If it does, it removes the register from
2372
                   the expression, and re-sets 's' to point to the
2373
                   right place.  */
2374
 
2375
                if (op_arg)
2376
                  {
2377
                    int npar = 0;
2378
 
2379
                    for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2380
                      if (*s1 == '(')
2381
                        npar++;
2382
                      else if (*s1 == ')')
2383
                        {
2384
                          if (!npar)
2385
                            break;
2386
                          npar--;
2387
                        }
2388
 
2389
                    if (*s1 != ')')
2390
                      {
2391
                        as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2392
                        return special_case;
2393
                      }
2394
 
2395
                    *s1 = '\0';
2396
                    (void) get_expression (s);
2397
                    *s1 = ')';
2398
                    s = s1 + 1;
2399
                    if (*s == ',' || *s == ']' || !*s)
2400
                      continue;
2401
                    if (*s != '+' && *s != '-')
2402
                      {
2403
                        as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2404
                        return special_case;
2405
                      }
2406
                    *s1 = '0';
2407
                    s = s1;
2408
                    op_exp = the_insn.exp;
2409
                    memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2410
                  }
2411
 
2412
                for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2413
                  ;
2414
 
2415
                if (s1 != s && ISDIGIT (s1[-1]))
2416
                  {
2417
                    if (s1[-2] == '%' && s1[-3] == '+')
2418
                      s1 -= 3;
2419
                    else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2420
                      s1 -= 4;
2421
                    else
2422
                      s1 = NULL;
2423
                    if (s1)
2424
                      {
2425
                        *s1 = '\0';
2426
                        if (op_arg && s1 == s + 1)
2427
                          the_insn.exp.X_op = O_absent;
2428
                        else
2429
                          (void) get_expression (s);
2430
                        *s1 = '+';
2431
                        if (op_arg)
2432
                          *s = ')';
2433
                        s = s1;
2434
                      }
2435
                  }
2436
                else
2437
                  s1 = NULL;
2438
 
2439
                if (!s1)
2440
                  {
2441
                    (void) get_expression (s);
2442
                    if (op_arg)
2443
                      *s = ')';
2444
                    s = expr_end;
2445
                  }
2446
 
2447
                if (op_arg)
2448
                  {
2449
                    the_insn.exp2 = the_insn.exp;
2450
                    the_insn.exp = op_exp;
2451
                    if (the_insn.exp2.X_op == O_absent)
2452
                      the_insn.exp2.X_op = O_illegal;
2453
                    else if (the_insn.exp.X_op == O_absent)
2454
                      {
2455
                        the_insn.exp = the_insn.exp2;
2456
                        the_insn.exp2.X_op = O_illegal;
2457
                      }
2458
                    else if (the_insn.exp.X_op == O_constant)
2459
                      {
2460
                        valueT val = the_insn.exp.X_add_number;
2461
                        switch (the_insn.reloc)
2462
                          {
2463
                          default:
2464
                            break;
2465
 
2466
                          case BFD_RELOC_SPARC_HH22:
2467
                            val = BSR (val, 32);
2468
                            /* Fall through.  */
2469
 
2470
                          case BFD_RELOC_SPARC_LM22:
2471
                          case BFD_RELOC_HI22:
2472
                            val = (val >> 10) & 0x3fffff;
2473
                            break;
2474
 
2475
                          case BFD_RELOC_SPARC_HM10:
2476
                            val = BSR (val, 32);
2477
                            /* Fall through.  */
2478
 
2479
                          case BFD_RELOC_LO10:
2480
                            val &= 0x3ff;
2481
                            break;
2482
 
2483
                          case BFD_RELOC_SPARC_H44:
2484
                            val >>= 22;
2485
                            val &= 0x3fffff;
2486
                            break;
2487
 
2488
                          case BFD_RELOC_SPARC_M44:
2489
                            val >>= 12;
2490
                            val &= 0x3ff;
2491
                            break;
2492
 
2493
                          case BFD_RELOC_SPARC_L44:
2494
                            val &= 0xfff;
2495
                            break;
2496
 
2497
                          case BFD_RELOC_SPARC_HIX22:
2498
                            val = ~val;
2499
                            val = (val >> 10) & 0x3fffff;
2500
                            break;
2501
 
2502
                          case BFD_RELOC_SPARC_LOX10:
2503
                            val = (val & 0x3ff) | 0x1c00;
2504
                            break;
2505
                          }
2506
                        the_insn.exp = the_insn.exp2;
2507
                        the_insn.exp.X_add_number += val;
2508
                        the_insn.exp2.X_op = O_illegal;
2509
                        the_insn.reloc = old_reloc;
2510
                      }
2511
                    else if (the_insn.exp2.X_op != O_constant)
2512
                      {
2513
                        as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2514
                        return special_case;
2515
                      }
2516
                    else
2517
                      {
2518
                        if (old_reloc != BFD_RELOC_SPARC13
2519
                            || the_insn.reloc != BFD_RELOC_LO10
2520
                            || sparc_arch_size != 64
2521
                            || sparc_pic_code)
2522
                          {
2523
                            as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2524
                            return special_case;
2525
                          }
2526
                        the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2527
                      }
2528
                  }
2529
              }
2530
              /* Check for constants that don't require emitting a reloc.  */
2531
              if (the_insn.exp.X_op == O_constant
2532
                  && the_insn.exp.X_add_symbol == 0
2533
                  && the_insn.exp.X_op_symbol == 0)
2534
                {
2535
                  /* For pc-relative call instructions, we reject
2536
                     constants to get better code.  */
2537
                  if (the_insn.pcrel
2538
                      && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2539
                      && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2540
                    {
2541
                      error_message = _(": PC-relative operand can't be a constant");
2542
                      goto error;
2543
                    }
2544
 
2545
                  if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2546
                      && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2547
                    {
2548
                      error_message = _(": TLS operand can't be a constant");
2549
                      goto error;
2550
                    }
2551
 
2552
                  /* Constants that won't fit are checked in md_apply_fix
2553
                     and bfd_install_relocation.
2554
                     ??? It would be preferable to install the constants
2555
                     into the insn here and save having to create a fixS
2556
                     for each one.  There already exists code to handle
2557
                     all the various cases (e.g. in md_apply_fix and
2558
                     bfd_install_relocation) so duplicating all that code
2559
                     here isn't right.  */
2560
                }
2561
 
2562
              continue;
2563
 
2564
            case 'a':
2565
              if (*s++ == 'a')
2566
                {
2567
                  opcode |= ANNUL;
2568
                  continue;
2569
                }
2570
              break;
2571
 
2572
            case 'A':
2573
              {
2574
                int asi = 0;
2575
 
2576
                /* Parse an asi.  */
2577
                if (*s == '#')
2578
                  {
2579
                    if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2580
                      {
2581
                        error_message = _(": invalid ASI name");
2582
                        goto error;
2583
                      }
2584
                  }
2585
                else
2586
                  {
2587
                    if (! parse_const_expr_arg (&s, &asi))
2588
                      {
2589
                        error_message = _(": invalid ASI expression");
2590
                        goto error;
2591
                      }
2592
                    if (asi < 0 || asi > 255)
2593
                      {
2594
                        error_message = _(": invalid ASI number");
2595
                        goto error;
2596
                      }
2597
                  }
2598
                opcode |= ASI (asi);
2599
                continue;
2600
              }                 /* Alternate space.  */
2601
 
2602
            case 'p':
2603
              if (strncmp (s, "%psr", 4) == 0)
2604
                {
2605
                  s += 4;
2606
                  continue;
2607
                }
2608
              break;
2609
 
2610
            case 'q':           /* Floating point queue.  */
2611
              if (strncmp (s, "%fq", 3) == 0)
2612
                {
2613
                  s += 3;
2614
                  continue;
2615
                }
2616
              break;
2617
 
2618
            case 'Q':           /* Coprocessor queue.  */
2619
              if (strncmp (s, "%cq", 3) == 0)
2620
                {
2621
                  s += 3;
2622
                  continue;
2623
                }
2624
              break;
2625
 
2626
            case 'S':
2627
              if (strcmp (str, "set") == 0
2628
                  || strcmp (str, "setuw") == 0)
2629
                {
2630
                  special_case = SPECIAL_CASE_SET;
2631
                  continue;
2632
                }
2633
              else if (strcmp (str, "setsw") == 0)
2634
                {
2635
                  special_case = SPECIAL_CASE_SETSW;
2636
                  continue;
2637
                }
2638
              else if (strcmp (str, "setx") == 0)
2639
                {
2640
                  special_case = SPECIAL_CASE_SETX;
2641
                  continue;
2642
                }
2643
              else if (strncmp (str, "fdiv", 4) == 0)
2644
                {
2645
                  special_case = SPECIAL_CASE_FDIV;
2646
                  continue;
2647
                }
2648
              break;
2649
 
2650
            case 'o':
2651
              if (strncmp (s, "%asi", 4) != 0)
2652
                break;
2653
              s += 4;
2654
              continue;
2655
 
2656
            case 's':
2657
              if (strncmp (s, "%fprs", 5) != 0)
2658
                break;
2659
              s += 5;
2660
              continue;
2661
 
2662
            case 'E':
2663
              if (strncmp (s, "%ccr", 4) != 0)
2664
                break;
2665
              s += 4;
2666
              continue;
2667
 
2668
            case 't':
2669
              if (strncmp (s, "%tbr", 4) != 0)
2670
                break;
2671
              s += 4;
2672
              continue;
2673
 
2674
            case 'w':
2675
              if (strncmp (s, "%wim", 4) != 0)
2676
                break;
2677
              s += 4;
2678
              continue;
2679
 
2680
            case 'x':
2681
              {
2682
                char *push = input_line_pointer;
2683
                expressionS e;
2684
 
2685
                input_line_pointer = s;
2686
                expression (&e);
2687
                if (e.X_op == O_constant)
2688
                  {
2689
                    int n = e.X_add_number;
2690
                    if (n != e.X_add_number || (n & ~0x1ff) != 0)
2691
                      as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2692
                    else
2693
                      opcode |= e.X_add_number << 5;
2694
                  }
2695
                else
2696
                  as_bad (_("non-immediate OPF operand, ignored"));
2697
                s = input_line_pointer;
2698
                input_line_pointer = push;
2699
                continue;
2700
              }
2701
 
2702
            case 'y':
2703
              if (strncmp (s, "%y", 2) != 0)
2704
                break;
2705
              s += 2;
2706
              continue;
2707
 
2708
            case 'u':
2709
            case 'U':
2710
              {
2711
                /* Parse a sparclet cpreg.  */
2712
                int cpreg;
2713
                if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2714
                  {
2715
                    error_message = _(": invalid cpreg name");
2716
                    goto error;
2717
                  }
2718
                opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2719
                continue;
2720
              }
2721
 
2722
            default:
2723
              as_fatal (_("failed sanity check."));
2724
            }                   /* switch on arg code.  */
2725
 
2726
          /* Break out of for() loop.  */
2727
          break;
2728
        }                       /* For each arg that we expect.  */
2729
 
2730
    error:
2731
      if (match == 0)
2732
        {
2733
          /* Args don't match.  */
2734
          if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2735
              && (insn->name == insn[1].name
2736
                  || !strcmp (insn->name, insn[1].name)))
2737
            {
2738
              ++insn;
2739
              s = argsStart;
2740
              continue;
2741
            }
2742
          else
2743
            {
2744
              as_bad (_("Illegal operands%s"), error_message);
2745
              return special_case;
2746
            }
2747
        }
2748
      else
2749
        {
2750
          /* We have a match.  Now see if the architecture is OK.  */
2751
          int needed_arch_mask = insn->architecture;
2752
 
2753
          if (v9_arg_p)
2754
            {
2755
              needed_arch_mask &=
2756
                ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2757
              if (! needed_arch_mask)
2758
                needed_arch_mask =
2759
                  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2760
            }
2761
 
2762
          if (needed_arch_mask
2763
              & SPARC_OPCODE_SUPPORTED (current_architecture))
2764
            /* OK.  */
2765
            ;
2766
          /* Can we bump up the architecture?  */
2767
          else if (needed_arch_mask
2768
                   & SPARC_OPCODE_SUPPORTED (max_architecture))
2769
            {
2770
              enum sparc_opcode_arch_val needed_architecture =
2771
                sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2772
                           & needed_arch_mask);
2773
 
2774
              assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2775
              if (warn_on_bump
2776
                  && needed_architecture > warn_after_architecture)
2777
                {
2778
                  as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2779
                           sparc_opcode_archs[current_architecture].name,
2780
                           sparc_opcode_archs[needed_architecture].name,
2781
                           str);
2782
                  warn_after_architecture = needed_architecture;
2783
                }
2784
              current_architecture = needed_architecture;
2785
            }
2786
          /* Conflict.  */
2787
          /* ??? This seems to be a bit fragile.  What if the next entry in
2788
             the opcode table is the one we want and it is supported?
2789
             It is possible to arrange the table today so that this can't
2790
             happen but what about tomorrow?  */
2791
          else
2792
            {
2793
              int arch, printed_one_p = 0;
2794
              char *p;
2795
              char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2796
 
2797
              /* Create a list of the architectures that support the insn.  */
2798
              needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2799
              p = required_archs;
2800
              arch = sparc_ffs (needed_arch_mask);
2801
              while ((1 << arch) <= needed_arch_mask)
2802
                {
2803
                  if ((1 << arch) & needed_arch_mask)
2804
                    {
2805
                      if (printed_one_p)
2806
                        *p++ = '|';
2807
                      strcpy (p, sparc_opcode_archs[arch].name);
2808
                      p += strlen (p);
2809
                      printed_one_p = 1;
2810
                    }
2811
                  ++arch;
2812
                }
2813
 
2814
              as_bad (_("Architecture mismatch on \"%s\"."), str);
2815
              as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2816
                         required_archs,
2817
                         sparc_opcode_archs[max_architecture].name);
2818
              return special_case;
2819
            }
2820
        } /* If no match.  */
2821
 
2822
      break;
2823
    } /* Forever looking for a match.  */
2824
 
2825
  the_insn.opcode = opcode;
2826
  return special_case;
2827
}
2828
 
2829
/* Parse an argument that can be expressed as a keyword.
2830
   (eg: #StoreStore or %ccfr).
2831
   The result is a boolean indicating success.
2832
   If successful, INPUT_POINTER is updated.  */
2833
 
2834
static int
2835
parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2836
     int (*lookup_fn) PARAMS ((const char *));
2837
     char **input_pointerP;
2838
     int *valueP;
2839
{
2840
  int value;
2841
  char c, *p, *q;
2842
 
2843
  p = *input_pointerP;
2844
  for (q = p + (*p == '#' || *p == '%');
2845
       ISALNUM (*q) || *q == '_';
2846
       ++q)
2847
    continue;
2848
  c = *q;
2849
  *q = 0;
2850
  value = (*lookup_fn) (p);
2851
  *q = c;
2852
  if (value == -1)
2853
    return 0;
2854
  *valueP = value;
2855
  *input_pointerP = q;
2856
  return 1;
2857
}
2858
 
2859
/* Parse an argument that is a constant expression.
2860
   The result is a boolean indicating success.  */
2861
 
2862
static int
2863
parse_const_expr_arg (input_pointerP, valueP)
2864
     char **input_pointerP;
2865
     int *valueP;
2866
{
2867
  char *save = input_line_pointer;
2868
  expressionS exp;
2869
 
2870
  input_line_pointer = *input_pointerP;
2871
  /* The next expression may be something other than a constant
2872
     (say if we're not processing the right variant of the insn).
2873
     Don't call expression unless we're sure it will succeed as it will
2874
     signal an error (which we want to defer until later).  */
2875
  /* FIXME: It might be better to define md_operand and have it recognize
2876
     things like %asi, etc. but continuing that route through to the end
2877
     is a lot of work.  */
2878
  if (*input_line_pointer == '%')
2879
    {
2880
      input_line_pointer = save;
2881
      return 0;
2882
    }
2883
  expression (&exp);
2884
  *input_pointerP = input_line_pointer;
2885
  input_line_pointer = save;
2886
  if (exp.X_op != O_constant)
2887
    return 0;
2888
  *valueP = exp.X_add_number;
2889
  return 1;
2890
}
2891
 
2892
/* Subroutine of sparc_ip to parse an expression.  */
2893
 
2894
static int
2895
get_expression (str)
2896
     char *str;
2897
{
2898
  char *save_in;
2899
  segT seg;
2900
 
2901
  save_in = input_line_pointer;
2902
  input_line_pointer = str;
2903
  seg = expression (&the_insn.exp);
2904
  if (seg != absolute_section
2905
      && seg != text_section
2906
      && seg != data_section
2907
      && seg != bss_section
2908
      && seg != undefined_section)
2909
    {
2910
      the_insn.error = _("bad segment");
2911
      expr_end = input_line_pointer;
2912
      input_line_pointer = save_in;
2913
      return 1;
2914
    }
2915
  expr_end = input_line_pointer;
2916
  input_line_pointer = save_in;
2917
  return 0;
2918
}
2919
 
2920
/* Subroutine of md_assemble to output one insn.  */
2921
 
2922
static void
2923
output_insn (insn, the_insn)
2924
     const struct sparc_opcode *insn;
2925
     struct sparc_it *the_insn;
2926
{
2927
  char *toP = frag_more (4);
2928
 
2929
  /* Put out the opcode.  */
2930
  if (INSN_BIG_ENDIAN)
2931
    number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2932
  else
2933
    number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2934
 
2935
  /* Put out the symbol-dependent stuff.  */
2936
  if (the_insn->reloc != BFD_RELOC_NONE)
2937
    {
2938
      fixS *fixP =  fix_new_exp (frag_now,      /* Which frag.  */
2939
                                 (toP - frag_now->fr_literal),  /* Where.  */
2940
                                 4,             /* Size.  */
2941
                                 &the_insn->exp,
2942
                                 the_insn->pcrel,
2943
                                 the_insn->reloc);
2944
      /* Turn off overflow checking in fixup_segment.  We'll do our
2945
         own overflow checking in md_apply_fix.  This is necessary because
2946
         the insn size is 4 and fixup_segment will signal an overflow for
2947
         large 8 byte quantities.  */
2948
      fixP->fx_no_overflow = 1;
2949
      if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2950
        fixP->tc_fix_data = the_insn->exp2.X_add_number;
2951
    }
2952
 
2953
  last_insn = insn;
2954
  last_opcode = the_insn->opcode;
2955
 
2956
#ifdef OBJ_ELF
2957
  dwarf2_emit_insn (4);
2958
#endif
2959
}
2960
 
2961
char *
2962
md_atof (int type, char *litP, int *sizeP)
2963
{
2964
  return ieee_md_atof (type, litP, sizeP, target_big_endian);
2965
}
2966
 
2967
/* Write a value out to the object file, using the appropriate
2968
   endianness.  */
2969
 
2970
void
2971
md_number_to_chars (buf, val, n)
2972
     char *buf;
2973
     valueT val;
2974
     int n;
2975
{
2976
  if (target_big_endian)
2977
    number_to_chars_bigendian (buf, val, n);
2978
  else if (target_little_endian_data
2979
           && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2980
    /* Output debug words, which are not in allocated sections, as big
2981
       endian.  */
2982
    number_to_chars_bigendian (buf, val, n);
2983
  else if (target_little_endian_data || ! target_big_endian)
2984
    number_to_chars_littleendian (buf, val, n);
2985
}
2986
 
2987
/* Apply a fixS to the frags, now that we know the value it ought to
2988
   hold.  */
2989
 
2990
void
2991
md_apply_fix (fixP, valP, segment)
2992
     fixS *fixP;
2993
     valueT *valP;
2994
     segT segment ATTRIBUTE_UNUSED;
2995
{
2996
  char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2997
  offsetT val = * (offsetT *) valP;
2998
  long insn;
2999
 
3000
  assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3001
 
3002
  fixP->fx_addnumber = val;     /* Remember value for emit_reloc.  */
3003
 
3004
#ifdef OBJ_ELF
3005
  /* SPARC ELF relocations don't use an addend in the data field.  */
3006
  if (fixP->fx_addsy != NULL)
3007
    {
3008
      switch (fixP->fx_r_type)
3009
        {
3010
        case BFD_RELOC_SPARC_TLS_GD_HI22:
3011
        case BFD_RELOC_SPARC_TLS_GD_LO10:
3012
        case BFD_RELOC_SPARC_TLS_GD_ADD:
3013
        case BFD_RELOC_SPARC_TLS_GD_CALL:
3014
        case BFD_RELOC_SPARC_TLS_LDM_HI22:
3015
        case BFD_RELOC_SPARC_TLS_LDM_LO10:
3016
        case BFD_RELOC_SPARC_TLS_LDM_ADD:
3017
        case BFD_RELOC_SPARC_TLS_LDM_CALL:
3018
        case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3019
        case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3020
        case BFD_RELOC_SPARC_TLS_LDO_ADD:
3021
        case BFD_RELOC_SPARC_TLS_IE_HI22:
3022
        case BFD_RELOC_SPARC_TLS_IE_LO10:
3023
        case BFD_RELOC_SPARC_TLS_IE_LD:
3024
        case BFD_RELOC_SPARC_TLS_IE_LDX:
3025
        case BFD_RELOC_SPARC_TLS_IE_ADD:
3026
        case BFD_RELOC_SPARC_TLS_LE_HIX22:
3027
        case BFD_RELOC_SPARC_TLS_LE_LOX10:
3028
        case BFD_RELOC_SPARC_TLS_DTPMOD32:
3029
        case BFD_RELOC_SPARC_TLS_DTPMOD64:
3030
        case BFD_RELOC_SPARC_TLS_DTPOFF32:
3031
        case BFD_RELOC_SPARC_TLS_DTPOFF64:
3032
        case BFD_RELOC_SPARC_TLS_TPOFF32:
3033
        case BFD_RELOC_SPARC_TLS_TPOFF64:
3034
          S_SET_THREAD_LOCAL (fixP->fx_addsy);
3035
 
3036
        default:
3037
          break;
3038
        }
3039
 
3040
      return;
3041
    }
3042
#endif
3043
 
3044
  /* This is a hack.  There should be a better way to
3045
     handle this.  Probably in terms of howto fields, once
3046
     we can look at these fixups in terms of howtos.  */
3047
  if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3048
    val += fixP->fx_where + fixP->fx_frag->fr_address;
3049
 
3050
#ifdef OBJ_AOUT
3051
  /* FIXME: More ridiculous gas reloc hacking.  If we are going to
3052
     generate a reloc, then we just want to let the reloc addend set
3053
     the value.  We do not want to also stuff the addend into the
3054
     object file.  Including the addend in the object file works when
3055
     doing a static link, because the linker will ignore the object
3056
     file contents.  However, the dynamic linker does not ignore the
3057
     object file contents.  */
3058
  if (fixP->fx_addsy != NULL
3059
      && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3060
    val = 0;
3061
 
3062
  /* When generating PIC code, we do not want an addend for a reloc
3063
     against a local symbol.  We adjust fx_addnumber to cancel out the
3064
     value already included in val, and to also cancel out the
3065
     adjustment which bfd_install_relocation will create.  */
3066
  if (sparc_pic_code
3067
      && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3068
      && fixP->fx_addsy != NULL
3069
      && ! S_IS_COMMON (fixP->fx_addsy)
3070
      && symbol_section_p (fixP->fx_addsy))
3071
    fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3072
 
3073
  /* When generating PIC code, we need to fiddle to get
3074
     bfd_install_relocation to do the right thing for a PC relative
3075
     reloc against a local symbol which we are going to keep.  */
3076
  if (sparc_pic_code
3077
      && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3078
      && fixP->fx_addsy != NULL
3079
      && (S_IS_EXTERNAL (fixP->fx_addsy)
3080
          || S_IS_WEAK (fixP->fx_addsy))
3081
      && S_IS_DEFINED (fixP->fx_addsy)
3082
      && ! S_IS_COMMON (fixP->fx_addsy))
3083
    {
3084
      val = 0;
3085
      fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3086
    }
3087
#endif
3088
 
3089
  /* If this is a data relocation, just output VAL.  */
3090
 
3091
  if (fixP->fx_r_type == BFD_RELOC_16
3092
      || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3093
    {
3094
      md_number_to_chars (buf, val, 2);
3095
    }
3096
  else if (fixP->fx_r_type == BFD_RELOC_32
3097
           || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3098
           || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3099
    {
3100
      md_number_to_chars (buf, val, 4);
3101
    }
3102
  else if (fixP->fx_r_type == BFD_RELOC_64
3103
           || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3104
    {
3105
      md_number_to_chars (buf, val, 8);
3106
    }
3107
  else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3108
           || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3109
    {
3110
      fixP->fx_done = 0;
3111
      return;
3112
    }
3113
  else
3114
    {
3115
      /* It's a relocation against an instruction.  */
3116
 
3117
      if (INSN_BIG_ENDIAN)
3118
        insn = bfd_getb32 ((unsigned char *) buf);
3119
      else
3120
        insn = bfd_getl32 ((unsigned char *) buf);
3121
 
3122
      switch (fixP->fx_r_type)
3123
        {
3124
        case BFD_RELOC_32_PCREL_S2:
3125
          val = val >> 2;
3126
          /* FIXME: This increment-by-one deserves a comment of why it's
3127
             being done!  */
3128
          if (! sparc_pic_code
3129
              || fixP->fx_addsy == NULL
3130
              || symbol_section_p (fixP->fx_addsy))
3131
            ++val;
3132
 
3133
          insn |= val & 0x3fffffff;
3134
 
3135
          /* See if we have a delay slot.  */
3136
          if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3137
            {
3138
#define G0              0
3139
#define O7              15
3140
#define XCC             (2 << 20)
3141
#define COND(x)         (((x)&0xf)<<25)
3142
#define CONDA           COND(0x8)
3143
#define INSN_BPA        (F2(0,1) | CONDA | BPRED | XCC)
3144
#define INSN_BA         (F2(0,2) | CONDA)
3145
#define INSN_OR         F3(2, 0x2, 0)
3146
#define INSN_NOP        F2(0,4)
3147
 
3148
              long delay;
3149
 
3150
              /* If the instruction is a call with either:
3151
                 restore
3152
                 arithmetic instruction with rd == %o7
3153
                 where rs1 != %o7 and rs2 if it is register != %o7
3154
                 then we can optimize if the call destination is near
3155
                 by changing the call into a branch always.  */
3156
              if (INSN_BIG_ENDIAN)
3157
                delay = bfd_getb32 ((unsigned char *) buf + 4);
3158
              else
3159
                delay = bfd_getl32 ((unsigned char *) buf + 4);
3160
              if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3161
                break;
3162
              if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore.  */
3163
                  && ((delay & OP3 (0x28)) != 0 /* Arithmetic.  */
3164
                      || ((delay & RD (~0)) != RD (O7))))
3165
                break;
3166
              if ((delay & RS1 (~0)) == RS1 (O7)
3167
                  || ((delay & F3I (~0)) == 0
3168
                      && (delay & RS2 (~0)) == RS2 (O7)))
3169
                break;
3170
              /* Ensure the branch will fit into simm22.  */
3171
              if ((val & 0x3fe00000)
3172
                  && (val & 0x3fe00000) != 0x3fe00000)
3173
                break;
3174
              /* Check if the arch is v9 and branch will fit
3175
                 into simm19.  */
3176
              if (((val & 0x3c0000) == 0
3177
                   || (val & 0x3c0000) == 0x3c0000)
3178
                  && (sparc_arch_size == 64
3179
                      || current_architecture >= SPARC_OPCODE_ARCH_V9))
3180
                /* ba,pt %xcc  */
3181
                insn = INSN_BPA | (val & 0x7ffff);
3182
              else
3183
                /* ba  */
3184
                insn = INSN_BA | (val & 0x3fffff);
3185
              if (fixP->fx_where >= 4
3186
                  && ((delay & (0xffffffff ^ RS1 (~0)))
3187
                      == (INSN_OR | RD (O7) | RS2 (G0))))
3188
                {
3189
                  long setter;
3190
                  int reg;
3191
 
3192
                  if (INSN_BIG_ENDIAN)
3193
                    setter = bfd_getb32 ((unsigned char *) buf - 4);
3194
                  else
3195
                    setter = bfd_getl32 ((unsigned char *) buf - 4);
3196
                  if ((setter & (0xffffffff ^ RD (~0)))
3197
                      != (INSN_OR | RS1 (O7) | RS2 (G0)))
3198
                    break;
3199
                  /* The sequence was
3200
                     or %o7, %g0, %rN
3201
                     call foo
3202
                     or %rN, %g0, %o7
3203
 
3204
                     If call foo was replaced with ba, replace
3205
                     or %rN, %g0, %o7 with nop.  */
3206
                  reg = (delay & RS1 (~0)) >> 14;
3207
                  if (reg != ((setter & RD (~0)) >> 25)
3208
                      || reg == G0 || reg == O7)
3209
                    break;
3210
 
3211
                  if (INSN_BIG_ENDIAN)
3212
                    bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3213
                  else
3214
                    bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3215
                }
3216
            }
3217
          break;
3218
 
3219
        case BFD_RELOC_SPARC_11:
3220
          if (! in_signed_range (val, 0x7ff))
3221
            as_bad_where (fixP->fx_file, fixP->fx_line,
3222
                          _("relocation overflow"));
3223
          insn |= val & 0x7ff;
3224
          break;
3225
 
3226
        case BFD_RELOC_SPARC_10:
3227
          if (! in_signed_range (val, 0x3ff))
3228
            as_bad_where (fixP->fx_file, fixP->fx_line,
3229
                          _("relocation overflow"));
3230
          insn |= val & 0x3ff;
3231
          break;
3232
 
3233
        case BFD_RELOC_SPARC_7:
3234
          if (! in_bitfield_range (val, 0x7f))
3235
            as_bad_where (fixP->fx_file, fixP->fx_line,
3236
                          _("relocation overflow"));
3237
          insn |= val & 0x7f;
3238
          break;
3239
 
3240
        case BFD_RELOC_SPARC_6:
3241
          if (! in_bitfield_range (val, 0x3f))
3242
            as_bad_where (fixP->fx_file, fixP->fx_line,
3243
                          _("relocation overflow"));
3244
          insn |= val & 0x3f;
3245
          break;
3246
 
3247
        case BFD_RELOC_SPARC_5:
3248
          if (! in_bitfield_range (val, 0x1f))
3249
            as_bad_where (fixP->fx_file, fixP->fx_line,
3250
                          _("relocation overflow"));
3251
          insn |= val & 0x1f;
3252
          break;
3253
 
3254
        case BFD_RELOC_SPARC_WDISP16:
3255
          if ((val & 3)
3256
              || val >= 0x1fffc
3257
              || val <= -(offsetT) 0x20008)
3258
            as_bad_where (fixP->fx_file, fixP->fx_line,
3259
                          _("relocation overflow"));
3260
          /* FIXME: The +1 deserves a comment.  */
3261
          val = (val >> 2) + 1;
3262
          insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3263
          break;
3264
 
3265
        case BFD_RELOC_SPARC_WDISP19:
3266
          if ((val & 3)
3267
              || val >= 0xffffc
3268
              || val <= -(offsetT) 0x100008)
3269
            as_bad_where (fixP->fx_file, fixP->fx_line,
3270
                          _("relocation overflow"));
3271
          /* FIXME: The +1 deserves a comment.  */
3272
          val = (val >> 2) + 1;
3273
          insn |= val & 0x7ffff;
3274
          break;
3275
 
3276
        case BFD_RELOC_SPARC_HH22:
3277
          val = BSR (val, 32);
3278
          /* Fall through.  */
3279
 
3280
        case BFD_RELOC_SPARC_LM22:
3281
        case BFD_RELOC_HI22:
3282
          if (!fixP->fx_addsy)
3283
            insn |= (val >> 10) & 0x3fffff;
3284
          else
3285
            /* FIXME: Need comment explaining why we do this.  */
3286
            insn &= ~0xffff;
3287
          break;
3288
 
3289
        case BFD_RELOC_SPARC22:
3290
          if (val & ~0x003fffff)
3291
            as_bad_where (fixP->fx_file, fixP->fx_line,
3292
                          _("relocation overflow"));
3293
          insn |= (val & 0x3fffff);
3294
          break;
3295
 
3296
        case BFD_RELOC_SPARC_HM10:
3297
          val = BSR (val, 32);
3298
          /* Fall through.  */
3299
 
3300
        case BFD_RELOC_LO10:
3301
          if (!fixP->fx_addsy)
3302
            insn |= val & 0x3ff;
3303
          else
3304
            /* FIXME: Need comment explaining why we do this.  */
3305
            insn &= ~0xff;
3306
          break;
3307
 
3308
        case BFD_RELOC_SPARC_OLO10:
3309
          val &= 0x3ff;
3310
          val += fixP->tc_fix_data;
3311
          /* Fall through.  */
3312
 
3313
        case BFD_RELOC_SPARC13:
3314
          if (! in_signed_range (val, 0x1fff))
3315
            as_bad_where (fixP->fx_file, fixP->fx_line,
3316
                          _("relocation overflow"));
3317
          insn |= val & 0x1fff;
3318
          break;
3319
 
3320
        case BFD_RELOC_SPARC_WDISP22:
3321
          val = (val >> 2) + 1;
3322
          /* Fall through.  */
3323
        case BFD_RELOC_SPARC_BASE22:
3324
          insn |= val & 0x3fffff;
3325
          break;
3326
 
3327
        case BFD_RELOC_SPARC_H44:
3328
          if (!fixP->fx_addsy)
3329
            {
3330
              bfd_vma tval = val;
3331
              tval >>= 22;
3332
              insn |= tval & 0x3fffff;
3333
            }
3334
          break;
3335
 
3336
        case BFD_RELOC_SPARC_M44:
3337
          if (!fixP->fx_addsy)
3338
            insn |= (val >> 12) & 0x3ff;
3339
          break;
3340
 
3341
        case BFD_RELOC_SPARC_L44:
3342
          if (!fixP->fx_addsy)
3343
            insn |= val & 0xfff;
3344
          break;
3345
 
3346
        case BFD_RELOC_SPARC_HIX22:
3347
          if (!fixP->fx_addsy)
3348
            {
3349
              val ^= ~(offsetT) 0;
3350
              insn |= (val >> 10) & 0x3fffff;
3351
            }
3352
          break;
3353
 
3354
        case BFD_RELOC_SPARC_LOX10:
3355
          if (!fixP->fx_addsy)
3356
            insn |= 0x1c00 | (val & 0x3ff);
3357
          break;
3358
 
3359
        case BFD_RELOC_NONE:
3360
        default:
3361
          as_bad_where (fixP->fx_file, fixP->fx_line,
3362
                        _("bad or unhandled relocation type: 0x%02x"),
3363
                        fixP->fx_r_type);
3364
          break;
3365
        }
3366
 
3367
      if (INSN_BIG_ENDIAN)
3368
        bfd_putb32 (insn, (unsigned char *) buf);
3369
      else
3370
        bfd_putl32 (insn, (unsigned char *) buf);
3371
    }
3372
 
3373
  /* Are we finished with this relocation now?  */
3374
  if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3375
    fixP->fx_done = 1;
3376
}
3377
 
3378
/* Translate internal representation of relocation info to BFD target
3379
   format.  */
3380
 
3381
arelent **
3382
tc_gen_reloc (section, fixp)
3383
     asection *section;
3384
     fixS *fixp;
3385
{
3386
  static arelent *relocs[3];
3387
  arelent *reloc;
3388
  bfd_reloc_code_real_type code;
3389
 
3390
  relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3391
  relocs[1] = NULL;
3392
 
3393
  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3394
  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3395
  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3396
 
3397
  switch (fixp->fx_r_type)
3398
    {
3399
    case BFD_RELOC_16:
3400
    case BFD_RELOC_32:
3401
    case BFD_RELOC_HI22:
3402
    case BFD_RELOC_LO10:
3403
    case BFD_RELOC_32_PCREL_S2:
3404
    case BFD_RELOC_SPARC13:
3405
    case BFD_RELOC_SPARC22:
3406
    case BFD_RELOC_SPARC_PC22:
3407
    case BFD_RELOC_SPARC_PC10:
3408
    case BFD_RELOC_SPARC_BASE13:
3409
    case BFD_RELOC_SPARC_WDISP16:
3410
    case BFD_RELOC_SPARC_WDISP19:
3411
    case BFD_RELOC_SPARC_WDISP22:
3412
    case BFD_RELOC_64:
3413
    case BFD_RELOC_SPARC_5:
3414
    case BFD_RELOC_SPARC_6:
3415
    case BFD_RELOC_SPARC_7:
3416
    case BFD_RELOC_SPARC_10:
3417
    case BFD_RELOC_SPARC_11:
3418
    case BFD_RELOC_SPARC_HH22:
3419
    case BFD_RELOC_SPARC_HM10:
3420
    case BFD_RELOC_SPARC_LM22:
3421
    case BFD_RELOC_SPARC_PC_HH22:
3422
    case BFD_RELOC_SPARC_PC_HM10:
3423
    case BFD_RELOC_SPARC_PC_LM22:
3424
    case BFD_RELOC_SPARC_H44:
3425
    case BFD_RELOC_SPARC_M44:
3426
    case BFD_RELOC_SPARC_L44:
3427
    case BFD_RELOC_SPARC_HIX22:
3428
    case BFD_RELOC_SPARC_LOX10:
3429
    case BFD_RELOC_SPARC_REV32:
3430
    case BFD_RELOC_SPARC_OLO10:
3431
    case BFD_RELOC_SPARC_UA16:
3432
    case BFD_RELOC_SPARC_UA32:
3433
    case BFD_RELOC_SPARC_UA64:
3434
    case BFD_RELOC_8_PCREL:
3435
    case BFD_RELOC_16_PCREL:
3436
    case BFD_RELOC_32_PCREL:
3437
    case BFD_RELOC_64_PCREL:
3438
    case BFD_RELOC_SPARC_PLT32:
3439
    case BFD_RELOC_SPARC_PLT64:
3440
    case BFD_RELOC_VTABLE_ENTRY:
3441
    case BFD_RELOC_VTABLE_INHERIT:
3442
    case BFD_RELOC_SPARC_TLS_GD_HI22:
3443
    case BFD_RELOC_SPARC_TLS_GD_LO10:
3444
    case BFD_RELOC_SPARC_TLS_GD_ADD:
3445
    case BFD_RELOC_SPARC_TLS_GD_CALL:
3446
    case BFD_RELOC_SPARC_TLS_LDM_HI22:
3447
    case BFD_RELOC_SPARC_TLS_LDM_LO10:
3448
    case BFD_RELOC_SPARC_TLS_LDM_ADD:
3449
    case BFD_RELOC_SPARC_TLS_LDM_CALL:
3450
    case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3451
    case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3452
    case BFD_RELOC_SPARC_TLS_LDO_ADD:
3453
    case BFD_RELOC_SPARC_TLS_IE_HI22:
3454
    case BFD_RELOC_SPARC_TLS_IE_LO10:
3455
    case BFD_RELOC_SPARC_TLS_IE_LD:
3456
    case BFD_RELOC_SPARC_TLS_IE_LDX:
3457
    case BFD_RELOC_SPARC_TLS_IE_ADD:
3458
    case BFD_RELOC_SPARC_TLS_LE_HIX22:
3459
    case BFD_RELOC_SPARC_TLS_LE_LOX10:
3460
    case BFD_RELOC_SPARC_TLS_DTPOFF32:
3461
    case BFD_RELOC_SPARC_TLS_DTPOFF64:
3462
    case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3463
    case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3464
    case BFD_RELOC_SPARC_GOTDATA_OP:
3465
      code = fixp->fx_r_type;
3466
      break;
3467
    default:
3468
      abort ();
3469
      return NULL;
3470
    }
3471
 
3472
#if defined (OBJ_ELF) || defined (OBJ_AOUT)
3473
  /* If we are generating PIC code, we need to generate a different
3474
     set of relocs.  */
3475
 
3476
#ifdef OBJ_ELF
3477
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3478
#else
3479
#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3480
#endif
3481
#ifdef TE_VXWORKS
3482
#define GOTT_BASE "__GOTT_BASE__"
3483
#define GOTT_INDEX "__GOTT_INDEX__"
3484
#endif
3485
 
3486
  /* This code must be parallel to the OBJ_ELF tc_fix_adjustable.  */
3487
 
3488
  if (sparc_pic_code)
3489
    {
3490
      switch (code)
3491
        {
3492
        case BFD_RELOC_32_PCREL_S2:
3493
          if (generic_force_reloc (fixp))
3494
            code = BFD_RELOC_SPARC_WPLT30;
3495
          break;
3496
        case BFD_RELOC_HI22:
3497
          code = BFD_RELOC_SPARC_GOT22;
3498
          if (fixp->fx_addsy != NULL)
3499
            {
3500
              if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3501
                code = BFD_RELOC_SPARC_PC22;
3502
#ifdef TE_VXWORKS
3503
              if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3504
                  || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3505
                code = BFD_RELOC_HI22; /* Unchanged.  */
3506
#endif
3507
            }
3508
          break;
3509
        case BFD_RELOC_LO10:
3510
          code = BFD_RELOC_SPARC_GOT10;
3511
          if (fixp->fx_addsy != NULL)
3512
            {
3513
              if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3514
                code = BFD_RELOC_SPARC_PC10;
3515
#ifdef TE_VXWORKS
3516
              if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3517
                  || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3518
                code = BFD_RELOC_LO10; /* Unchanged.  */
3519
#endif
3520
            }
3521
          break;
3522
        case BFD_RELOC_SPARC13:
3523
          code = BFD_RELOC_SPARC_GOT13;
3524
          break;
3525
        default:
3526
          break;
3527
        }
3528
    }
3529
#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT)  */
3530
 
3531
  /* Nothing is aligned in DWARF debugging sections.  */
3532
  if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3533
    switch (code)
3534
      {
3535
      case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3536
      case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3537
      case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3538
      default: break;
3539
      }
3540
 
3541
  if (code == BFD_RELOC_SPARC_OLO10)
3542
    reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3543
  else
3544
    reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3545
  if (reloc->howto == 0)
3546
    {
3547
      as_bad_where (fixp->fx_file, fixp->fx_line,
3548
                    _("internal error: can't export reloc type %d (`%s')"),
3549
                    fixp->fx_r_type, bfd_get_reloc_code_name (code));
3550
      xfree (reloc);
3551
      relocs[0] = NULL;
3552
      return relocs;
3553
    }
3554
 
3555
  /* @@ Why fx_addnumber sometimes and fx_offset other times?  */
3556
#ifdef OBJ_AOUT
3557
 
3558
  if (reloc->howto->pc_relative == 0
3559
      || code == BFD_RELOC_SPARC_PC10
3560
      || code == BFD_RELOC_SPARC_PC22)
3561
    reloc->addend = fixp->fx_addnumber;
3562
  else if (sparc_pic_code
3563
           && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3564
           && fixp->fx_addsy != NULL
3565
           && (S_IS_EXTERNAL (fixp->fx_addsy)
3566
               || S_IS_WEAK (fixp->fx_addsy))
3567
           && S_IS_DEFINED (fixp->fx_addsy)
3568
           && ! S_IS_COMMON (fixp->fx_addsy))
3569
    reloc->addend = fixp->fx_addnumber;
3570
  else
3571
    reloc->addend = fixp->fx_offset - reloc->address;
3572
 
3573
#else /* elf or coff  */
3574
 
3575
  if (code != BFD_RELOC_32_PCREL_S2
3576
      && code != BFD_RELOC_SPARC_WDISP22
3577
      && code != BFD_RELOC_SPARC_WDISP16
3578
      && code != BFD_RELOC_SPARC_WDISP19
3579
      && code != BFD_RELOC_SPARC_WPLT30
3580
      && code != BFD_RELOC_SPARC_TLS_GD_CALL
3581
      && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3582
    reloc->addend = fixp->fx_addnumber;
3583
  else if (symbol_section_p (fixp->fx_addsy))
3584
    reloc->addend = (section->vma
3585
                     + fixp->fx_addnumber
3586
                     + md_pcrel_from (fixp));
3587
  else
3588
    reloc->addend = fixp->fx_offset;
3589
#endif
3590
 
3591
  /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3592
     on the same location.  */
3593
  if (code == BFD_RELOC_SPARC_OLO10)
3594
    {
3595
      relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3596
      relocs[2] = NULL;
3597
 
3598
      reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3599
      *reloc->sym_ptr_ptr
3600
        = symbol_get_bfdsym (section_symbol (absolute_section));
3601
      reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3602
      reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3603
      reloc->addend = fixp->tc_fix_data;
3604
    }
3605
 
3606
  return relocs;
3607
}
3608
 
3609
/* We have no need to default values of symbols.  */
3610
 
3611
symbolS *
3612
md_undefined_symbol (name)
3613
     char *name ATTRIBUTE_UNUSED;
3614
{
3615
  return 0;
3616
}
3617
 
3618
/* Round up a section size to the appropriate boundary.  */
3619
 
3620
valueT
3621
md_section_align (segment, size)
3622
     segT segment ATTRIBUTE_UNUSED;
3623
     valueT size;
3624
{
3625
#ifndef OBJ_ELF
3626
  /* This is not right for ELF; a.out wants it, and COFF will force
3627
     the alignment anyways.  */
3628
  valueT align = ((valueT) 1
3629
                  << (valueT) bfd_get_section_alignment (stdoutput, segment));
3630
  valueT newsize;
3631
 
3632
  /* Turn alignment value into a mask.  */
3633
  align--;
3634
  newsize = (size + align) & ~align;
3635
  return newsize;
3636
#else
3637
  return size;
3638
#endif
3639
}
3640
 
3641
/* Exactly what point is a PC-relative offset relative TO?
3642
   On the sparc, they're relative to the address of the offset, plus
3643
   its size.  This gets us to the following instruction.
3644
   (??? Is this right?  FIXME-SOON)  */
3645
long
3646
md_pcrel_from (fixP)
3647
     fixS *fixP;
3648
{
3649
  long ret;
3650
 
3651
  ret = fixP->fx_where + fixP->fx_frag->fr_address;
3652
  if (! sparc_pic_code
3653
      || fixP->fx_addsy == NULL
3654
      || symbol_section_p (fixP->fx_addsy))
3655
    ret += fixP->fx_size;
3656
  return ret;
3657
}
3658
 
3659
/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3660
   of two.  */
3661
 
3662
static int
3663
mylog2 (value)
3664
     int value;
3665
{
3666
  int shift;
3667
 
3668
  if (value <= 0)
3669
    return -1;
3670
 
3671
  for (shift = 0; (value & 1) == 0; value >>= 1)
3672
    ++shift;
3673
 
3674
  return (value == 1) ? shift : -1;
3675
}
3676
 
3677
/* Sort of like s_lcomm.  */
3678
 
3679
#ifndef OBJ_ELF
3680
static int max_alignment = 15;
3681
#endif
3682
 
3683
static void
3684
s_reserve (ignore)
3685
     int ignore ATTRIBUTE_UNUSED;
3686
{
3687
  char *name;
3688
  char *p;
3689
  char c;
3690
  int align;
3691
  int size;
3692
  int temp;
3693
  symbolS *symbolP;
3694
 
3695
  name = input_line_pointer;
3696
  c = get_symbol_end ();
3697
  p = input_line_pointer;
3698
  *p = c;
3699
  SKIP_WHITESPACE ();
3700
 
3701
  if (*input_line_pointer != ',')
3702
    {
3703
      as_bad (_("Expected comma after name"));
3704
      ignore_rest_of_line ();
3705
      return;
3706
    }
3707
 
3708
  ++input_line_pointer;
3709
 
3710
  if ((size = get_absolute_expression ()) < 0)
3711
    {
3712
      as_bad (_("BSS length (%d.) <0! Ignored."), size);
3713
      ignore_rest_of_line ();
3714
      return;
3715
    }                           /* Bad length.  */
3716
 
3717
  *p = 0;
3718
  symbolP = symbol_find_or_make (name);
3719
  *p = c;
3720
 
3721
  if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3722
      && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3723
    {
3724
      as_bad (_("bad .reserve segment -- expected BSS segment"));
3725
      return;
3726
    }
3727
 
3728
  if (input_line_pointer[2] == '.')
3729
    input_line_pointer += 7;
3730
  else
3731
    input_line_pointer += 6;
3732
  SKIP_WHITESPACE ();
3733
 
3734
  if (*input_line_pointer == ',')
3735
    {
3736
      ++input_line_pointer;
3737
 
3738
      SKIP_WHITESPACE ();
3739
      if (*input_line_pointer == '\n')
3740
        {
3741
          as_bad (_("missing alignment"));
3742
          ignore_rest_of_line ();
3743
          return;
3744
        }
3745
 
3746
      align = (int) get_absolute_expression ();
3747
 
3748
#ifndef OBJ_ELF
3749
      if (align > max_alignment)
3750
        {
3751
          align = max_alignment;
3752
          as_warn (_("alignment too large; assuming %d"), align);
3753
        }
3754
#endif
3755
 
3756
      if (align < 0)
3757
        {
3758
          as_bad (_("negative alignment"));
3759
          ignore_rest_of_line ();
3760
          return;
3761
        }
3762
 
3763
      if (align != 0)
3764
        {
3765
          temp = mylog2 (align);
3766
          if (temp < 0)
3767
            {
3768
              as_bad (_("alignment not a power of 2"));
3769
              ignore_rest_of_line ();
3770
              return;
3771
            }
3772
 
3773
          align = temp;
3774
        }
3775
 
3776
      record_alignment (bss_section, align);
3777
    }
3778
  else
3779
    align = 0;
3780
 
3781
  if (!S_IS_DEFINED (symbolP)
3782
#ifdef OBJ_AOUT
3783
      && S_GET_OTHER (symbolP) == 0
3784
      && S_GET_DESC (symbolP) == 0
3785
#endif
3786
      )
3787
    {
3788
      if (! need_pass_2)
3789
        {
3790
          char *pfrag;
3791
          segT current_seg = now_seg;
3792
          subsegT current_subseg = now_subseg;
3793
 
3794
          /* Switch to bss.  */
3795
          subseg_set (bss_section, 1);
3796
 
3797
          if (align)
3798
            /* Do alignment.  */
3799
            frag_align (align, 0, 0);
3800
 
3801
          /* Detach from old frag.  */
3802
          if (S_GET_SEGMENT (symbolP) == bss_section)
3803
            symbol_get_frag (symbolP)->fr_symbol = NULL;
3804
 
3805
          symbol_set_frag (symbolP, frag_now);
3806
          pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3807
                            (offsetT) size, (char *) 0);
3808
          *pfrag = 0;
3809
 
3810
          S_SET_SEGMENT (symbolP, bss_section);
3811
 
3812
          subseg_set (current_seg, current_subseg);
3813
 
3814
#ifdef OBJ_ELF
3815
          S_SET_SIZE (symbolP, size);
3816
#endif
3817
        }
3818
    }
3819
  else
3820
    {
3821
      as_warn ("Ignoring attempt to re-define symbol %s",
3822
               S_GET_NAME (symbolP));
3823
    }                           /* if not redefining.  */
3824
 
3825
  demand_empty_rest_of_line ();
3826
}
3827
 
3828
static void
3829
s_common (ignore)
3830
     int ignore ATTRIBUTE_UNUSED;
3831
{
3832
  char *name;
3833
  char c;
3834
  char *p;
3835
  offsetT temp, size;
3836
  symbolS *symbolP;
3837
 
3838
  name = input_line_pointer;
3839
  c = get_symbol_end ();
3840
  /* Just after name is now '\0'.  */
3841
  p = input_line_pointer;
3842
  *p = c;
3843
  SKIP_WHITESPACE ();
3844
  if (*input_line_pointer != ',')
3845
    {
3846
      as_bad (_("Expected comma after symbol-name"));
3847
      ignore_rest_of_line ();
3848
      return;
3849
    }
3850
 
3851
  /* Skip ','.  */
3852
  input_line_pointer++;
3853
 
3854
  if ((temp = get_absolute_expression ()) < 0)
3855
    {
3856
      as_bad (_(".COMMon length (%lu) out of range ignored"),
3857
              (unsigned long) temp);
3858
      ignore_rest_of_line ();
3859
      return;
3860
    }
3861
  size = temp;
3862
  *p = 0;
3863
  symbolP = symbol_find_or_make (name);
3864
  *p = c;
3865
  if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3866
    {
3867
      as_bad (_("Ignoring attempt to re-define symbol"));
3868
      ignore_rest_of_line ();
3869
      return;
3870
    }
3871
  if (S_GET_VALUE (symbolP) != 0)
3872
    {
3873
      if (S_GET_VALUE (symbolP) != (valueT) size)
3874
        {
3875
          as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3876
                   S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
3877
        }
3878
    }
3879
  else
3880
    {
3881
#ifndef OBJ_ELF
3882
      S_SET_VALUE (symbolP, (valueT) size);
3883
      S_SET_EXTERNAL (symbolP);
3884
#endif
3885
    }
3886
  know (symbol_get_frag (symbolP) == &zero_address_frag);
3887
  if (*input_line_pointer != ',')
3888
    {
3889
      as_bad (_("Expected comma after common length"));
3890
      ignore_rest_of_line ();
3891
      return;
3892
    }
3893
  input_line_pointer++;
3894
  SKIP_WHITESPACE ();
3895
  if (*input_line_pointer != '"')
3896
    {
3897
      temp = get_absolute_expression ();
3898
 
3899
#ifndef OBJ_ELF
3900
      if (temp > max_alignment)
3901
        {
3902
          temp = max_alignment;
3903
          as_warn (_("alignment too large; assuming %ld"), (long) temp);
3904
        }
3905
#endif
3906
 
3907
      if (temp < 0)
3908
        {
3909
          as_bad (_("negative alignment"));
3910
          ignore_rest_of_line ();
3911
          return;
3912
        }
3913
 
3914
#ifdef OBJ_ELF
3915
      if (symbol_get_obj (symbolP)->local)
3916
        {
3917
          segT old_sec;
3918
          int old_subsec;
3919
          char *p;
3920
          int align;
3921
 
3922
          old_sec = now_seg;
3923
          old_subsec = now_subseg;
3924
 
3925
          if (temp == 0)
3926
            align = 0;
3927
          else
3928
            align = mylog2 (temp);
3929
 
3930
          if (align < 0)
3931
            {
3932
              as_bad (_("alignment not a power of 2"));
3933
              ignore_rest_of_line ();
3934
              return;
3935
            }
3936
 
3937
          record_alignment (bss_section, align);
3938
          subseg_set (bss_section, 0);
3939
          if (align)
3940
            frag_align (align, 0, 0);
3941
          if (S_GET_SEGMENT (symbolP) == bss_section)
3942
            symbol_get_frag (symbolP)->fr_symbol = 0;
3943
          symbol_set_frag (symbolP, frag_now);
3944
          p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3945
                        (offsetT) size, (char *) 0);
3946
          *p = 0;
3947
          S_SET_SEGMENT (symbolP, bss_section);
3948
          S_CLEAR_EXTERNAL (symbolP);
3949
          S_SET_SIZE (symbolP, size);
3950
          subseg_set (old_sec, old_subsec);
3951
        }
3952
      else
3953
#endif /* OBJ_ELF  */
3954
        {
3955
        allocate_common:
3956
          S_SET_VALUE (symbolP, (valueT) size);
3957
#ifdef OBJ_ELF
3958
          S_SET_ALIGN (symbolP, temp);
3959
          S_SET_SIZE (symbolP, size);
3960
#endif
3961
          S_SET_EXTERNAL (symbolP);
3962
          S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3963
        }
3964
    }
3965
  else
3966
    {
3967
      input_line_pointer++;
3968
      /* @@ Some use the dot, some don't.  Can we get some consistency??  */
3969
      if (*input_line_pointer == '.')
3970
        input_line_pointer++;
3971
      /* @@ Some say data, some say bss.  */
3972
      if (strncmp (input_line_pointer, "bss\"", 4)
3973
          && strncmp (input_line_pointer, "data\"", 5))
3974
        {
3975
          while (*--input_line_pointer != '"')
3976
            ;
3977
          input_line_pointer--;
3978
          goto bad_common_segment;
3979
        }
3980
      while (*input_line_pointer++ != '"')
3981
        ;
3982
      goto allocate_common;
3983
    }
3984
 
3985
  symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
3986
 
3987
  demand_empty_rest_of_line ();
3988
  return;
3989
 
3990
  {
3991
  bad_common_segment:
3992
    p = input_line_pointer;
3993
    while (*p && *p != '\n')
3994
      p++;
3995
    c = *p;
3996
    *p = '\0';
3997
    as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3998
    *p = c;
3999
    input_line_pointer = p;
4000
    ignore_rest_of_line ();
4001
    return;
4002
  }
4003
}
4004
 
4005
/* Handle the .empty pseudo-op.  This suppresses the warnings about
4006
   invalid delay slot usage.  */
4007
 
4008
static void
4009
s_empty (ignore)
4010
     int ignore ATTRIBUTE_UNUSED;
4011
{
4012
  /* The easy way to implement is to just forget about the last
4013
     instruction.  */
4014
  last_insn = NULL;
4015
}
4016
 
4017
static void
4018
s_seg (ignore)
4019
     int ignore ATTRIBUTE_UNUSED;
4020
{
4021
 
4022
  if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4023
    {
4024
      input_line_pointer += 6;
4025
      s_text (0);
4026
      return;
4027
    }
4028
  if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4029
    {
4030
      input_line_pointer += 6;
4031
      s_data (0);
4032
      return;
4033
    }
4034
  if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4035
    {
4036
      input_line_pointer += 7;
4037
      s_data1 ();
4038
      return;
4039
    }
4040
  if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4041
    {
4042
      input_line_pointer += 5;
4043
      /* We only support 2 segments -- text and data -- for now, so
4044
         things in the "bss segment" will have to go into data for now.
4045
         You can still allocate SEG_BSS stuff with .lcomm or .reserve.  */
4046
      subseg_set (data_section, 255);   /* FIXME-SOMEDAY.  */
4047
      return;
4048
    }
4049
  as_bad (_("Unknown segment type"));
4050
  demand_empty_rest_of_line ();
4051
}
4052
 
4053
static void
4054
s_data1 ()
4055
{
4056
  subseg_set (data_section, 1);
4057
  demand_empty_rest_of_line ();
4058
}
4059
 
4060
static void
4061
s_proc (ignore)
4062
     int ignore ATTRIBUTE_UNUSED;
4063
{
4064
  while (!is_end_of_line[(unsigned char) *input_line_pointer])
4065
    {
4066
      ++input_line_pointer;
4067
    }
4068
  ++input_line_pointer;
4069
}
4070
 
4071
/* This static variable is set by s_uacons to tell sparc_cons_align
4072
   that the expression does not need to be aligned.  */
4073
 
4074
static int sparc_no_align_cons = 0;
4075
 
4076
/* This static variable is set by sparc_cons to emit requested types
4077
   of relocations in cons_fix_new_sparc.  */
4078
 
4079
static const char *sparc_cons_special_reloc;
4080
 
4081
/* This handles the unaligned space allocation pseudo-ops, such as
4082
   .uaword.  .uaword is just like .word, but the value does not need
4083
   to be aligned.  */
4084
 
4085
static void
4086
s_uacons (bytes)
4087
     int bytes;
4088
{
4089
  /* Tell sparc_cons_align not to align this value.  */
4090
  sparc_no_align_cons = 1;
4091
  cons (bytes);
4092
  sparc_no_align_cons = 0;
4093
}
4094
 
4095
/* This handles the native word allocation pseudo-op .nword.
4096
   For sparc_arch_size 32 it is equivalent to .word,  for
4097
   sparc_arch_size 64 it is equivalent to .xword.  */
4098
 
4099
static void
4100
s_ncons (bytes)
4101
     int bytes ATTRIBUTE_UNUSED;
4102
{
4103
  cons (sparc_arch_size == 32 ? 4 : 8);
4104
}
4105
 
4106
#ifdef OBJ_ELF
4107
/* Handle the SPARC ELF .register pseudo-op.  This sets the binding of a
4108
   global register.
4109
   The syntax is:
4110
 
4111
   .register %g[2367],{#scratch|symbolname|#ignore}
4112
*/
4113
 
4114
static void
4115
s_register (ignore)
4116
     int ignore ATTRIBUTE_UNUSED;
4117
{
4118
  char c;
4119
  int reg;
4120
  int flags;
4121
  const char *regname;
4122
 
4123
  if (input_line_pointer[0] != '%'
4124
      || input_line_pointer[1] != 'g'
4125
      || ((input_line_pointer[2] & ~1) != '2'
4126
          && (input_line_pointer[2] & ~1) != '6')
4127
      || input_line_pointer[3] != ',')
4128
    as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4129
  reg = input_line_pointer[2] - '0';
4130
  input_line_pointer += 4;
4131
 
4132
  if (*input_line_pointer == '#')
4133
    {
4134
      ++input_line_pointer;
4135
      regname = input_line_pointer;
4136
      c = get_symbol_end ();
4137
      if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4138
        as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4139
      if (regname[0] == 'i')
4140
        regname = NULL;
4141
      else
4142
        regname = "";
4143
    }
4144
  else
4145
    {
4146
      regname = input_line_pointer;
4147
      c = get_symbol_end ();
4148
    }
4149
  if (sparc_arch_size == 64)
4150
    {
4151
      if (globals[reg])
4152
        {
4153
          if ((regname && globals[reg] != (symbolS *) 1
4154
               && strcmp (S_GET_NAME (globals[reg]), regname))
4155
              || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4156
            as_bad (_("redefinition of global register"));
4157
        }
4158
      else
4159
        {
4160
          if (regname == NULL)
4161
            globals[reg] = (symbolS *) 1;
4162
          else
4163
            {
4164
              if (*regname)
4165
                {
4166
                  if (symbol_find (regname))
4167
                    as_bad (_("Register symbol %s already defined."),
4168
                            regname);
4169
                }
4170
              globals[reg] = symbol_make (regname);
4171
              flags = symbol_get_bfdsym (globals[reg])->flags;
4172
              if (! *regname)
4173
                flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4174
              if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4175
                flags |= BSF_GLOBAL;
4176
              symbol_get_bfdsym (globals[reg])->flags = flags;
4177
              S_SET_VALUE (globals[reg], (valueT) reg);
4178
              S_SET_ALIGN (globals[reg], reg);
4179
              S_SET_SIZE (globals[reg], 0);
4180
              /* Although we actually want undefined_section here,
4181
                 we have to use absolute_section, because otherwise
4182
                 generic as code will make it a COM section.
4183
                 We fix this up in sparc_adjust_symtab.  */
4184
              S_SET_SEGMENT (globals[reg], absolute_section);
4185
              S_SET_OTHER (globals[reg], 0);
4186
              elf_symbol (symbol_get_bfdsym (globals[reg]))
4187
                ->internal_elf_sym.st_info =
4188
                  ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4189
              elf_symbol (symbol_get_bfdsym (globals[reg]))
4190
                ->internal_elf_sym.st_shndx = SHN_UNDEF;
4191
            }
4192
        }
4193
    }
4194
 
4195
  *input_line_pointer = c;
4196
 
4197
  demand_empty_rest_of_line ();
4198
}
4199
 
4200
/* Adjust the symbol table.  We set undefined sections for STT_REGISTER
4201
   symbols which need it.  */
4202
 
4203
void
4204
sparc_adjust_symtab ()
4205
{
4206
  symbolS *sym;
4207
 
4208
  for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4209
    {
4210
      if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4211
                       ->internal_elf_sym.st_info) != STT_REGISTER)
4212
        continue;
4213
 
4214
      if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4215
                       ->internal_elf_sym.st_shndx != SHN_UNDEF))
4216
        continue;
4217
 
4218
      S_SET_SEGMENT (sym, undefined_section);
4219
    }
4220
}
4221
#endif
4222
 
4223
/* If the --enforce-aligned-data option is used, we require .word,
4224
   et. al., to be aligned correctly.  We do it by setting up an
4225
   rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4226
   no unexpected alignment was introduced.
4227
 
4228
   The SunOS and Solaris native assemblers enforce aligned data by
4229
   default.  We don't want to do that, because gcc can deliberately
4230
   generate misaligned data if the packed attribute is used.  Instead,
4231
   we permit misaligned data by default, and permit the user to set an
4232
   option to check for it.  */
4233
 
4234
void
4235
sparc_cons_align (nbytes)
4236
     int nbytes;
4237
{
4238
  int nalign;
4239
  char *p;
4240
 
4241
  /* Only do this if we are enforcing aligned data.  */
4242
  if (! enforce_aligned_data)
4243
    return;
4244
 
4245
  /* Don't align if this is an unaligned pseudo-op.  */
4246
  if (sparc_no_align_cons)
4247
    return;
4248
 
4249
  nalign = mylog2 (nbytes);
4250
  if (nalign == 0)
4251
    return;
4252
 
4253
  assert (nalign > 0);
4254
 
4255
  if (now_seg == absolute_section)
4256
    {
4257
      if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4258
        as_bad (_("misaligned data"));
4259
      return;
4260
    }
4261
 
4262
  p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4263
                (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4264
 
4265
  record_alignment (now_seg, nalign);
4266
}
4267
 
4268
/* This is called from HANDLE_ALIGN in tc-sparc.h.  */
4269
 
4270
void
4271
sparc_handle_align (fragp)
4272
     fragS *fragp;
4273
{
4274
  int count, fix;
4275
  char *p;
4276
 
4277
  count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4278
 
4279
  switch (fragp->fr_type)
4280
    {
4281
    case rs_align_test:
4282
      if (count != 0)
4283
        as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4284
      break;
4285
 
4286
    case rs_align_code:
4287
      p = fragp->fr_literal + fragp->fr_fix;
4288
      fix = 0;
4289
 
4290
      if (count & 3)
4291
        {
4292
          fix = count & 3;
4293
          memset (p, 0, fix);
4294
          p += fix;
4295
          count -= fix;
4296
        }
4297
 
4298
      if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4299
        {
4300
          unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f  */
4301
          if (INSN_BIG_ENDIAN)
4302
            number_to_chars_bigendian (p, wval, 4);
4303
          else
4304
            number_to_chars_littleendian (p, wval, 4);
4305
          p += 4;
4306
          count -= 4;
4307
          fix += 4;
4308
        }
4309
 
4310
      if (INSN_BIG_ENDIAN)
4311
        number_to_chars_bigendian (p, 0x01000000, 4);
4312
      else
4313
        number_to_chars_littleendian (p, 0x01000000, 4);
4314
 
4315
      fragp->fr_fix += fix;
4316
      fragp->fr_var = 4;
4317
      break;
4318
 
4319
    default:
4320
      break;
4321
    }
4322
}
4323
 
4324
#ifdef OBJ_ELF
4325
/* Some special processing for a Sparc ELF file.  */
4326
 
4327
void
4328
sparc_elf_final_processing ()
4329
{
4330
  /* Set the Sparc ELF flag bits.  FIXME: There should probably be some
4331
     sort of BFD interface for this.  */
4332
  if (sparc_arch_size == 64)
4333
    {
4334
      switch (sparc_memory_model)
4335
        {
4336
        case MM_RMO:
4337
          elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4338
          break;
4339
        case MM_PSO:
4340
          elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4341
          break;
4342
        default:
4343
          break;
4344
        }
4345
    }
4346
  else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4347
    elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4348
  if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4349
    elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4350
  else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4351
    elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4352
}
4353
 
4354
void
4355
sparc_cons (exp, size)
4356
     expressionS *exp;
4357
     int size;
4358
{
4359
  char *save;
4360
 
4361
  SKIP_WHITESPACE ();
4362
  sparc_cons_special_reloc = NULL;
4363
  save = input_line_pointer;
4364
  if (input_line_pointer[0] == '%'
4365
      && input_line_pointer[1] == 'r'
4366
      && input_line_pointer[2] == '_')
4367
    {
4368
      if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4369
        {
4370
          input_line_pointer += 7;
4371
          sparc_cons_special_reloc = "disp";
4372
        }
4373
      else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4374
        {
4375
          if (size != 4 && size != 8)
4376
            as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4377
          else
4378
            {
4379
              input_line_pointer += 6;
4380
              sparc_cons_special_reloc = "plt";
4381
            }
4382
        }
4383
      else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4384
        {
4385
          if (size != 4 && size != 8)
4386
            as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4387
          else
4388
            {
4389
              input_line_pointer += 13;
4390
              sparc_cons_special_reloc = "tls_dtpoff";
4391
            }
4392
        }
4393
      if (sparc_cons_special_reloc)
4394
        {
4395
          int bad = 0;
4396
 
4397
          switch (size)
4398
            {
4399
            case 1:
4400
              if (*input_line_pointer != '8')
4401
                bad = 1;
4402
              input_line_pointer--;
4403
              break;
4404
            case 2:
4405
              if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4406
                bad = 1;
4407
              break;
4408
            case 4:
4409
              if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4410
                bad = 1;
4411
              break;
4412
            case 8:
4413
              if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4414
                bad = 1;
4415
              break;
4416
            default:
4417
              bad = 1;
4418
              break;
4419
            }
4420
 
4421
          if (bad)
4422
            {
4423
              as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4424
                      sparc_cons_special_reloc, size * 8, size);
4425
            }
4426
          else
4427
            {
4428
              input_line_pointer += 2;
4429
              if (*input_line_pointer != '(')
4430
                {
4431
                  as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4432
                          sparc_cons_special_reloc, size * 8);
4433
                  bad = 1;
4434
                }
4435
            }
4436
 
4437
          if (bad)
4438
            {
4439
              input_line_pointer = save;
4440
              sparc_cons_special_reloc = NULL;
4441
            }
4442
          else
4443
            {
4444
              int c;
4445
              char *end = ++input_line_pointer;
4446
              int npar = 0;
4447
 
4448
              while (! is_end_of_line[(c = *end)])
4449
                {
4450
                  if (c == '(')
4451
                    npar++;
4452
                  else if (c == ')')
4453
                    {
4454
                      if (!npar)
4455
                        break;
4456
                      npar--;
4457
                    }
4458
                  end++;
4459
                }
4460
 
4461
              if (c != ')')
4462
                as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4463
                        sparc_cons_special_reloc, size * 8);
4464
              else
4465
                {
4466
                  *end = '\0';
4467
                  expression (exp);
4468
                  *end = c;
4469
                  if (input_line_pointer != end)
4470
                    {
4471
                      as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4472
                              sparc_cons_special_reloc, size * 8);
4473
                    }
4474
                  else
4475
                    {
4476
                      input_line_pointer++;
4477
                      SKIP_WHITESPACE ();
4478
                      c = *input_line_pointer;
4479
                      if (! is_end_of_line[c] && c != ',')
4480
                        as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4481
                                sparc_cons_special_reloc, size * 8);
4482
                    }
4483
                }
4484
            }
4485
        }
4486
    }
4487
  if (sparc_cons_special_reloc == NULL)
4488
    expression (exp);
4489
}
4490
 
4491
#endif
4492
 
4493
/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4494
   reloc for a cons.  We could use the definition there, except that
4495
   we want to handle little endian relocs specially.  */
4496
 
4497
void
4498
cons_fix_new_sparc (frag, where, nbytes, exp)
4499
     fragS *frag;
4500
     int where;
4501
     unsigned int nbytes;
4502
     expressionS *exp;
4503
{
4504
  bfd_reloc_code_real_type r;
4505
 
4506
  r = (nbytes == 1 ? BFD_RELOC_8 :
4507
       (nbytes == 2 ? BFD_RELOC_16 :
4508
        (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4509
 
4510
  if (target_little_endian_data
4511
      && nbytes == 4
4512
      && now_seg->flags & SEC_ALLOC)
4513
    r = BFD_RELOC_SPARC_REV32;
4514
 
4515
  if (sparc_cons_special_reloc)
4516
    {
4517
      if (*sparc_cons_special_reloc == 'd')
4518
        switch (nbytes)
4519
          {
4520
          case 1: r = BFD_RELOC_8_PCREL; break;
4521
          case 2: r = BFD_RELOC_16_PCREL; break;
4522
          case 4: r = BFD_RELOC_32_PCREL; break;
4523
          case 8: r = BFD_RELOC_64_PCREL; break;
4524
          default: abort ();
4525
          }
4526
      else if (*sparc_cons_special_reloc == 'p')
4527
        switch (nbytes)
4528
          {
4529
          case 4: r = BFD_RELOC_SPARC_PLT32; break;
4530
          case 8: r = BFD_RELOC_SPARC_PLT64; break;
4531
          }
4532
      else
4533
        switch (nbytes)
4534
          {
4535
          case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4536
          case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4537
          }
4538
    }
4539
  else if (sparc_no_align_cons)
4540
    {
4541
      switch (nbytes)
4542
        {
4543
        case 2: r = BFD_RELOC_SPARC_UA16; break;
4544
        case 4: r = BFD_RELOC_SPARC_UA32; break;
4545
        case 8: r = BFD_RELOC_SPARC_UA64; break;
4546
        default: abort ();
4547
        }
4548
   }
4549
 
4550
  fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4551
  sparc_cons_special_reloc = NULL;
4552
}
4553
 
4554
void
4555
sparc_cfi_frame_initial_instructions ()
4556
{
4557
  cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4558
}
4559
 
4560
int
4561
sparc_regname_to_dw2regnum (char *regname)
4562
{
4563
  char *p, *q;
4564
 
4565
  if (!regname[0])
4566
    return -1;
4567
 
4568
  q = "goli";
4569
  p = strchr (q, regname[0]);
4570
  if (p)
4571
    {
4572
      if (regname[1] < '0' || regname[1] > '8' || regname[2])
4573
        return -1;
4574
      return (p - q) * 8 + regname[1] - '0';
4575
    }
4576
  if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4577
    return 14;
4578
  if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4579
    return 30;
4580
  if (regname[0] == 'f' || regname[0] == 'r')
4581
    {
4582
      unsigned int regnum;
4583
 
4584
      regnum = strtoul (regname + 1, &q, 10);
4585
      if (p == q || *q)
4586
        return -1;
4587
      if (regnum >= ((regname[0] == 'f'
4588
                      && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4589
                     ? 64 : 32))
4590
        return -1;
4591
      if (regname[0] == 'f')
4592
        {
4593
          regnum += 32;
4594
          if (regnum >= 64 && (regnum & 1))
4595
            return -1;
4596
        }
4597
      return regnum;
4598
    }
4599
  return -1;
4600
}
4601
 
4602
void
4603
sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4604
{
4605
  sparc_cons_special_reloc = "disp";
4606
  sparc_no_align_cons = 1;
4607
  emit_expr (exp, nbytes);
4608
  sparc_no_align_cons = 0;
4609
  sparc_cons_special_reloc = NULL;
4610
}

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