OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [arm/] [arch6zk.s] - Blame information for rev 832

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
.text
2
.align 0
3
 
4
label:
5
        # ARMV6K instructions
6
        clrex
7
        ldrexb          r4, [r12]
8
        ldrexbne        r12, [r4]
9
        ldrexd          r4, [r12]
10
        ldrexdne        r12, [r4]
11
        ldrexh          r4, [r12]
12
        ldrexhne        r12, [r4]
13
        nop             {128}
14
        nopne           {127}
15
        sev
16
        strexb          r4, r12, [r7]
17
        strexbne        r12, r4, [r8]
18
        strexd          r4, r12, [r7]
19
        strexdne        r12, r4, [r8]
20
        strexh          r4, r12, [r7]
21
        strexhne        r12, r4, [r8]
22
        wfe
23
        wfi
24
        yield
25
        # ARMV6Z instructions
26
        smc 0xec31
27
        smcne 0x13ce
28
 
29
        # Add three nop instructions to ensure that the
30
        # output is 32-byte aligned as required for arm-aout.
31
        nop
32
        nop
33
        nop

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.