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        @ Things you can't do with 16-bit Thumb instructions, but you can
        @ do with the equivalent ARM instruction.  Does not include errors
        @ caught by fixup processing (e.g. out-of-range immediates).
 
        .text
        .code 16
        .thumb_func
l:
        @ Arithmetic instruction templates
        .macro  ar2 opc
        \opc    r8,r0
        \opc    r0,r8
        .endm
        .macro  ar2sh opc
        ar2     \opc
        \opc    r0,#12
        \opc    r0,r1,lsl #2
        \opc    r0,r1,lsl r3
        .endm
        .macro  ar2r opc
        ar2     \opc
        \opc    r0,r1,ror #8
        .endm
        .macro  ar3 opc
        \opc    r1,r2,r3
        \opc    r8,r0
        \opc    r0,r8
        .endm
        .macro ar3sh opc
        ar3     \opc
        \opc    r0,#12
        \opc    r0,r1,lsl #2
        \opc    r0,r1,lsl r3
        .endm
 
        ar2sh   tst
        ar2sh   cmn
        ar2sh   mvn
        ar2     neg
        ar2     rev
        ar2     rev16
        ar2     revsh
        ar2r    sxtb
        ar2r    sxth
        ar2r    uxtb
        ar2r    uxth
 
        ar3sh   adc
        ar3sh   and
        ar3sh   bic
        ar3sh   eor
        ar3sh   orr
        ar3sh   sbc
        ar3     mul
 
        @ Shift instruction template
        .macro  shift opc
        \opc    r8,r0,#12  @ form 1
        \opc    r0,r8,#12
        ar2     \opc       @ form 2
        .endm
        shift   asr
        shift   lsl
        shift   lsr
        shift   ror
        ror     r0,r1,#12
 
        @ add/sub/mov/cmp are idiosyncratic
        add     r0,r1,lsl #2
        add     r0,r1,lsl r3
        add     r8,r0,#1        @ form 1
        add     r0,r8,#1
        add     r8,#10          @ form 2
        add     r8,r1,r2        @ form 3
        add     r1,r8,r2
        add     r1,r2,r8
        add     r8,pc,#4        @ form 5
        add     r8,sp,#4        @ form 6
 
        ar3sh   sub
        sub     r8,r0,#1        @ form 1
        sub     r0,r8,#1
        sub     r8,#10          @ form 2
        sub     r8,r1,r2        @ form 3
        sub     r1,r8,r2
        sub     r1,r2,r8
 
        cmp     r0,r1,lsl #2
        cmp     r0,r1,lsl r3
        cmp     r8,#255
 
        mov     r0,r1,lsl #2
        mov     r0,r1,lsl r3
        mov     r8,#255
 
        @ Load/store template
        .macro  ldst opc
        \opc    r8,[r0]
        \opc    r0,[r8]
        \opc    r0,[r0,r8]
        \opc    r0,[r1,#4]!
        \opc    r0,[r1],#4
        \opc    r0,[r1,-r2]
        \opc    r0,[r1],r2
        .endm
        ldst    ldr
        ldst    ldrb
        ldst    ldrh
        ldst    ldrsb
        ldst    ldrsh
        ldst    str
        ldst    strb
        ldst    strh
 
        ldr     r0,[r1,r2,lsl #1]
        str     r0,[r1,r2,lsl #1]
 
        @ Load/store multiple
        ldmia   r8!,{r1,r2}
        ldmia   r7!,{r8}
        ldmia   r7,{r1,r2}
        ldmia   r7!,{r1,r7}
 
        stmia   r8!,{r1,r2}
        stmia   r7!,{r8}
        stmia   r7,{r1,r2}
        stmia   r7!,{r1,r7}
 
        push    {r8,r9}
        pop     {r8,r9}
 
        @ Miscellaneous
        bkpt    #257
        cpsie   ai,#5
        cpsid   ai,#5
 
        @ Conditional suffixes
        addeq   r0,r1,r2
        @ low register non flag setting add.
        .syntax unified
        add     r0, r1
 

Line No.	Rev	Author	Line
1	38	julius	`@ Things you can't do with 16-bit Thumb instructions, but you can`
2			`@ do with the equivalent ARM instruction. Does not include errors`
3			`@ caught by fixup processing (e.g. out-of-range immediates).`
4
5			`.text`
6			`.code 16`
7			`.thumb_func`
8			`l:`
9			`@ Arithmetic instruction templates`
10			`.macro ar2 opc`
11			`\opc r8,r0`
12			`\opc r0,r8`
13			`.endm`
14			`.macro ar2sh opc`
15			`ar2 \opc`
16			`\opc r0,#12`
17			`\opc r0,r1,lsl #2`
18			`\opc r0,r1,lsl r3`
19			`.endm`
20			`.macro ar2r opc`
21			`ar2 \opc`
22			`\opc r0,r1,ror #8`
23			`.endm`
24			`.macro ar3 opc`
25			`\opc r1,r2,r3`
26			`\opc r8,r0`
27			`\opc r0,r8`
28			`.endm`
29			`.macro ar3sh opc`
30			`ar3 \opc`
31			`\opc r0,#12`
32			`\opc r0,r1,lsl #2`
33			`\opc r0,r1,lsl r3`
34			`.endm`
35
36			`ar2sh tst`
37			`ar2sh cmn`
38			`ar2sh mvn`
39			`ar2 neg`
40			`ar2 rev`
41			`ar2 rev16`
42			`ar2 revsh`
43			`ar2r sxtb`
44			`ar2r sxth`
45			`ar2r uxtb`
46			`ar2r uxth`
47
48			`ar3sh adc`
49			`ar3sh and`
50			`ar3sh bic`
51			`ar3sh eor`
52			`ar3sh orr`
53			`ar3sh sbc`
54			`ar3 mul`
55
56			`@ Shift instruction template`
57			`.macro shift opc`
58			`\opc r8,r0,#12 @ form 1`
59			`\opc r0,r8,#12`
60			`ar2 \opc @ form 2`
61			`.endm`
62			`shift asr`
63			`shift lsl`
64			`shift lsr`
65			`shift ror`
66			`ror r0,r1,#12`
67
68			`@ add/sub/mov/cmp are idiosyncratic`
69			`add r0,r1,lsl #2`
70			`add r0,r1,lsl r3`
71			`add r8,r0,#1 @ form 1`
72			`add r0,r8,#1`
73			`add r8,#10 @ form 2`
74			`add r8,r1,r2 @ form 3`
75			`add r1,r8,r2`
76			`add r1,r2,r8`
77			`add r8,pc,#4 @ form 5`
78			`add r8,sp,#4 @ form 6`
79
80			`ar3sh sub`
81			`sub r8,r0,#1 @ form 1`
82			`sub r0,r8,#1`
83			`sub r8,#10 @ form 2`
84			`sub r8,r1,r2 @ form 3`
85			`sub r1,r8,r2`
86			`sub r1,r2,r8`
87
88			`cmp r0,r1,lsl #2`
89			`cmp r0,r1,lsl r3`
90			`cmp r8,#255`
91
92			`mov r0,r1,lsl #2`
93			`mov r0,r1,lsl r3`
94			`mov r8,#255`
95
96			`@ Load/store template`
97			`.macro ldst opc`
98			`\opc r8,[r0]`
99			`\opc r0,[r8]`
100			`\opc r0,[r0,r8]`
101			`\opc r0,[r1,#4]!`
102			`\opc r0,[r1],#4`
103			`\opc r0,[r1,-r2]`
104			`\opc r0,[r1],r2`
105			`.endm`
106			`ldst ldr`
107			`ldst ldrb`
108			`ldst ldrh`
109			`ldst ldrsb`
110			`ldst ldrsh`
111			`ldst str`
112			`ldst strb`
113			`ldst strh`
114
115			`ldr r0,[r1,r2,lsl #1]`
116			`str r0,[r1,r2,lsl #1]`
117
118			`@ Load/store multiple`
119			`ldmia r8!,{r1,r2}`
120			`ldmia r7!,{r8}`
121			`ldmia r7,{r1,r2}`
122			`ldmia r7!,{r1,r7}`
123
124			`stmia r8!,{r1,r2}`
125			`stmia r7!,{r8}`
126			`stmia r7,{r1,r2}`
127			`stmia r7!,{r1,r7}`
128
129			`push {r8,r9}`
130			`pop {r8,r9}`
131
132			`@ Miscellaneous`
133			`bkpt #257`
134			`cpsie ai,#5`
135			`cpsid ai,#5`
136
137			`@ Conditional suffixes`
138			`addeq r0,r1,r2`
139			`@ low register non flag setting add.`
140			`.syntax unified`
141			`add r0, r1`
142

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[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [arm/] [t16-bad.s] - Blame information for rev 832