OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [bfin/] [expected_comparison_errors.l] - Blame information for rev 832

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
.*: Assembler messages:
2
.*:1: Error: AREGs are in bad order or same. Input text was A0.
3
.*:2: Error: AREGs are in bad order or same. Input text was A1.
4
.*:3: Error: AREGs are in bad order or same. Input text was A0.
5
.*:4: Error: AREGs are in bad order or same. Input text was a0.
6
.*:5: Error: AREGs are in bad order or same. Input text was a1.
7
.*:6: Error: AREGs are in bad order or same. Input text was a0.
8
.*:7: Error: AREGs are in bad order or same. Input text was a0.
9
.*:8: Error: AREGs are in bad order or same. Input text was a1.
10
.*:9: Error: AREGs are in bad order or same. Input text was a0.
11
.*:10: Error: Compare only of same register class. Input text was P0.
12
.*:11: Error: Compare only of same register class.
13
.*:12: Error: Compare only of same register class.
14
.*:13: Error: Compare only of same register class. Input text was R0.
15
.*:14: Error: Compare only of same register class.
16
.*:15: Error: Compare only of same register class.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.