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[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [bfin/] [move2.s] - Blame information for rev 816

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Line No. Rev Author Line
1 132 jeremybenn
 
2
.EXTERN MY_LABEL2;
3
.section .text;
4
 
5
//
6
//4 MOVE
7
//
8
 
9
//genreg = genreg ; /* (a) */
10
R0 = R0;
11
R1 = R1;
12
R2 = R2;
13
R3 = R3;
14
R4 = R4;
15
R5 = R5;
16
R6 = R6;
17
R7 = R7;
18
 
19
P0 = P0;
20
P1 = P1;
21
P2 = P2;
22
P3 = P3;
23
P4 = P4;
24
P5 = P5;
25
SP = SP;
26
FP = FP;
27
 
28
A0.X = A0.X;
29
A0.W = A0.W;
30
A1.X = A1.X;
31
A1.W = A1.W;
32
 
33
 
34
R0 = A1.W;
35
R1 = A1.X;
36
R2 = A0.W;
37
R3 = A0.X;
38
R4 = FP;
39
R5 = SP;
40
R6 = P5;
41
R7 = P4;
42
 
43
P0 = P3;
44
P1 = P2;
45
P2 = P1;
46
P3 = P0;
47
P4 = R7;
48
P5 = R6;
49
SP = R5;
50
FP = R4;
51
 
52
A0.X = R3;
53
A0.W = R2;
54
A1.X = R1;
55
A1.W = R0;
56
 
57
A0.X = A0.W;
58
A0.X = A1.W;
59
A0.X = A1.X;
60
 
61
A1.X = A1.W;
62
A1.X = A0.W;
63
A1.X = A0.X;
64
 
65
A0.W = A0.W;
66
A0.W = A1.W;
67
A0.W = A1.X;
68
 
69
A1.W = A1.W;
70
A1.W = A0.W;
71
A1.W = A0.X;
72
 
73
//genreg = dagreg ; /* (a) */
74
R0 = I0;
75
R1 = I1;
76
R2 = I2;
77
R3 = I3;
78
R4 = M0;
79
R5 = M1;
80
R6 = M2;
81
R7 = M3;
82
 
83
R0 = B0;
84
R1 = B1;
85
R2 = B2;
86
R3 = B3;
87
R4 = L0;
88
R5 = L1;
89
R6 = L2;
90
R7 = L3;
91
 
92
P0 = I0;
93
P1 = I1;
94
P2 = I2;
95
P3 = I3;
96
P4 = M0;
97
P5 = M1;
98
SP = M2;
99
FP = M3;
100
 
101
P0 = B0;
102
P1 = B1;
103
P2 = B2;
104
P3 = B3;
105
P4 = L0;
106
P5 = L1;
107
SP = L2;
108
FP = L3;
109
 
110
 
111
A0.X = I0;
112
A0.W = I1;
113
A1.X = I2;
114
A1.W = I3;
115
 
116
A0.X = M0;
117
A0.W = M1;
118
A1.X = M2;
119
A1.W = M3;
120
 
121
A0.X = B0;
122
A0.W = B1;
123
A1.X = B2;
124
A1.W = B3;
125
 
126
A0.X = L0;
127
A0.W = L1;
128
A1.X = L2;
129
A1.W = L3;
130
 
131
//dagreg = genreg ; /* (a) */
132
I0 = R0;
133
I1 = P0;
134
I2 = SP;
135
I3 = FP;
136
I0 = A0.X;
137
I1 = A0.W;
138
I2 = A1.X;
139
I3 = A1.W;
140
 
141
M0 = R0;
142
M1 = P0;
143
M2 = SP;
144
M3 = FP;
145
M0 = A0.X;
146
M1 = A0.W;
147
M2 = A1.X;
148
M3 = A1.W;
149
 
150
B0 = R0;
151
B1 = P0;
152
B2 = SP;
153
B3 = FP;
154
B0 = A0.X;
155
B1 = A0.W;
156
B2 = A1.X;
157
B3 = A1.W;
158
 
159
L0 = R0;
160
L1 = P0;
161
L2 = SP;
162
L3 = FP;
163
L0 = A0.X;
164
L1 = A0.W;
165
L2 = A1.X;
166
L3 = A1.W;
167
 
168
 
169
//dagreg = dagreg ; /* (a) */
170
 
171
I0 = I1;
172
I1 = M0;
173
I2 = B1;
174
I3 = L0;
175
 
176
M0 = I1;
177
M1 = M0;
178
M2 = B1;
179
M3 = L0;
180
 
181
B0 = I1;
182
B1 = M0;
183
B2 = B1;
184
B3 = L0;
185
 
186
L0 = I1;
187
L1 = M0;
188
L2 = B1;
189
L3 = L0;
190
 
191
//genreg = USP ; /* (a)*/
192
R1 = USP;
193
P2 = USP;
194
SP = USP;
195
FP = USP;
196
A0.X = USP;
197
A1.W = USP;
198
 
199
//USP = genreg ; /* (a)*/
200
USP = R2;
201
USP = P4;
202
USP = SP;
203
USP = FP;
204
USP = A0.X;
205
USP = A1.W;
206
 
207
//Dreg = sysreg ; /* sysreg to 32-bit D-register (a) */
208
R0 = ASTAT;
209
R1 = SEQSTAT;
210
R2 = SYSCFG;
211
R3 = RETI;
212
R4 = RETX;
213
R5 = RETN;
214
R6 = RETE;
215
R7 = RETS;
216
R0 = LC0;
217
R1 = LC1;
218
R2 = LT0;
219
R3 = LT1;
220
R4 = LB0;
221
R5 = LB1;
222
R6 = CYCLES;
223
R7 = CYCLES2;
224
//R0 = EMUDAT; 
225
//sysreg = Dreg ; /* 32-bit D-register to sysreg (a) */
226
ASTAT = R0;
227
SEQSTAT = R1;
228
SYSCFG = R3;
229
RETI = R4;
230
RETX =R5;
231
RETN = R6;
232
RETE = R7;
233
RETS = R0;
234
LC0 = R1;
235
LC1 = R2;
236
LT0 = R3;
237
LT1 = R4;
238
LB0 = R5;
239
LB1 = R6;
240
CYCLES = R7;
241
CYCLES2 = R0;
242
//EMUDAT = R1; 
243
//sysreg = Preg ; /* 32-bit P-register to sysreg (a) */
244
ASTAT = P0;
245
SEQSTAT = P1;
246
SYSCFG = P3;
247
RETI = P4;
248
RETX =P5;
249
RETN = SP;
250
RETE = FP;
251
RETS = P0;
252
LC0 = P1;
253
LC1 = P2;
254
LT0 = P3;
255
LT1 = P4;
256
LB0 = P5;
257
LB1 = SP;
258
CYCLES = SP;
259
CYCLES2 = P0;
260
//EMUDAT = P1; 
261
 
262
 
263
//sysreg = USP ; /* (a) */
264
//ASTAT = USP;
265
//SEQSTAT = USP;
266
//SYSCFG = USP;
267
//RETI = USP;
268
//RETX =USP;
269
//RETN = USP;
270
//RETE = USP;
271
//RETS = USP;
272
//LC0 = USP;
273
//LC1 = USP;
274
//LT0 = USP;
275
//LT1 = USP;
276
//LB0 = USP;
277
//LB1 = USP;
278
//CYCLES = USP;
279
//CYCLES2 = USP;
280
//EMUDAT = USP; 
281
 
282
A0 = A1 ; /* move 40-bit Accumulator value (b) */
283
 
284
A1 = A0 ; /* move 40-bit Accumulator value (b) */
285
 
286
//A0 = Dreg ; /* 32-bit D-register to 40-bit A0, sign extended (b)*/
287
A0 = R0;
288
A0 = R1;
289
A0 = R2;
290
 
291
//A1 = Dreg ; /* 32-bit D-register to 40-bit A1, sign extended (b)*/
292
 
293
A1 = R0;
294
A1 = R1;
295
A1 = R2;
296
//Dreg_even = A0 (opt_mode) ; /* move 32-bit A0.W to even Dreg (b) */
297
R0 = A0;
298
R2 = A0(FU);
299
R4 = A0(ISS2);
300
 
301
//Dreg_odd = A1 (opt_mode) ; /* move 32-bit A1.W to odd Dreg (b) */
302
R1 = A1;
303
R3 = A1(FU);
304
R5 = A1(ISS2);
305
 
306
//Dreg_even = A0, Dreg_odd = A1 (opt_mode) ; /* move both Accumulators to a register pair (b) */
307
R0 = A0, R1 = A1;
308
R0 = A0, R1 = A1(FU);
309
R6 = A0, R7 = A1(ISS2);
310
 
311
 
312
//Dreg_odd = A1, Dreg_even = A0 (opt_mode) ; /* move both Accumulators to a register pair (b) */
313
R1 = A1, R0 = A0;
314
R3 = A1, R2 = A0(FU);
315
R5 = A1, R4 = A0(ISS2);
316
 
317
//IF CC DPreg = DPreg ; /* move if CC = 1 (a) */
318
 
319
IF CC R3 = R0;
320
IF CC R2 = R0;
321
IF CC R7 = R0;
322
 
323
IF CC R2 = P2;
324
IF CC R4 = P1;
325
IF CC R0 = P0;
326
IF CC R7 = P4;
327
 
328
IF CC P0 = P2;
329
IF CC P4 = P5;
330
IF CC P1 = P3;
331
IF CC P5 = P4;
332
 
333
IF CC P0 = R2;
334
IF CC P4 = R3;
335
IF CC P5 = R7;
336
IF CC P2 = R6;
337
 
338
//IF ! CC DPreg = DPreg ; /* move if CC = 0 (a) */
339
IF !CC R3 = R0;
340
IF !CC R2 = R0;
341
IF !CC R7 = R0;
342
 
343
IF !CC R2 = P2;
344
IF !CC R4 = P1;
345
IF !CC R0 = P0;
346
IF !CC R7 = P4;
347
 
348
IF !CC P0 = P2;
349
IF !CC P4 = P5;
350
IF !CC P1 = P3;
351
IF !CC P5 = P4;
352
 
353
IF !CC P0 = R2;
354
IF !CC P4 = R3;
355
IF !CC P5 = R7;
356
IF !CC P2 = R6;
357
 
358
//Dreg = Dreg_lo (Z) ; /* (a) */
359
 
360
R0 = R0.L(Z);
361
R2 = R1.L(Z);
362
R1 = R2.L(Z);
363
R7 = R6.L(Z);
364
 
365
//Dreg = Dreg_lo (X) ; /* (a)*/
366
R0 = R0.L(X);
367
R2 = R1.L(X);
368
R1 = R2.L(X);
369
R7 = R6.L(X);
370
 
371
R0 = R0.L;
372
R2 = R1.L;
373
R1 = R2.L;
374
R7 = R6.L;
375
 
376
//A0.X = Dreg_lo ; /* least significant 8 bits of Dreg into A0.X (b) */
377
A0.X = R0.L;
378
A0.X = R1.L;
379
 
380
//A1.X = Dreg_lo ; /* least significant 8 bits of Dreg into A1.X (b) */
381
A1.X = R0.L;
382
A1.X = R1.L;
383
 
384
//Dreg_lo = A0.X ; /* 8-bit A0.X, sign-extended, into least significant 16 bits of Dreg (b) */
385
R0.L = A0.X;
386
R1.L = A0.X;
387
R7.L = A0.X;
388
 
389
//Dreg_lo = A1.X ; /* 8-bit A1.X, sign-extended, into least significant 16 bits of Dreg (b) */
390
R0.L = A1.X;
391
R1.L = A1.X;
392
R7.L = A1.X;
393
 
394
//A0.L = Dreg_lo ; /* least significant 16 bits of Dreg into least significant 16 bits of A0.W (b) */
395
A0.L = R0.L;
396
A0.L = R1.L;
397
A0.L = R6.L;
398
 
399
//A1.L = Dreg_lo ; /* least significant 16 bits of Dreg into least significant 16 bits of A1.W (b) */
400
A1.L = R0.L;
401
A1.L = R1.L;
402
A1.L = R6.L;
403
 
404
//A0.H = Dreg_hi ; /* most significant 16 bits of Dreg into most significant 16 bits of A0.W (b) */
405
A0.H = R0.H;
406
A0.H = R1.H;
407
A0.H = R6.H;
408
//A1.H = Dreg_hi ; /* most significant 16 bits of Dreg into most significant 16 bits of A1.W (b) */
409
A1.H = R0.H;
410
A1.H = R1.H;
411
A1.H = R6.H;
412
 
413
//Dreg_lo = A0 (opt_mode) ; /* move A0 to lower half of Dreg (b) */
414
R0.L = A0;
415
R1.L = A0;
416
 
417
R0.L = A0(FU);
418
R1.L = A0(FU);
419
 
420
R0.L = A0(IS);
421
R1.L = A0(IS);
422
 
423
R0.L = A0(IU);
424
R1.L = A0(IU);
425
 
426
R0.L = A0(T);
427
R1.L = A0(T);
428
 
429
R0.L = A0(S2RND);
430
R1.L = A0(S2RND);
431
 
432
R0.L = A0(ISS2);
433
R1.L = A0(ISS2);
434
 
435
R0.L = A0(IH);
436
R1.L = A0(IH);
437
 
438
//Dreg_hi = A1 (opt_mode) ; /* move A1 to upper half of Dreg (b) */
439
R0.H = A1;
440
R1.H = A1;
441
 
442
R0.H = A1(FU);
443
R1.H = A1(FU);
444
 
445
R0.H = A1(IS);
446
R1.H = A1(IS);
447
 
448
R0.H = A1(IU);
449
R1.H = A1(IU);
450
 
451
R0.H = A1(T);
452
R1.H = A1(T);
453
 
454
R0.H = A1(S2RND);
455
R1.H = A1(S2RND);
456
 
457
R0.H = A1(ISS2);
458
R1.H = A1(ISS2);
459
 
460
R0.H = A1(IH);
461
R1.H = A1(IH);
462
 
463
 
464
//Dreg_lo = A0, Dreg_hi = A1 (opt_mode) ; /* move both values at once; must go to the lower and upper halves of the same Dreg (b)*/
465
 
466
R0.L = A0, R0.H = A1; 
467
R1.L = A0, R1.H = A1; 
468
 
469
R0.L = A0, R0.H = A1(FU); 
470
R1.L = A0, R1.H = A1(FU);
471
 
472
R0.L = A0, R0.H = A1(IS); 
473
R1.L = A0, R1.H = A1(IS);
474
 
475
R0.L = A0, R0.H = A1(IU); 
476
R1.L = A0, R1.H = A1(IU);
477
 
478
R0.L = A0, R0.H = A1(T); 
479
R1.L = A0, R1.H = A1(T);
480
 
481
R0.L = A0, R0.H = A1(S2RND); 
482
R1.L = A0, R1.H = A1(S2RND);
483
 
484
R0.L = A0, R0.H = A1(ISS2); 
485
R1.L = A0, R1.H = A1(ISS2);
486
 
487
R0.L = A0, R0.H = A1(IH); 
488
R1.L = A0, R1.H = A1(IH);
489
 
490
//Dreg_hi = A1, Dreg_lo = AO (opt_mode) ; /* move both values at once; must go to the upper and lower halves of the same Dreg (b) */
491
 
492
R0.H = A1,R0.L = A0;  
493
R1.H = A1,R1.L = A0;  
494
 
495
R0.H = A1,R0.L = A0 (FU); 
496
R1.H = A1,R1.L = A0 (FU);
497
 
498
R0.H = A1,R0.L = A0 (IS); 
499
R1.H = A1,R1.L = A0 (IS);
500
 
501
R0.H = A1,R0.L = A0 (IU); 
502
R1.H = A1,R1.L = A0 (IU);
503
 
504
R0.H = A1,R0.L = A0 (T); 
505
R1.H = A1,R1.L = A0 (T);
506
 
507
R0.H = A1,R0.L = A0 (S2RND); 
508
R1.H = A1,R1.L = A0 (S2RND);
509
 
510
R0.H = A1,R0.L = A0 (ISS2); 
511
R1.H = A1,R1.L = A0 (ISS2);
512
 
513
R0.H = A1,R0.L = A0 (IH); 
514
R1.H = A1,R1.L = A0 (IH);
515
 
516
//Dreg = Dreg_byte (Z) ; /* (a)*/
517
 
518
R0 = R1.B(Z);
519
R0 = R2.B(Z);
520
 
521
R7 = R1.B(Z);
522
R7 = R2.B(Z);
523
 
524
//Dreg = Dreg_byte (X) ; /* (a) */
525
R0 = R1.B(X);
526
R0 = R2.B(X);
527
 
528
R7 = R1.B(X);
529
R7 = R2.B(X);
530
 

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