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[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [bfin/] [vector2.s] - Blame information for rev 156

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1 38 julius 
 
2 
.EXTERN MY_LABEL2;
3 
.section .text;
4 
 
5 
//
6 
//14 VECTOR OPERATIONS
7 
//
8 
 
9 
//Dreg_hi = Dreg_lo = SIGN ( Dreg_hi ) * Dreg_hi + SIGN ( Dreg_lo ) * Dreg_lo ; /* (b) */
10 
 
11 
r7.h=r7.l=sign(r2.h)*r3.h+sign(r2.l)*r3.l ;
12 
r0.h=r0.l=sign(r1.h)*r2.h+sign(r1.l)*r2.l ;
13 
r3.h=r3.l=sign(r4.h)*r5.h+sign(r4.l)*r5.l ;
14 
r6.h=r6.l=sign(r7.h)*r0.h+sign(r7.l)*r0.l ;
15 
r1.h=r1.l=sign(r2.h)*r3.h+sign(r2.l)*r3.l ;
16 
r4.h=r4.l=sign(r5.h)*r6.h+sign(r5.l)*r6.l ;
17 
r7.h=r7.l=sign(r0.h)*r1.h+sign(r0.l)*r1.l ;
18 
r2.h=r2.l=sign(r3.h)*r4.h+sign(r3.l)*r4.l ;
19 
 
20 
//Dual 16-Bit Operation
21 
//Dreg = VIT_MAX ( Dreg , Dreg ) (ASL) ; /* shift history bits left (b) */
22 
//Dreg = VIT_MAX ( Dreg , Dreg ) (ASR) ; /* shift history bits right (b) */
23 
//Single 16-Bit Operation
24 
//Dreg_lo = VIT_MAX ( Dreg ) (ASL) ; /* shift history bits left (b) */
25 
//Dreg_lo = VIT_MAX ( Dreg ) (ASR) ; /* shift history bits right (b) */
26 
r5 = vit_max(r3, r2)(asl) ; /* shift left, dual operation */
27 
r7 = vit_max (r1, r0) (asr) ; /* shift right, dual operation */
28 
 
29 
r0 = vit_max(r1, r2)(asl) ; /* shift left, dual operation */
30 
r3 = vit_max (r4, r5) (asr) ; /* shift right, dual operation */
31 
r6 = vit_max(r7, r0)(asl) ; /* shift left, dual operation */
32 
r1 = vit_max (r2, r3) (asr) ; /* shift right, dual operation */
33 
r4 = vit_max(r5, r6)(asl) ; /* shift left, dual operation */
34 
r7 = vit_max (r0, r1) (asr) ; /* shift right, dual operation */
35 
r2 = vit_max(r3, r4)(asl) ; /* shift left, dual operation */
36 
r5 = vit_max (r6, r7) (asr) ; /* shift right, dual operation */
37 
 
38 
 
39 
r3.l = vit_max (r1)(asl) ; /* shift left, single operation */
40 
r3.l = vit_max (r1)(asr) ; /* shift right, single operation */
41 
 
42 
r0.l = vit_max (r1)(asl) ; /* shift left, single operation */
43 
r2.l = vit_max (r3)(asr) ; /* shift right, single operation */
44 
r4.l = vit_max (r5)(asl) ; /* shift left, single operation */
45 
r6.l = vit_max (r7)(asr) ; /* shift right, single operation */
46 
r1.l = vit_max (r2)(asl) ; /* shift left, single operation */
47 
r3.l = vit_max (r4)(asr) ; /* shift right, single operation */
48 
r5.l = vit_max (r6)(asl) ; /* shift left, single operation */
49 
r7.l = vit_max (r0)(asr) ; /* shift right, single operation */
50 
 
51 
//Dreg = ABS Dreg (V) ; /* (b) */
52 
r3 = abs r1 (v) ;
53 
 
54 
r0 = abs r0 (v) ;
55 
r0 = abs r1 (v) ;
56 
r2 = abs r3 (v) ;
57 
r4 = abs r5 (v) ;
58 
r6 = abs r7 (v) ;
59 
r1 = abs r0 (v) ;
60 
r3 = abs r2 (v) ;
61 
r5 = abs r4 (v) ;
62 
r7 = abs r6 (v) ;
63 
 
64 
//Dual 16-Bit Operations
65 
//Dreg = Dreg +|+ Dreg (opt_mode_0) ; /* add | add (b) */
66 
r5=r3 +|+ r4 ; /* dual 16-bit operations, add|add */
67 
 
68 
r0=r1 +|+ r2 ;
69 
r3=r4 +|+ r5 ;
70 
r6=r7 +|+ r0 ;
71 
r1=r2 +|+ r3 ;
72 
r4=r3 +|+ r5 ;
73 
r6=r3 +|+ r7 ;
74 
 
75 
r0=r1 +|+ r2 (S);
76 
r3=r4 +|+ r5 (S);
77 
r6=r7 +|+ r0 (S);
78 
r1=r2 +|+ r3 (S);
79 
r4=r3 +|+ r5 (S);
80 
r6=r3 +|+ r7 (S);
81 
 
82 
r0=r1 +|+ r2 (CO);
83 
r3=r4 +|+ r5 (CO);
84 
r6=r7 +|+ r0 (CO) ;
85 
r1=r2 +|+ r3 (CO);
86 
r4=r3 +|+ r5 (CO);
87 
r6=r3 +|+ r7 (CO);
88 
 
89 
r0=r1 +|+ r2 (SCO);
90 
r3=r4 +|+ r5 (SCO);
91 
r6=r7 +|+ r0 (SCO);
92 
r1=r2 +|+ r3 (SCO);
93 
r4=r3 +|+ r5 (SCO);
94 
r6=r3 +|+ r7 (SCO);
95 
 
96 
//Dreg = Dreg –|+ Dreg (opt_mode_0) ; /* subtract | add (b) */
97 
r6=r0 -|+ r1(s) ; /* same as above, subtract|add with saturation */
98 
 
99 
r0=r1 -|+ r2 ;
100 
r3=r4 -|+ r5 ;
101 
r6=r7 -|+ r0 ;
102 
r1=r2 -|+ r3 ;
103 
r4=r3 -|+ r5 ;
104 
r6=r3 -|+ r7 ;
105 
 
106 
r0=r1 -|+ r2 (S);
107 
r3=r4 -|+ r5 (S);
108 
r6=r7 -|+ r0 (S);
109 
r1=r2 -|+ r3 (S);
110 
r4=r3 -|+ r5 (S);
111 
r6=r3 -|+ r7 (S);
112 
 
113 
r0=r1 -|+ r2 (CO);
114 
r3=r4 -|+ r5 (CO);
115 
r6=r7 -|+ r0 (CO) ;
116 
r1=r2 -|+ r3 (CO);
117 
r4=r3 -|+ r5 (CO);
118 
r6=r3 -|+ r7 (CO);
119 
 
120 
r0=r1 -|+ r2 (SCO);
121 
r3=r4 -|+ r5 (SCO);
122 
r6=r7 -|+ r0 (SCO);
123 
r1=r2 -|+ r3 (SCO);
124 
r4=r3 -|+ r5 (SCO);
125 
r6=r3 -|+ r7 (SCO);
126 
 
127 
 
128 
//Dreg = Dreg +|– Dreg (opt_mode_0) ; /* add | subtract (b) */
129 
r0=r2 +|- r1(co) ; /* add|subtract with half-word results crossed over in the destination register */
130 
 
131 
r0=r1 +|- r2 ;
132 
r3=r4 +|- r5 ;
133 
r6=r7 +|- r0 ;
134 
r1=r2 +|- r3 ;
135 
r4=r3 +|- r5 ;
136 
r6=r3 +|- r7 ;
137 
 
138 
r0=r1 +|- r2 (S);
139 
r3=r4 +|- r5 (S);
140 
r6=r7 +|- r0 (S);
141 
r1=r2 +|- r3 (S);
142 
r4=r3 +|- r5 (S);
143 
r6=r3 +|- r7 (S);
144 
 
145 
r0=r1 +|- r2 (CO);
146 
r3=r4 +|- r5 (CO);
147 
r6=r7 +|- r0 (CO) ;
148 
r1=r2 +|- r3 (CO);
149 
r4=r3 +|- r5 (CO);
150 
r6=r3 +|- r7 (CO);
151 
 
152 
r0=r1 +|- r2 (SCO);
153 
r3=r4 +|- r5 (SCO);
154 
r6=r7 +|- r0 (SCO);
155 
r1=r2 +|- r3 (SCO);
156 
r4=r3 +|- r5 (SCO);
157 
r6=r3 +|- r7 (SCO);
158 
 
159 
//Dreg = Dreg –|– Dreg (opt_mode_0) ; /* subtract | subtract (b) */
160 
r7=r3 -|- r6(sco) ; /* subtract|subtract with saturation and half-word results crossed over in the destination register */
161 
 
162 
r0=r1 -|- r2 ;
163 
r3=r4 -|- r5 ;
164 
r6=r7 -|- r0 ;
165 
r1=r2 -|- r3 ;
166 
r4=r3 -|- r5 ;
167 
r6=r3 -|- r7 ;
168 
 
169 
r0=r1 -|- r2 (S);
170 
r3=r4 -|- r5 (S);
171 
r6=r7 -|- r0 (S);
172 
r1=r2 -|- r3 (S);
173 
r4=r3 -|- r5 (S);
174 
r6=r3 -|- r7 (S);
175 
 
176 
r0=r1 -|- r2 (CO);
177 
r3=r4 -|- r5 (CO);
178 
r6=r7 -|- r0 (CO) ;
179 
r1=r2 -|- r3 (CO);
180 
r4=r3 -|- r5 (CO);
181 
r6=r3 -|- r7 (CO);
182 
 
183 
r0=r1 -|- r2 (SCO);
184 
r3=r4 -|- r5 (SCO);
185 
r6=r7 -|- r0 (SCO);
186 
r1=r2 -|- r3 (SCO);
187 
r4=r3 -|- r5 (SCO);
188 
r6=r3 -|- r7 (SCO);
189 
 
190 
//Quad 16-Bit Operations
191 
//Dreg = Dreg +|+ Dreg, Dreg = Dreg –|– Dreg (opt_mode_0,opt_mode_2) ; /* add | add, subtract | subtract; the set of source registers must be the same for each operation (b) */
192 
r5=r3 +|+ r4, r7=r3-|-r4 ; /* quad 16-bit operations, add|add, subtract|subtract */
193 
 
194 
r0=r1 +|+ r2, r7=r1 -|- r2;
195 
r3=r4 +|+ r5, r6=r4 -|- r5;
196 
r6=r7 +|+ r0, r5=r7 -|- r0;
197 
r1=r2 +|+ r3, r4=r2 -|- r3;
198 
r4=r3 +|+ r5, r3=r3 -|- r5;
199 
r6=r3 +|+ r7, r2=r3 -|- r7;
200 
 
201 
r0=r1 +|+ r2, r7=r1 -|- r2(S);
202 
r3=r4 +|+ r5, r6=r4 -|- r5(S);
203 
r6=r7 +|+ r0, r5=r7 -|- r0(S);
204 
r1=r2 +|+ r3, r4=r2 -|- r3(S);
205 
r4=r3 +|+ r5, r3=r3 -|- r5(S);
206 
r6=r3 +|+ r7, r2=r3 -|- r7(S);
207 
 
208 
 
209 
r0=r1 +|+ r2, r7=r1 -|- r2(CO);
210 
r3=r4 +|+ r5, r6=r4 -|- r5(CO);
211 
r6=r7 +|+ r0, r5=r7 -|- r0(CO);
212 
r1=r2 +|+ r3, r4=r2 -|- r3(CO);
213 
r4=r3 +|+ r5, r3=r3 -|- r5(CO);
214 
r6=r3 +|+ r7, r2=r3 -|- r7(CO);
215 
 
216 
 
217 
r0=r1 +|+ r2, r7=r1 -|- r2(SCO);
218 
r3=r4 +|+ r5, r6=r4 -|- r5(SCO);
219 
r6=r7 +|+ r0, r5=r7 -|- r0(SCO);
220 
r1=r2 +|+ r3, r4=r2 -|- r3(SCO);
221 
r4=r3 +|+ r5, r3=r3 -|- r5(SCO);
222 
r6=r3 +|+ r7, r2=r3 -|- r7(SCO);
223 
 
224 
r0=r1 +|+ r2, r7=r1 -|- r2(ASR);
225 
r3=r4 +|+ r5, r6=r4 -|- r5(ASR);
226 
r6=r7 +|+ r0, r5=r7 -|- r0(ASR);
227 
r1=r2 +|+ r3, r4=r2 -|- r3(ASR);
228 
r4=r3 +|+ r5, r3=r3 -|- r5(ASR);
229 
r6=r3 +|+ r7, r2=r3 -|- r7(ASR);
230 
 
231 
 
232 
r0=r1 +|+ r2, r7=r1 -|- r2(ASL);
233 
r3=r4 +|+ r5, r6=r4 -|- r5(ASL);
234 
r6=r7 +|+ r0, r5=r7 -|- r0(ASL);
235 
r1=r2 +|+ r3, r4=r2 -|- r3(ASL);
236 
r4=r3 +|+ r5, r3=r3 -|- r5(ASL);
237 
r6=r3 +|+ r7, r2=r3 -|- r7(ASL);
238 
 
239 
 
240 
r0=r1 +|+ r2, r7=r1 -|- r2(S,ASR);
241 
r3=r4 +|+ r5, r6=r4 -|- r5(S,ASR);
242 
r6=r7 +|+ r0, r5=r7 -|- r0(S,ASR);
243 
r1=r2 +|+ r3, r4=r2 -|- r3(S,ASR);
244 
r4=r3 +|+ r5, r3=r3 -|- r5(S,ASR);
245 
r6=r3 +|+ r7, r2=r3 -|- r7(S,ASR);
246 
 
247 
 
248 
r0=r1 +|+ r2, r7=r1 -|- r2(CO,ASR);
249 
r3=r4 +|+ r5, r6=r4 -|- r5(CO,ASR);
250 
r6=r7 +|+ r0, r5=r7 -|- r0(CO,ASR);
251 
r1=r2 +|+ r3, r4=r2 -|- r3(CO,ASR);
252 
r4=r3 +|+ r5, r3=r3 -|- r5(CO,ASR);
253 
r6=r3 +|+ r7, r2=r3 -|- r7(CO,ASR);
254 
 
255 
 
256 
r0=r1 +|+ r2, r7=r1 -|- r2(SCO,ASR);
257 
r3=r4 +|+ r5, r6=r4 -|- r5(SCO,ASR);
258 
r6=r7 +|+ r0, r5=r7 -|- r0(SCO,ASR);
259 
r1=r2 +|+ r3, r4=r2 -|- r3(SCO,ASR);
260 
r4=r3 +|+ r5, r3=r3 -|- r5(SCO,ASR);
261 
r6=r3 +|+ r7, r2=r3 -|- r7(SCO,ASR);
262 
 
263 
r0=r1 +|+ r2, r7=r1 -|- r2(S,ASL);
264 
r3=r4 +|+ r5, r6=r4 -|- r5(S,ASL);
265 
r6=r7 +|+ r0, r5=r7 -|- r0(S,ASL);
266 
r1=r2 +|+ r3, r4=r2 -|- r3(S,ASL);
267 
r4=r3 +|+ r5, r3=r3 -|- r5(S,ASL);
268 
r6=r3 +|+ r7, r2=r3 -|- r7(S,ASL);
269 
 
270 
 
271 
r0=r1 +|+ r2, r7=r1 -|- r2(CO,ASL);
272 
r3=r4 +|+ r5, r6=r4 -|- r5(CO,ASL);
273 
r6=r7 +|+ r0, r5=r7 -|- r0(CO,ASL);
274 
r1=r2 +|+ r3, r4=r2 -|- r3(CO,ASL);
275 
r4=r3 +|+ r5, r3=r3 -|- r5(CO,ASL);
276 
r6=r3 +|+ r7, r2=r3 -|- r7(CO,ASL);
277 
 
278 
 
279 
r0=r1 +|+ r2, r7=r1 -|- r2(SCO,ASL);
280 
r3=r4 +|+ r5, r6=r4 -|- r5(SCO,ASL);
281 
r6=r7 +|+ r0, r5=r7 -|- r0(SCO,ASL);
282 
r1=r2 +|+ r3, r4=r2 -|- r3(SCO,ASL);
283 
r4=r3 +|+ r5, r3=r3 -|- r5(SCO,ASL);
284 
r6=r3 +|+ r7, r2=r3 -|- r7(SCO,ASL);
285 
 
286 
 
287 
//Dreg = Dreg +|– Dreg, Dreg = Dreg –|+ Dreg (opt_mode_0,opt_mode_2) ; /* add | subtract, subtract | add; the set of source registers must be the same for each operation (b) */
288 
r5=r3 +|- r4, r7=r3 -|+ r4 ; /* quad 16-bit operations, add|subtract, subtract|add */
289 
 
290 
r0=r1 +|- r2, r7=r1 -|+ r2;
291 
r3=r4 +|- r5, r6=r4 -|+ r5;
292 
r6=r7 +|- r0, r5=r7 -|+ r0;
293 
r1=r2 +|- r3, r4=r2 -|+ r3;
294 
r4=r3 +|- r5, r3=r3 -|+ r5;
295 
r6=r3 +|- r7, r2=r3 -|+ r7;
296 
 
297 
r0=r1 +|- r2, r7=r1 -|+ r2(S);
298 
r3=r4 +|- r5, r6=r4 -|+ r5(S);
299 
r6=r7 +|- r0, r5=r7 -|+ r0(S);
300 
r1=r2 +|- r3, r4=r2 -|+ r3(S);
301 
r4=r3 +|- r5, r3=r3 -|+ r5(S);
302 
r6=r3 +|- r7, r2=r3 -|+ r7(S);
303 
 
304 
 
305 
r0=r1 +|- r2, r7=r1 -|+ r2(CO);
306 
r3=r4 +|- r5, r6=r4 -|+ r5(CO);
307 
r6=r7 +|- r0, r5=r7 -|+ r0(CO);
308 
r1=r2 +|- r3, r4=r2 -|+ r3(CO);
309 
r4=r3 +|- r5, r3=r3 -|+ r5(CO);
310 
r6=r3 +|- r7, r2=r3 -|+ r7(CO);
311 
 
312 
 
313 
r0=r1 +|- r2, r7=r1 -|+ r2(SCO);
314 
r3=r4 +|- r5, r6=r4 -|+ r5(SCO);
315 
r6=r7 +|- r0, r5=r7 -|+ r0(SCO);
316 
r1=r2 +|- r3, r4=r2 -|+ r3(SCO);
317 
r4=r3 +|- r5, r3=r3 -|+ r5(SCO);
318 
r6=r3 +|- r7, r2=r3 -|+ r7(SCO);
319 
 
320 
r0=r1 +|- r2, r7=r1 -|+ r2(ASR);
321 
r3=r4 +|- r5, r6=r4 -|+ r5(ASR);
322 
r6=r7 +|- r0, r5=r7 -|+ r0(ASR);
323 
r1=r2 +|- r3, r4=r2 -|+ r3(ASR);
324 
r4=r3 +|- r5, r3=r3 -|+ r5(ASR);
325 
r6=r3 +|- r7, r2=r3 -|+ r7(ASR);
326 
 
327 
 
328 
r0=r1 +|- r2, r7=r1 -|+ r2(ASL);
329 
r3=r4 +|- r5, r6=r4 -|+ r5(ASL);
330 
r6=r7 +|- r0, r5=r7 -|+ r0(ASL);
331 
r1=r2 +|- r3, r4=r2 -|+ r3(ASL);
332 
r4=r3 +|- r5, r3=r3 -|+ r5(ASL);
333 
r6=r3 +|- r7, r2=r3 -|+ r7(ASL);
334 
 
335 
 
336 
r0=r1 +|- r2, r7=r1 -|+ r2(S,ASR);
337 
r3=r4 +|- r5, r6=r4 -|+ r5(S,ASR);
338 
r6=r7 +|- r0, r5=r7 -|+ r0(S,ASR);
339 
r1=r2 +|- r3, r4=r2 -|+ r3(S,ASR);
340 
r4=r3 +|- r5, r3=r3 -|+ r5(S,ASR);
341 
r6=r3 +|- r7, r2=r3 -|+ r7(S,ASR);
342 
 
343 
 
344 
r0=r1 +|- r2, r7=r1 -|+ r2(CO,ASR);
345 
r3=r4 +|- r5, r6=r4 -|+ r5(CO,ASR);
346 
r6=r7 +|- r0, r5=r7 -|+ r0(CO,ASR);
347 
r1=r2 +|- r3, r4=r2 -|+ r3(CO,ASR);
348 
r4=r3 +|- r5, r3=r3 -|+ r5(CO,ASR);
349 
r6=r3 +|- r7, r2=r3 -|+ r7(CO,ASR);
350 
 
351 
 
352 
r0=r1 +|- r2, r7=r1 -|+ r2(SCO,ASR);
353 
r3=r4 +|- r5, r6=r4 -|+ r5(SCO,ASR);
354 
r6=r7 +|- r0, r5=r7 -|+ r0(SCO,ASR);
355 
r1=r2 +|- r3, r4=r2 -|+ r3(SCO,ASR);
356 
r4=r3 +|- r5, r3=r3 -|+ r5(SCO,ASR);
357 
r6=r3 +|- r7, r2=r3 -|+ r7(SCO,ASR);
358 
 
359 
r0=r1 +|- r2, r7=r1 -|+ r2(S,ASL);
360 
r3=r4 +|- r5, r6=r4 -|+ r5(S,ASL);
361 
r6=r7 +|- r0, r5=r7 -|+ r0(S,ASL);
362 
r1=r2 +|- r3, r4=r2 -|+ r3(S,ASL);
363 
r4=r3 +|- r5, r3=r3 -|+ r5(S,ASL);
364 
r6=r3 +|- r7, r2=r3 -|+ r7(S,ASL);
365 
 
366 
 
367 
r0=r1 +|- r2, r7=r1 -|+ r2(CO,ASL);
368 
r3=r4 +|- r5, r6=r4 -|+ r5(CO,ASL);
369 
r6=r7 +|- r0, r5=r7 -|+ r0(CO,ASL);
370 
r1=r2 +|- r3, r4=r2 -|+ r3(CO,ASL);
371 
r4=r3 +|- r5, r3=r3 -|+ r5(CO,ASL);
372 
r6=r3 +|- r7, r2=r3 -|+ r7(CO,ASL);
373 
 
374 
 
375 
r0=r1 +|- r2, r7=r1 -|+ r2(SCO,ASL);
376 
r3=r4 +|- r5, r6=r4 -|+ r5(SCO,ASL);
377 
r6=r7 +|- r0, r5=r7 -|+ r0(SCO,ASL);
378 
r1=r2 +|- r3, r4=r2 -|+ r3(SCO,ASL);
379 
r4=r3 +|- r5, r3=r3 -|+ r5(SCO,ASL);
380 
r6=r3 +|- r7, r2=r3 -|+ r7(SCO,ASL);
381 
 
382 
 
383 
 
384 
//Dual 32-Bit Operations
385 
//Dreg = Dreg + Dreg, Dreg = Dreg - Dreg (opt_mode_1) ; /* add, subtract; the set of source registers must be the same for each operation (b) */
386 
r2=r0+r1, r3=r0-r1 ; /* 32-bit operations */
387 
 
388 
r7=r0+r1, r0=r0-r1 ; /* 32-bit operations */
389 
r6=r1+r2, r1=r1-r2 ; /* 32-bit operations */
390 
r5=r2+r3, r2=r2-r3 ; /* 32-bit operations */
391 
r4=r3+r4, r3=r3-r4 ; /* 32-bit operations */
392 
r3=r4+r5, r4=r4-r5 ; /* 32-bit operations */
393 
r2=r5+r6, r5=r5-r6 ; /* 32-bit operations */
394 
r1=r6+r7, r6=r6-r7 ; /* 32-bit operations */
395 
r0=r7+r0, r7=r7-r0 ; /* 32-bit operations */
396 
 
397 
r2=r0+r1, r3=r0-r1(s) ; /* dual 32-bit operations with saturation */
398 
r7=r0+r1, r0=r0-r1 (s); /* 32-bit operations */
399 
r6=r1+r2, r1=r1-r2 (s); /* 32-bit operations */
400 
r5=r2+r3, r2=r2-r3 (s); /* 32-bit operations */
401 
r4=r3+r4, r3=r3-r4(s) ; /* 32-bit operations */
402 
r3=r4+r5, r4=r4-r5 (s); /* 32-bit operations */
403 
r2=r5+r6, r5=r5-r6 (s); /* 32-bit operations */
404 
r1=r6+r7, r6=r6-r7 (s); /* 32-bit operations */
405 
r0=r7+r0, r7=r7-r0 (s); /* 32-bit operations */
406 
 
407 
 
408 
 
409 
//Dual 40-Bit Accumulator Operations
410 
//Dreg = A1 + A0, Dreg = A1 - A0 (opt_mode_1) ; /* add, subtract Accumulators; subtract A0 from A1 (b) */
411 
r0=a1+a0, r1=a1-a0 ;
412 
r2=a1+a0, r3=a1-a0 ;
413 
r4=a1+a0, r5=a1-a0 ;
414 
r6=a1+a0, r7=a1-a0 ;
415 
r1=a1+a0, r0=a1-a0 ;
416 
r3=a1+a0, r2=a1-a0 ;
417 
r5=a1+a0, r4=a1-a0 ;
418 
 
419 
r0=a1+a0, r1=a1-a0 (s);
420 
r2=a1+a0, r3=a1-a0 (s);
421 
r4=a1+a0, r5=a1-a0 (s);
422 
r6=a1+a0, r7=a1-a0 (s);
423 
r1=a1+a0, r0=a1-a0 (s);
424 
r3=a1+a0, r2=a1-a0 (s);
425 
r5=a1+a0, r4=a1-a0 (s);
426 
 
427 
//Dreg = A0 + A1, Dreg = A0 - A1 (opt_mode_1) ; /* add, subtract Accumulators; subtract A1 from A0 (b) */
428 
r4=a0+a1, r6=a0-a1(s);
429 
 
430 
r0=a0+a1, r1=a0-a1 ;
431 
r2=a0+a1, r3=a0-a1 ;
432 
r4=a0+a1, r5=a0-a1 ;
433 
r6=a0+a1, r7=a0-a1 ;
434 
r1=a0+a1, r0=a0-a1 ;
435 
r3=a0+a1, r2=a0-a1 ;
436 
r5=a0+a1, r4=a0-a1 ;
437 
 
438 
r0=a0+a1, r1=a0-a1 (s);
439 
r2=a0+a1, r3=a0-a1 (s);
440 
r4=a0+a1, r5=a0-a1 (s);
441 
r6=a0+a1, r7=a0-a1 (s);
442 
r1=a0+a1, r0=a0-a1 (s);
443 
r3=a0+a1, r2=a0-a1 (s);
444 
r5=a0+a1, r4=a0-a1 (s);
445 
 
446 
//Constant Shift Magnitude
447 
//Dreg = Dreg >>> uimm4 (V) ; /* arithmetic shift right, immediate (b) */
448 
R0 = R0 >>> 5(V);
449 
 
450 
R0 = R1 >>> 5(V);
451 
R2 = R3 >>> 5(V);
452 
R4 = R5 >>> 5(V);
453 
R6 = R7 >>> 5(V);
454 
R1 = R0 >>> 5(V);
455 
R3 = R2 >>> 5(V);
456 
R5 = R4 >>> 5(V);
457 
R7 = R6 >>> 5(V);
458 
 
459 
 
460 
//Dreg = Dreg << uimm4 (V,S) ; /* arithmetic shift left, immediate with saturation (b) */
461 
 
462 
R0 = R1 << 5(V,S);
463 
R2 = R3 << 5(V,S);
464 
R4 = R5 << 5(V,S);
465 
R6 = R7 << 5(V,S);
466 
R1 = R0 << 5(V,S);
467 
R3 = R2 << 5(V,S);
468 
R5 = R4 << 5(V,S);
469 
R7 = R6 << 5(V,S);
470 
 
471 
//Registered Shift Magnitude
472 
//Dreg = ASHIFT Dreg BY Dreg_lo (V) ; /* arithmetic shift (b) */
473 
r2=ashift r7 by r5.l (v) ;
474 
 
475 
R0 = ASHIFT R1 BY R2.L (V);
476 
R3 = ASHIFT R4 BY R5.L (V);
477 
R6 = ASHIFT R7 BY R0.L (V);
478 
R1 = ASHIFT R2 BY R3.L (V);
479 
R4 = ASHIFT R5 BY R6.L (V);
480 
R7 = ASHIFT R0 BY R1.L (V);
481 
R2 = ASHIFT R3 BY R4.L (V);
482 
R5 = ASHIFT R6 BY R7.L (V);
483 
 
484 
 
485 
//Dreg = ASHIFT Dreg BY Dreg_lo (V, S) ; /* arithmetic shift with saturation (b) */
486 
R0 = ASHIFT R1 BY R2.L (V,S);
487 
R3 = ASHIFT R4 BY R5.L (V,S);
488 
R6 = ASHIFT R7 BY R0.L (V,S);
489 
R1 = ASHIFT R2 BY R3.L (V,S);
490 
R4 = ASHIFT R5 BY R6.L (V,S);
491 
R7 = ASHIFT R0 BY R1.L (V,S);
492 
R2 = ASHIFT R3 BY R4.L (V,S);
493 
R5 = ASHIFT R6 BY R7.L (V,S);
494 
 
495 
//Constant Shift Magnitude
496 
//Dreg = Dreg >> uimm4 (V) ; /* logical shift right, immediate (b) */
497 
R0 = R1 >> 5(V);
498 
R2 = R3 >> 5(V);
499 
R4 = R5 >> 5(V);
500 
R6 = R7 >> 5(V);
501 
R1 = R0 >> 5(V);
502 
R3 = R2 >> 5(V);
503 
R5 = R4 >> 5(V);
504 
R7 = R6 >> 5(V);
505 
 
506 
//Dreg = Dreg << uimm4 (V) ; /* logical shift left, immediate (b) */
507 
R0 = R1 << 5(V);
508 
R2 = R3 << 5(V);
509 
R4 = R5 << 5(V);
510 
R6 = R7 << 5(V);
511 
R1 = R0 << 5(V);
512 
R3 = R2 << 5(V);
513 
R5 = R4 << 5(V);
514 
R7 = R6 << 5(V);
515 
 
516 
 
517 
//Registered Shift Magnitude
518 
//Dreg = LSHIFT Dreg BY Dreg_lo (V) ; /* logical shift (b) */
519 
 
520 
R0 = LSHIFT R1 BY R2.L (V);
521 
R3 = LSHIFT R4 BY R5.L (V);
522 
R6 = LSHIFT R7 BY R0.L (V);
523 
R1 = LSHIFT R2 BY R3.L (V);
524 
R4 = LSHIFT R5 BY R6.L (V);
525 
R7 = LSHIFT R0 BY R1.L (V);
526 
R2 = LSHIFT R3 BY R4.L (V);
527 
R5 = LSHIFT R6 BY R7.L (V);
528 
 
529 
//Dreg = MAX ( Dreg , Dreg ) (V) ; /* dual 16-bit operations (b) */
530 
r7 = max (r1, r0) (v) ;
531 
 
532 
R0 = MAX (R1, R2) (V);
533 
R3 = MAX (R4, R5) (V);
534 
R6 = MAX (R7, R0) (V);
535 
R1 = MAX (R2, R3) (V);
536 
R4 = MAX (R5, R6) (V);
537 
R7 = MAX (R0, R1) (V);
538 
R2 = MAX (R3, R4) (V);
539 
R5 = MAX (R6, R7) (V);
540 
 
541 
//Dreg = MIN ( Dreg , Dreg ) (V) ; /* dual 16-bit operation (b) */
542 
R0 = MIN (R1, R2) (V);
543 
R3 = MIN (R4, R5) (V);
544 
R6 = MIN (R7, R0) (V);
545 
R1 = MIN (R2, R3) (V);
546 
R4 = MIN (R5, R6) (V);
547 
R7 = MIN (R0, R1) (V);
548 
R2 = MIN (R3, R4) (V);
549 
R5 = MIN (R6, R7) (V);
550 
 
551 
r2.h=r7.l*r6.h, r2.l=r7.h*r6.h ;
552 
/* simultaneous MAC0 and MAC1 execution, 16-bit results. Both
553 
results are signed fractions. */
554 
r4.l=r1.l*r0.l, r4.h=r1.h*r0.h ;
555 
/* same as above. MAC order is arbitrary. */
556 
r0.h=r3.h*r2.l (m), r0.l=r3.l*r2.l ;
557 
 
558 
a1=r2.l*r3.h, a0=r2.h*r3.h ;
559 
/* both multiply signed fractions into separate Accumulators */
560 
a0=r1.l*r0.l, a1+=r1.h*r0.h ;
561 
/* same as above, but sum result into A1. MAC order is arbitrary.
562 
*/
563 
a1+=r3.h*r3.l, a0-=r3.h*r3.h ;
564 
/* sum product into A1, subtract product from A0 */
565 
a1=r3.h*r2.l (m), a0+=r3.l*r2.l ;
566 
/* MAC1 multiplies a signed fraction in r3.h by an unsigned fraction
567 
in r2.l. MAC0 multiplies two signed fractions. */
568 
a1=r7.h*r4.h (m), a0+=r7.l*r4.l (fu) ;
569 
/* MAC1 multiplies signed fraction by unsigned fraction. MAC0
570 
multiplies and accumulates two unsigned fractions. */
571 
a1+=r3.h*r2.h, a0=r3.l*r2.l (is) ;
572 
/* both MACs perform signed integer multiplication */
573 
a1=r6.h*r7.h, a0+=r6.l*r7.l (w32) ;
574 
/* both MACs multiply signed fractions, sign extended, and saturate
575 
both Accumulators at bit 31 */
576 
r2.h=(a1=r7.l*r6.h), r2.l=(a0=r7.h*r6.h) ; /* simultaneous MAC0
577 
and MAC1 execution, both are signed fractions, both products load
578 
into the Accumulators,MAC1 into half-word registers. */
579 
r4.l=(a0=r1.l*r0.l), r4.h=(a1+=r1.h*r0.h) ; /* same as above,
580 
but sum result into A1. ; MAC order is arbitrary. */
581 
r7.h=(a1+=r6.h*r5.l), r7.l=(a0=r6.h*r5.h) ; /* sum into A1,
582 
subtract into A0 */
583 
r0.h=(a1=r7.h*r4.l) (m), r0.l=(a0+=r7.l*r4.l) ; /* MAC1 multiplies
584 
a signed fraction by an unsigned fraction. MAC0 multiplies
585 
two signed fractions. */
586 
r5.h=(a1=r3.h*r2.h) (m), r5.l=(a0+=r3.l*r2.l) (fu) ; /* MAC1
587 
multiplies signed fraction by unsigned fraction. MAC0 multiplies
588 
two unsigned fractions. */
589 
r0.h=(a1+=r3.h*r2.h), r0.l=(a0=r3.l*r2.l) (is) ; /* both MACs
590 
perform signed integer multiplication. */
591 
r5.h=(a1=r2.h*r1.h), a0+=r2.l*r1.l ; /* both MACs multiply
592 
signed fractions. MAC0 does not copy the accum result. */
593 
r3.h=(a1=r2.h*r1.h) (m), a0=r2.l*r1.l ; /* MAC1 multiplies
594 
signed fraction by unsigned fraction and uses all 40 bits of A1.
595 
MAC0 multiplies two signed fractions. */
596 
r3.h=a1, r3.l=(a0+=r0.l*r1.l) (s2rnd) ; /* MAC1 copies Accumulator
597 
to register half. MAC0 multiplies signed fractions. Both
598 
scale the result and round on the way to the destination register.
599 
*/
600 
r0.l=(a0+=r7.l*r6.l), r0.h=(a1+=r7.h*r6.h) (iss2) ; /* both
601 
MACs process signed integer the way to the destination half-registers.
602 
*/
603 
r3=(a1=r6.h*r7.h), r2=(a0=r6.l*r7.l) ; /* simultaneous MAC0 and
604 
MAC1 execution, both are signed fractions, both products load
605 
into the Accumulators */
606 
r4=(a0=r6.l*r7.l), r5=(a1+=r6.h*r7.h) ; /* same as above, but
607 
sum result into A1. MAC order is arbitrary. */
608 
r7=(a1+=r3.h*r5.h), r6=(a0-=r3.l*r5.l) ; /* sum into A1, subtract
609 
into A0 */
610 
r1=(a1=r7.l*r4.l) (m), r0=(a0+=r7.h*r4.h) ; /* MAC1 multiplies
611 
a signed fraction by an unsigned fraction. MAC0 multiplies two
612 
signed fractions. */
613 
r5=(a1=r3.h*r7.h) (m), r4=(a0+=r3.l*r7.l) (fu) ; /* MAC1 multiplies
614 
signed fraction by unsigned fraction. MAC0 multiplies two
615 
unsigned fractions. */
616 
r1=(a1+=r3.h*r2.h), r0=(a0=r3.l*r2.l) (is) ; /* both MACs perform
617 
signed integer multiplication */
618 
r5=(a1-=r6.h*r7.h), a0+=r6.l*r7.l ; /* both MACs multiply
619 
signed fractions. MAC0 does not copy the accum result */
620 
r3=(a1=r6.h*r7.h) (m), a0-=r6.l*r7.l ; /* MAC1 multiplies
621 
signed fraction by unsigned fraction and uses all 40 bits of A1.
622 
MAC0 multiplies two signed fractions. */
623 
r3=a1, r2=(a0+=r0.l*r1.l) (s2rnd) ; /* MAC1 moves Accumulator
624 
to register. MAC0 multiplies signed fractions. Both scale the
625 
result and round on the way to the destination register. */
626 
r0=(a0+=r7.l*r6.l), r1=(a1+=r7.h*r6.h) (iss2) ; /* both MACs
627 
process signed integer operands and scale the result on the way
628 
to the destination registers. */
629 
 
630 
r5 =-r3 (v) ; /* R5.H becomes the negative of R3.H and R5.L
631 
becomes the negative of R3.L If r3 = 0x0004 7FFF the result is r5
632 
= 0xFFFC 8001 */
633 
 
634 
r3=pack(r4.l, r5.l) ; /* pack low / low half-words */
635 
r1=pack(r6.l, r4.h) ; /* pack low / high half-words */
636 
r0=pack(r2.h, r4.l) ; /* pack high / low half-words */
637 
r5=pack(r7.h, r2.h) ; /* pack high / high half-words */
638 
 
639 
(r1,r0) = SEARCH R2 (LE) || R2=[P0++];
640 
/* search for the last minimum in all but the
641 
last element of the array */
642 
(r1,r0) = SEARCH R2 (LE);
643 
 
644 
saa (r1:0, r3:2) || r0=[i0++] || r2=[i1++] ;
645 
saa (r1:0, r3:2)(r) || r1=[i0++] || r3=[i1++] ;
646 
mnop || r1 = [i0++] || r3 = [i1++] ;
647 
r7.h=r7.l=sign(r2.h)*r3.h + sign(r2.l)*r3.l || i0+=m3 || r0=[i0]
648 
;
649 
 
650 
/* Add/subtract two vector values while incrementing an Ireg and
651 
loading a data register. */
652 
R2 = R2 +|+ R4, R4 = R2 -|- R4 (ASR) || I0 += M0 (BREV) || R1 = [I0] ;
653 
/* Multiply and accumulate to Accumulator while loading a data
654 
register and storing a data register using an Ireg pointer. */
655 
A1=R2.L*R1.L, A0=R2.H*R1.H || R2.H=W[I2++] || [I3++]=R3 ;
656 
/* Multiply and accumulate while loading two data registers. One
657 
load uses an Ireg pointer. */
658 
A1+=R0.L*R2.H,A0+=R0.L*R2.L || R2.L=W[I2++] || R0=[I1--] ;
659 
R3.H=(A1+=R0.L*R1.H), R3.L=(A0+=R0.L*R1.L) || R0=[P0++] || R1=[I0] ;
660 
/* Pack two vector values while storing a data register using an
661 
Ireg pointer and loading another data register. */
662 
R1=PACK(R1.H,R0.H) || [I0++]=R0 || R2.L=W[I2++] ;
663 
 
664 
/* Multiply-Accumulate to a Data register while incrementing an
665 
Ireg. */
666 
r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 ;
667 
/* which the assembler expands into:
668 
r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 || nop ; */
669 
 
670 
/* Test for ensure (m) is not thown away.  */
671 
r0.l=r3.l*r2.l, r0.h=r3.h*r2.l (m) ;
672 
R2 = R7.L * R0.L, R3 = R7.L * R0.H (m);
673 
R2 = (A0 = R7.L * R0.L), R3 = ( A1 = R7.L * R0.H) (m);
674 
 
675 
/* Both scalar instructions must share the same mode option.  */
676 
R0.H = (A1 = R4.L * R3.L), A0 = R4.H * R3.L (T);
677 
R0.H = (A1 = R4.L * R3.L) (M), A0 = R4.H * R3.L (T);
678 
A0 = R4.H * R3.L, R0.H = (A1 = R4.L * R3.L) (T);
679 
A0 = R4.H * R3.L, R0.H = (A1 = R4.L * R3.L) (T,M);
680 
A1 += R7.H * R4.H, R0.L = (A0 = R7.L * R4.H) (T);

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