OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [d30v/] [serial.l] - Blame information for rev 832

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
.*: Assembler messages:
2
.*:6: Error: Unable to mix instructions as specified
3
.*:7: Error: Unable to mix instructions as specified
4
.*:8: Error: Unable to mix instructions as specified
5
.*:9: Error: Unable to mix instructions as specified
6
GAS LISTING .*
7
 
8
 
9
   1                    # serial.s
10
   2                    #
11
   3                    # In the following examples, the right-subinstructions
12
   4                    # will never be executed.  GAS should detect this.
13
   5
14
   6 \?\?\?\? ........          trap r21 -> add r2, r0, r0 ; right instruction will never be executed.
15
\*\*\*\*  Error:Unable to mix instructions as specified
16
   6      ........
17
   7 \?\?\?\? 08002000          dbt     -> add r2, r0, r0               ; ditto
18
\*\*\*\*  Error:Unable to mix instructions as specified
19
   7      00F00000
20
   7      00B00000
21
   7      00F00000
22
   8 \?\?\?\? 08002000          rtd     -> add r2, r0, r0               ; ditto
23
\*\*\*\*  Error:Unable to mix instructions as specified
24
   8      00F00000
25
   8      00A00000
26
   8      00F00000
27
   9 \?\?\?\? 08002000          reit    -> add r2, r0, r0               ; ditto
28
\*\*\*\*  Error:Unable to mix instructions as specified
29
   9      00F00000
30
   9      00800000
31
   9      00F00000
32
  10 \?\?\?\? 08002000          mvtsys psw,  r1 -> add r2, r0, r0       ; OK
33
  10      00F00000
34
  10      00E00040
35
  10      88002000
36
  11 \?\?\?\? 00E00042          mvtsys pswh, r1 -> add r2, r0, r0       ; OK
37
  11      88002000
38
  12 \?\?\?\? 00E00041          mvtsys pswl, r1 -> add r2, r0, r0       ; OK
39
  12      88002000
40
  13 \?\?\?\? 00E00043          mvtsys f0, r1 -> add r2, r0, r0         ; OK
41
  13      88002000
42
  14 \?\?\?\? 00E0A040          mvtsys mod_s, r1 -> add r2, r0, r0      ; OK
43
  14      88002000

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.