URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [i386/] [intel-regs.d] - Blame information for rev 832

Line No.	Rev	Author	Line
1	38	julius	`#objdump: -drw`
2			`#name: i386 Intel register names`
3
4			`.: +file format .i386.*`
5
6			`Disassembly of section \.text:`
7			`0+0 <.*>:`
8			`.*[ ]+R_386_16[ ]+eax`
9			`.*[ ]+R_386_16[ ]+rax`
10			`.*[ ]+R_386_16[ ]+axl`
11			`.*[ ]+R_386_16[ ]+r8b`
12			`.*[ ]+R_386_16[ ]+r8w`
13			`.*[ ]+R_386_16[ ]+r8d`
14			`.*[ ]+R_386_16[ ]+r8`
15			`.*[ ]+R_386_16[ ]+fs`
16			`#.*[ ]+R_386_16[ ]+st`
17			`.*[ ]+R_386_16[ ]+cr0`
18			`.*[ ]+R_386_16[ ]+dr0`
19			`.*[ ]+R_386_16[ ]+tr0`
20			`.*[ ]+R_386_16[ ]+mm0`
21			`.*[ ]+R_386_16[ ]+xmm0`
22			`.*[ ]+R_386_32[ ]+rax`
23			`.*[ ]+R_386_32[ ]+axl`
24			`.*[ ]+R_386_32[ ]+r8b`
25			`.*[ ]+R_386_32[ ]+r8w`
26			`.*[ ]+R_386_32[ ]+r8d`
27			`.*[ ]+R_386_32[ ]+r8`
28			`#.*[ ]+R_386_32[ ]+st`
29			`.*:[ ]+0f 20 c0[ ]+mov[ ]+%cr0,%eax`
30			`.*:[ ]+0f 21 c0[ ]+mov[ ]+%db0,%eax`
31			`.*:[ ]+0f 24 c0[ ]+mov[ ]+%tr0,%eax`
32			`.*[ ]+R_386_32[ ]+mm0`
33			`.*[ ]+R_386_32[ ]+xmm0`
34			`.*[ ]+R_386_32[ ]+ymm0`
35			`.*:[ ]+dd c0[ ]+ffree[ ]+%st(\(0\))?`
36			`.*:[ ]+0f ef c0[ ]+pxor[ ]+%mm0,%mm0`
37			`.*:[ ]+0f 57 c0[ ]+xorps[ ]+%xmm0,%xmm0`
38			`.*:[ ]+c5 fc 57 c0[ ]+vxorps[ ]+%ymm0,%ymm0,%ymm0`
39			`.*:[ ]+44[ ]+inc %esp`
40			`.*:[ ]+88 c0[ ]+mov[ ]+%al,%al`
41			`.*:[ ]+66 44[ ]+inc[ ]+%sp`
42			`.*:[ ]+89 c0[ ]+mov[ ]+%eax,%eax`
43			`.*:[ ]+44[ ]+inc %esp`
44			`.*:[ ]+89 c0[ ]+mov[ ]+%eax,%eax`
45			`.*:[ ]+4c[ ]+dec %esp`
46			`.*:[ ]+89 c0[ ]+mov[ ]+%eax,%eax`
47			`#pass`