URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Go to most recent revision |
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
38 |
julius |
#as: -J
|
| 2 |
|
|
#objdump: -drw
|
| 3 |
|
|
#name: x86-64 32-bit addressing
|
| 4 |
|
|
|
| 5 |
|
|
.*: +file format .*
|
| 6 |
|
|
|
| 7 |
|
|
Disassembly of section .text:
|
| 8 |
|
|
|
| 9 |
|
|
0+000 <.text>:
|
| 10 |
|
|
[ ]*0:[ ]+67 48 8d 80 00 00 00 00[ ]+(addr32[ ]+)?lea[ ]+0x0\(%eax\),%rax.*
|
| 11 |
|
|
[ ]*8:[ ]+67 49 8d 80 00 00 00 00[ ]+(addr32[ ]+)?lea[ ]+0x0\(%r8d\),%rax.*
|
| 12 |
|
|
[ ]*10:[ ]+67 48 8d 05 00 00 00 00[ ]+(addr32[ ]+)?lea[ ]+0x0\(%eip\),%rax.*
|
| 13 |
|
|
[ ]*18:[ ]+67 48 8d 04 25 00 00 00 00[ ]+addr32[ ]+lea[ ]+0x0,%rax.*
|
| 14 |
|
|
[ ]*21:[ ]+67 a0 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%al
|
| 15 |
|
|
[ ]*27:[ ]+67 66 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%ax
|
| 16 |
|
|
[ ]*2e:[ ]+67 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%eax
|
| 17 |
|
|
[ ]*34:[ ]+67 48 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%rax
|
| 18 |
|
|
[ ]*3b:[ ]+67 a2 98 08 60 00[ ]+addr32[ ]+mov[ ]+%al,0x600898
|
| 19 |
|
|
[ ]*41:[ ]+67 66 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%ax,0x600898
|
| 20 |
|
|
[ ]*48:[ ]+67 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%eax,0x600898
|
| 21 |
|
|
[ ]*4e:[ ]+67 48 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%rax,0x600898
|
| 22 |
|
|
#pass
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.