OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [mips/] [rol-hw.d] - Blame information for rev 832

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
#objdump: -dr --prefix-addresses
2
#name: MIPS hardware rol/ror
3
#source: rol.s
4
#as: -32
5
 
6
# Test the rol and ror macros.
7
 
8
.*: +file format .*mips.*
9
 
10
Disassembly of section .text:
11
0+0000 <[^>]*> negu at,a1
12
0+0004 <[^>]*> rorv a0,a0,at
13
0+0008 <[^>]*> negu a0,a2
14
0+000c <[^>]*> rorv a0,a1,a0
15
0+0010 <[^>]*> ror  a0,a0,0x1f
16
0+0014 <[^>]*> ror  a0,a1,0x1f
17
0+0018 <[^>]*> ror  a0,a1,0x0
18
0+001c <[^>]*> rorv a0,a0,a1
19
0+0020 <[^>]*> rorv a0,a1,a2
20
0+0024 <[^>]*> ror  a0,a0,0x1
21
0+0028 <[^>]*> ror  a0,a1,0x1
22
0+002c <[^>]*> ror  a0,a1,0x0
23
0+0030 <[^>]*> ror  a0,a1,0x0
24
0+0034 <[^>]*> ror  a0,a1,0x1f
25
0+0038 <[^>]*> ror  a0,a1,0x1
26
0+003c <[^>]*> ror  a0,a1,0x0
27
0+0040 <[^>]*> ror  a0,a1,0x1
28
0+0044 <[^>]*> ror  a0,a1,0x1f
29
        ...

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.