OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [mips/] [vr4120-2.s] - Blame information for rev 38

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
# Test workarounds selected by -mfix-vr4120.
2
# Note that we only work around bugs gcc may generate.
3
 
4
r21:
5
        macc    $4,$5,$6
6
        div     $0,$7,$8
7
        or      $4,$5
8
 
9
        dmacc   $4,$5,$6
10
        div     $0,$7,$8
11
        or      $4,$5
12
 
13
        macc    $4,$5,$6
14
        divu    $0,$7,$8
15
        or      $4,$5
16
 
17
        dmacc   $4,$5,$6
18
        divu    $0,$7,$8
19
        or      $4,$5
20
 
21
        macc    $4,$5,$6
22
        ddiv    $0,$7,$8
23
        or      $4,$5
24
 
25
        dmacc   $4,$5,$6
26
        ddiv    $0,$7,$8
27
        or      $4,$5
28
 
29
        macc    $4,$5,$6
30
        ddivu   $0,$7,$8
31
        or      $4,$5
32
 
33
        dmacc   $4,$5,$6
34
        ddivu   $0,$7,$8
35
        or      $4,$5
36
 
37
r23:
38
        dmult   $4,$5
39
        dmult   $6,$7
40
        or      $4,$5
41
 
42
        dmultu  $4,$5
43
        dmultu  $6,$7
44
        or      $4,$5
45
 
46
        dmacc   $4,$5,$6
47
        dmacc   $6,$7,$8
48
        or      $4,$5
49
 
50
        dmult   $4,$5
51
        dmacc   $6,$7,$8
52
        or      $4,$5
53
 
54
r24:
55
        macc    $4,$5,$6
56
        mtlo    $7
57
 
58
        dmacc   $4,$5,$6
59
        mtlo    $7
60
 
61
        macc    $4,$5,$6
62
        mthi    $7
63
 
64
        dmacc   $4,$5,$6
65
        mthi    $7
66
 
67
vr4181a_md1:
68
        macc    $4,$5,$6
69
        mult    $4,$5
70
        or      $4,$5
71
 
72
        macc    $4,$5,$6
73
        multu   $4,$5
74
        or      $4,$5
75
 
76
        macc    $4,$5,$6
77
        dmult   $4,$5
78
        or      $4,$5
79
 
80
        macc    $4,$5,$6
81
        dmultu  $4,$5
82
        or      $4,$5
83
 
84
        dmacc   $4,$5,$6
85
        mult    $4,$5
86
        or      $4,$5
87
 
88
        dmacc   $4,$5,$6
89
        multu   $4,$5
90
        or      $4,$5
91
 
92
        dmacc   $4,$5,$6
93
        dmult   $4,$5
94
        or      $4,$5
95
 
96
        dmacc   $4,$5,$6
97
        dmultu  $4,$5
98
        or      $4,$5
99
 
100
vr4181a_md4:
101
        dmult   $4,$5
102
        macc    $4,$5,$6
103
        or      $4,$5
104
 
105
        dmultu  $4,$5
106
        macc    $4,$5,$6
107
        or      $4,$5
108
 
109
        div     $0,$4,$5
110
        macc    $4,$5,$6
111
        or      $4,$5
112
 
113
        divu    $0,$4,$5
114
        macc    $4,$5,$6
115
        or      $4,$5
116
 
117
        ddiv    $0,$4,$5
118
        macc    $4,$5,$6
119
        or      $4,$5
120
 
121
        ddivu   $0,$4,$5
122
        macc    $4,$5,$6
123
        or      $4,$5
124
 
125
        dmult   $4,$5
126
        dmacc   $4,$5,$6
127
        or      $4,$5
128
 
129
        dmultu  $4,$5
130
        dmacc   $4,$5,$6
131
        or      $4,$5
132
 
133
        div     $0,$4,$5
134
        dmacc   $4,$5,$6
135
        or      $4,$5
136
 
137
        divu    $0,$4,$5
138
        dmacc   $4,$5,$6
139
        or      $4,$5
140
 
141
        ddiv    $0,$4,$5
142
        dmacc   $4,$5,$6
143
        or      $4,$5
144
 
145
        ddivu   $0,$4,$5
146
        dmacc   $4,$5,$6
147
        or      $4,$5

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.