OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [mn10300/] [am33_2.s] - Blame information for rev 830

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius 
        .text
2 
        .am33
3 
        mov r0,r1
4 
        ext r2
5 
        extb r3,r4
6 
        extbu r4,r5
7 
        exth r6,r7
8 
        exthu r7,r8
9 
        clr r9
10 
        add r10,r11
11 
        addc r12,r13
12 
        sub r14,r15
13 
        subc r15,r14
14 
        inc r13
15 
        inc4 r12
16 
        cmp r11,r10
17 
        mov xr0, r1
18 
        mov r1, xr2
19 
        and r0,r1
20 
        or r2,r3
21 
        xor r4,r5
22 
        not r6
23 
        asr r7,r8
24 
        lsr r9,r10
25 
        asl r11,r12
26 
        asl2 r13
27 
        ror r14
28 
        rol r15
29 
        mul r1,r2
30 
        mulu r3,r4
31 
        div r5,r6
32 
        divu r7,r8
33 
        mov (r1),r2
34 
        mov r3,(r4)
35 
        movbu (r5),r6
36 
        movbu r7,(r8)
37 
        movhu (r9),r10
38 
        movhu r11,(r12)
39 
        mov (r1+),r2
40 
        mov r3,(r4+)
41 
        mov (sp),r5
42 
        mov r6,(sp)
43 
        movbu (sp),r7
44 
        movbu r8,(sp)
45 
        movhu (sp),r9
46 
        movhu r10,(sp)
47 
        movhu (r6+),r7
48 
        movhu r8,(r9+)
49 
        mac r1,r2
50 
        macu r3,r4
51 
        macb r5,r6
52 
        macbu r7,r8
53 
        mach r9,r10
54 
        machu r11,r12
55 
        dmach r13,r14
56 
        dmachu r15,r14
57 
        dmulh r13,r12
58 
        dmulhu r11,r10
59 
        sat16 r9,r8
60 
        mcste r7,r6
61 
        swap r5,r4
62 
        swaph r3,r2
63 
        swhw  r1,r0
64 
        bsch r1,r2

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.