OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [msp430/] [opcode.s] - Blame information for rev 856

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
        .arch msp430x123
2
        .text
3
        .p2align 1,0
4
 
5
.global foo
6
foo:
7
        and     #1, r11
8
        inv     r10
9
        xor     #0x00ff, r11
10
        bis     #8,     r12
11
        bit     #0x10,  r13
12
        bic     #0xa0, r14
13
        cmp     #0, r15
14
        sub     #1, r10
15
        subc    #0, r11
16
        add     #1, r12
17
        addc    #2, r13
18
        push    r14
19
        pop     r15
20
        sxt     r10
21
        rra     r11
22
        swpb    r12
23
        rrc     r13
24
        ret
25
 
26
        .p2align 1,0
27
.global main
28
        .type   main,@function
29
main:
30
        mov     #(__stack-0), r1
31
        call    #foo
32
        mov     &a, r14
33
        mov     r14, r15
34
        rla     r15
35
        subc    r15, r15
36
        inv     r15
37
        call    #__floatsisf
38
        mov     r14, &c
39
        mov     r15, &c+2
40
        mov     &b, r14
41
        mov     r14, r15
42
        rla     r15
43
        subc    r15, r15
44
        inv     r15
45
        call    #__floatsisf
46
        mov     r14, &d
47
        mov     r15, &d+2
48
        mov     #llo(240), r15
49
        br      #__stop_progExec__
50
        .comm a,2,2
51
        .comm b,2,2
52
        .comm c,4,2
53
        .comm d,4,2
54
 
55
        ;; This next instruction triggered a bug which
56
        ;; was fixed by a patch to msp430-dis.c on Jan 2, 2004
57
        add     &0x200, &0x172

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.