OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gprof/] [sparc.c] - Blame information for rev 816

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
/*
2
 * Copyright (c) 1983, 1993
3
 *      The Regents of the University of California.  All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 * 1. Redistributions of source code must retain the above copyright
9
 *    notice, this list of conditions and the following disclaimer.
10
 * 2. Redistributions in binary form must reproduce the above copyright
11
 *    notice, this list of conditions and the following disclaimer in the
12
 *    documentation and/or other materials provided with the distribution.
13
 * 3. Neither the name of the University nor the names of its contributors
14
 *    may be used to endorse or promote products derived from this software
15
 *    without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27
 * SUCH DAMAGE.
28
 */
29
#include "gprof.h"
30
#include "search_list.h"
31
#include "source.h"
32
#include "symtab.h"
33
#include "cg_arcs.h"
34
#include "corefile.h"
35
#include "hist.h"
36
 
37
    /*
38
     *        opcode of the `callf' instruction
39
     */
40
#define CALL    (0xc0000000)
41
 
42
void sparc_find_call (Sym *, bfd_vma, bfd_vma);
43
 
44
void
45
sparc_find_call (Sym *parent, bfd_vma p_lowpc, bfd_vma p_highpc)
46
{
47
  bfd_vma pc, dest_pc;
48
  unsigned int insn;
49
  Sym *child;
50
 
51
  DBG (CALLDEBUG, printf ("[find_call] %s: 0x%lx to 0x%lx\n",
52
                          parent->name, (unsigned long) p_lowpc,
53
                          (unsigned long) p_highpc));
54
  for (pc = (p_lowpc + 3) & ~(bfd_vma) 3; pc < p_highpc; pc += 4)
55
    {
56
      insn = bfd_get_32 (core_bfd, ((unsigned char *) core_text_space
57
                                    + pc - core_text_sect->vma));
58
      if (insn & CALL)
59
        {
60
          DBG (CALLDEBUG,
61
               printf ("[find_call] 0x%lx: callf", (unsigned long) pc));
62
          /*
63
           * Regular pc relative addressing check that this is the
64
           * address of a function.
65
           */
66
          dest_pc = pc + (((bfd_signed_vma) (insn & 0x3fffffff)
67
                           ^ 0x20000000) - 0x20000000);
68
          if (hist_check_address (dest_pc))
69
            {
70
              child = sym_lookup (&symtab, dest_pc);
71
              DBG (CALLDEBUG,
72
                   printf ("\tdest_pc=0x%lx, (name=%s, addr=0x%lx)\n",
73
                           (unsigned long) dest_pc, child->name,
74
                           (unsigned long) child->addr));
75
              if (child->addr == dest_pc)
76
                {
77
                  /* a hit:  */
78
                  arc_add (parent, child, (unsigned long) 0);
79
                  continue;
80
                }
81
            }
82
          /*
83
           * Something funny going on.
84
           */
85
          DBG (CALLDEBUG, printf ("\tbut it's a botch\n"));
86
        }
87
    }
88
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.