OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [ld/] [scripttempl/] [elf32xc16x.sc] - Blame information for rev 866

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
cat <
2
OUTPUT_FORMAT("${OUTPUT_FORMAT}")
3
OUTPUT_ARCH(${ARCH})
4
ENTRY("_start")
5
MEMORY
6
{
7
 
8
        vectarea : o =0x00000, l = 0x0300
9
 
10
        introm    : o = 0x00400, l = 0x16000
11
        /* The stack starts at the top of main ram.  */
12
 
13
        dram   : o = 0x8000 , l = 0xffff
14
        /* At the very top of the address space is the 8-bit area.  */
15
 
16
         ldata  : o =0x4000 ,l = 0x0200
17
}
18
 
19
SECTIONS
20
{
21
.init :
22
        {
23
          *(.init)
24
        } ${RELOCATING+ >introm}
25
 
26
.text :
27
        {
28
          *(.rodata)
29
          *(.text.*)
30
          *(.text)
31
                  ${RELOCATING+ _etext = . ; }
32
        } ${RELOCATING+ > introm}
33
.data :
34
        {
35
          *(.data)
36
          *(.data.*)
37
 
38
          ${RELOCATING+ _edata = . ; }
39
        } ${RELOCATING+ > dram}
40
 
41
.bss :
42
        {
43
          ${RELOCATING+ _bss_start = . ;}
44
          *(.bss)
45
          *(COMMON)
46
          ${RELOCATING+ _end = . ;  }
47
        } ${RELOCATING+ > dram}
48
 
49
 .ldata :
50
         {
51
          *(.ldata)
52
         } ${RELOCATING+ > ldata}
53
 
54
 
55
  .vects :
56
          {
57
          *(.vects)
58
       } ${RELOCATING+ > vectarea}
59
 
60
}
61
EOF

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.