OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [ld/] [testsuite/] [ld-arm/] [arm-lib-plt32.d] - Blame information for rev 156

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
 
2
tmpdir/arm-lib-plt32.so:     file format elf32-(little|big)arm
3
architecture: arm, flags 0x00000150:
4
HAS_SYMS, DYNAMIC, D_PAGED
5
start address 0x.*
6
 
7
Disassembly of section .plt:
8
 
9
.* <.plt>:
10
 .*:    e52de004        push    {lr}            ; \(str lr, \[sp, #-4\]!\)
11
 .*:    e59fe004        ldr     lr, \[pc, #4\]  ; .* 
12
 .*:    e08fe00e        add     lr, pc, lr
13
 .*:    e5bef008        ldr     pc, \[lr, #8\]!
14
 .*:    .*
15
 .*:    e28fc6.*        add     ip, pc, #.*     ; 0x.*
16
 .*:    e28cca.*        add     ip, ip, #.*     ; 0x.*
17
 .*:    e5bcf.*         ldr     pc, \[ip, #.*\]!
18
Disassembly of section .text:
19
 
20
.* :
21
 .*:    e1a0c00d        mov     ip, sp
22
 .*:    e92dd800        push    {fp, ip, lr, pc}
23
 .*:    ebfffff9        bl      .* 
24
 .*:    e89d6800        ldm     sp, {fp, sp, lr}
25
 .*:    e12fff1e        bx      lr
26
 
27
.* :
28
 .*:    e12fff1e        bx      lr

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.