URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [ld/] [testsuite/] [ld-arm/] [armthumb-lib.d] - Blame information for rev 38

Line No.	Rev	Author	Line
1	38	julius
2			`tmpdir/armthumb-lib.so: file format elf32-(little\|big)arm`
3			`architecture: arm, flags 0x00000150:`
4			`HAS_SYMS, DYNAMIC, D_PAGED`
5			`start address 0x.*`
6
7			`Disassembly of section .plt:`
8
9			`.* <.plt>:`
10			`.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)`
11			`.: e59fe004 ldr lr, \[pc, #4\] ; .`
12			`.*: e08fe00e add lr, pc, lr`
13			`.*: e5bef008 ldr pc, \[lr, #8\]!`
14			`.: .`
15			`.: e28fc6. add ip, pc, #.* ; 0x.*`
16			`.: e28cca. add ip, ip, #.* ; 0x.*`
17			`.: e5bcf. ldr pc, \[ip, #.*\]!`
18			`Disassembly of section .text:`
19
20			`.* :`
21			`.*: e1a0c00d mov ip, sp`
22			`.*: e92dd800 push {fp, ip, lr, pc}`
23			`.: ebfffff. bl .`
24			`.*: e89d6800 ldm sp, {fp, sp, lr}`
25			`.*: e12fff1e bx lr`
26			`.*: e1a00000 nop \(mov r0,r0\)`
27			`.*: e1a00000 nop \(mov r0,r0\)`
28			`.*: e1a00000 nop \(mov r0,r0\)`
29
30			`.* <__real_lib_func2>:`
31			`.*: 4770 bx lr`
32			`.*: 46c0 nop \(mov r8, r8\)`
33			`.*: 46c0 nop \(mov r8, r8\)`
34			`.*: 46c0 nop \(mov r8, r8\)`
35			`.*: 46c0 nop \(mov r8, r8\)`
36			`.*: 46c0 nop \(mov r8, r8\)`
37			`.*: 46c0 nop \(mov r8, r8\)`
38			`.*: 46c0 nop \(mov r8, r8\)`
39
40			`.* :`
41			`.: e59fc004 ldr ip, \[pc, #4\] ; .`
42			`.*: e08cc00f add ip, ip, pc`
43			`.*: e12fff1c bx ip`
44			`.: ffffffe5 .`