OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [ld/] [testsuite/] [ld-mips-elf/] [mips16-intermix.d] - Blame information for rev 825

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius 
 
2 
.*: +file format elf.*mips
3 
 
4 
SYMBOL TABLE:
5 
#...
6 
.* l     F .text        0+[0-9a-f]+ m32_static_l
7 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static_l
8 
.* l     F .text        0+[0-9a-f]+ m32_static1_l
9 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static1_l
10 
.* l     F .text        0+[0-9a-f]+ m32_static32_l
11 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static32_l
12 
.* l     F .text        0+[0-9a-f]+ m32_static16_l
13 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static16_l
14 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_d
15 
.* l     F .text        0+[0-9a-f]+ m32_static_d
16 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static_d
17 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static_d
18 
.* l     F .text        0+[0-9a-f]+ m32_static1_d
19 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static1_d
20 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static1_d
21 
.* l     F .text        0+[0-9a-f]+ m32_static32_d
22 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static32_d
23 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static32_d
24 
.* l     F .text        0+[0-9a-f]+ m32_static16_d
25 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static16_d
26 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static16_d
27 
.* l     F .text        0+[0-9a-f]+ m32_static_ld
28 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static_ld
29 
.* l     F .text        0+[0-9a-f]+ m32_static1_ld
30 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static1_ld
31 
.* l     F .text        0+[0-9a-f]+ m32_static32_ld
32 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static32_ld
33 
.* l     F .text        0+[0-9a-f]+ m32_static16_ld
34 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static16_ld
35 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_dl
36 
.* l     F .text        0+[0-9a-f]+ m32_static_dl
37 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static_dl
38 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static_dl
39 
.* l     F .text        0+[0-9a-f]+ m32_static1_dl
40 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static1_dl
41 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static1_dl
42 
.* l     F .text        0+[0-9a-f]+ m32_static32_dl
43 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static32_dl
44 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static32_dl
45 
.* l     F .text        0+[0-9a-f]+ m32_static16_dl
46 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static16_dl
47 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static16_dl
48 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_dlld
49 
.* l     F .text        0+[0-9a-f]+ m32_static_dlld
50 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static_dlld
51 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static_dlld
52 
.* l     F .text        0+[0-9a-f]+ m32_static1_dlld
53 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static1_dlld
54 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static1_dlld
55 
.* l     F .text        0+[0-9a-f]+ m32_static32_dlld
56 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static32_dlld
57 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static32_dlld
58 
.* l     F .text        0+[0-9a-f]+ m32_static16_dlld
59 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static16_dlld
60 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static16_dlld
61 
.* l     F .text        0+[0-9a-f]+ m32_static_d_l
62 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static_d_l
63 
.* l     F .text        0+[0-9a-f]+ m32_static1_d_l
64 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static1_d_l
65 
.* l     F .text        0+[0-9a-f]+ m32_static32_d_l
66 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static32_d_l
67 
.* l     F .text        0+[0-9a-f]+ m32_static16_d_l
68 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static16_d_l
69 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_d_d
70 
.* l     F .text        0+[0-9a-f]+ m32_static_d_d
71 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static_d_d
72 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static_d_d
73 
.* l     F .text        0+[0-9a-f]+ m32_static1_d_d
74 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static1_d_d
75 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static1_d_d
76 
.* l     F .text        0+[0-9a-f]+ m32_static32_d_d
77 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static32_d_d
78 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static32_d_d
79 
.* l     F .text        0+[0-9a-f]+ m32_static16_d_d
80 
.* l     F .text        0+[0-9a-f]+ 0xf0 m16_static16_d_d
81 
.* l     F .text        0+[0-9a-f]+ __fn_stub_m16_static16_d_d
82 
#...
83 
.* l     F .text        0+[0-9a-f]+ __call_stub_m32_static1_d
84 
.* l     F .text        0+[0-9a-f]+ __call_stub_m16_static1_d
85 
.* l     F .text        0+[0-9a-f]+ __call_stub_m32_static1_dl
86 
.* l     F .text        0+[0-9a-f]+ __call_stub_m16_static1_dl
87 
.* l     F .text        0+[0-9a-f]+ __call_stub_m32_static1_dlld
88 
.* l     F .text        0+[0-9a-f]+ __call_stub_m16_static1_dlld
89 
.* l     F .text        0+[0-9a-f]+ __call_stub_fp_m32_static1_d_l
90 
.* l     F .text        0+[0-9a-f]+ __call_stub_fp_m16_static1_d_l
91 
.* l     F .text        0+[0-9a-f]+ __call_stub_fp_m32_static1_d_d
92 
.* l     F .text        0+[0-9a-f]+ __call_stub_fp_m16_static1_d_d
93 
.* l     F .text        0+[0-9a-f]+ __call_stub_m32_static16_d
94 
.* l     F .text        0+[0-9a-f]+ __call_stub_m16_static16_d
95 
.* l     F .text        0+[0-9a-f]+ __call_stub_m32_static16_dl
96 
.* l     F .text        0+[0-9a-f]+ __call_stub_m16_static16_dl
97 
.* l     F .text        0+[0-9a-f]+ __call_stub_m32_static16_dlld
98 
.* l     F .text        0+[0-9a-f]+ __call_stub_m16_static16_dlld
99 
.* l     F .text        0+[0-9a-f]+ __call_stub_fp_m32_static16_d_l
100 
.* l     F .text        0+[0-9a-f]+ __call_stub_fp_m16_static16_d_l
101 
.* l     F .text        0+[0-9a-f]+ __call_stub_fp_m32_static16_d_d
102 
.* l     F .text        0+[0-9a-f]+ __call_stub_fp_m16_static16_d_d
103 
#...
104 
.* g     F .text        0+[0-9a-f]+ m32_ld
105 
#...
106 
.* g     F .text        0+[0-9a-f]+ m32_d_l
107 
.* g     F .text        0+[0-9a-f]+ 0xf0 m16_d_d
108 
.* g     F .text        0+[0-9a-f]+ 0xf0 m16_d
109 
#...
110 
.* g     F .text        0+[0-9a-f]+ 0xf0 f16
111 
#...
112 
.* g     F .text        0+[0-9a-f]+ m32_d
113 
#...
114 
.* g     F .text        0+[0-9a-f]+ 0xf0 m16_dl
115 
#...
116 
.* g     F .text        0+[0-9a-f]+ f32
117 
#...
118 
.* g     F .text        0+[0-9a-f]+ 0xf0 m16_l
119 
#...
120 
.* g     F .text        0+[0-9a-f]+ 0xf0 m16_ld
121 
#...
122 
.* g     F .text        0+[0-9a-f]+ 0xf0 m16_dlld
123 
.* g     F .text        0+[0-9a-f]+ m32_d_d
124 
#...
125 
.* g     F .text        0+[0-9a-f]+ m32_dl
126 
#...
127 
.* g     F .text        0+[0-9a-f]+ m32_dlld
128 
#...
129 
.* g     F .text        0+[0-9a-f]+ 0xf0 m16_d_l
130 
#...
131 
.* g     F .text        0+[0-9a-f]+ m32_l
132 
#pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.