OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [ld/] [testsuite/] [ld-mips-elf/] [reloc-1-n64.d] - Blame information for rev 38

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius 
#source: reloc-1a.s -mabi=64 -EB
2 
#source: reloc-1b.s -mabi=64 -EB
3 
#ld: -melf64btsmip -r
4 
#readelf: --relocs
5 
 
6 
Relocation section '\.rela\.text' .*
7 
.*
8 
#
9 
# Relocations against tstarta
10 
#
11 
.* R_MIPS_HI16 .* \.text \+ f+7ff0
12 
.* R_MIPS_NONE *
13 
.* R_MIPS_NONE *
14 
.* R_MIPS_LO16 .* \.text \+ f+7ff0
15 
.* R_MIPS_NONE *
16 
.* R_MIPS_NONE *
17 
.* R_MIPS_HI16 .* \.text \+ f+8000
18 
.* R_MIPS_NONE *
19 
.* R_MIPS_NONE *
20 
.* R_MIPS_LO16 .* \.text \+ f+8000
21 
.* R_MIPS_NONE *
22 
.* R_MIPS_NONE *
23 
.* R_MIPS_HI16 .* \.text \+ 0
24 
.* R_MIPS_NONE *
25 
.* R_MIPS_NONE *
26 
.* R_MIPS_LO16 .* \.text \+ 0
27 
.* R_MIPS_NONE *
28 
.* R_MIPS_NONE *
29 
.* R_MIPS_HI16 .* \.text \+ 7ff0
30 
.* R_MIPS_NONE *
31 
.* R_MIPS_NONE *
32 
.* R_MIPS_LO16 .* \.text \+ 7ff0
33 
.* R_MIPS_NONE *
34 
.* R_MIPS_NONE *
35 
.* R_MIPS_HI16 .* \.text \+ 8010
36 
.* R_MIPS_NONE *
37 
.* R_MIPS_NONE *
38 
.* R_MIPS_LO16 .* \.text \+ 8010
39 
.* R_MIPS_NONE *
40 
.* R_MIPS_NONE *
41 
#
42 
# Relocations against t32a
43 
#
44 
.* R_MIPS_HI16 .* \.text \+ f+8010
45 
.* R_MIPS_NONE *
46 
.* R_MIPS_NONE *
47 
.* R_MIPS_LO16 .* \.text \+ f+8010
48 
.* R_MIPS_NONE *
49 
.* R_MIPS_NONE *
50 
.* R_MIPS_HI16 .* \.text \+ f+8020
51 
.* R_MIPS_NONE *
52 
.* R_MIPS_NONE *
53 
.* R_MIPS_LO16 .* \.text \+ f+8020
54 
.* R_MIPS_NONE *
55 
.* R_MIPS_NONE *
56 
.* R_MIPS_HI16 .* \.text \+ 20
57 
.* R_MIPS_NONE *
58 
.* R_MIPS_NONE *
59 
.* R_MIPS_LO16 .* \.text \+ 20
60 
.* R_MIPS_NONE *
61 
.* R_MIPS_NONE *
62 
.* R_MIPS_HI16 .* \.text \+ 8010
63 
.* R_MIPS_NONE *
64 
.* R_MIPS_NONE *
65 
.* R_MIPS_LO16 .* \.text \+ 8010
66 
.* R_MIPS_NONE *
67 
.* R_MIPS_NONE *
68 
.* R_MIPS_HI16 .* \.text \+ 8030
69 
.* R_MIPS_NONE *
70 
.* R_MIPS_NONE *
71 
.* R_MIPS_LO16 .* \.text \+ 8030
72 
.* R_MIPS_NONE *
73 
.* R_MIPS_NONE *
74 
#
75 
# Relocations against _start
76 
#
77 
.* R_MIPS_HI16 .* _start \+ f+7ff0
78 
.* R_MIPS_NONE *
79 
.* R_MIPS_NONE *
80 
.* R_MIPS_LO16 .* _start \+ f+7ff0
81 
.* R_MIPS_NONE *
82 
.* R_MIPS_NONE *
83 
.* R_MIPS_HI16 .* _start \+ f+8000
84 
.* R_MIPS_NONE *
85 
.* R_MIPS_NONE *
86 
.* R_MIPS_LO16 .* _start \+ f+8000
87 
.* R_MIPS_NONE *
88 
.* R_MIPS_NONE *
89 
.* R_MIPS_HI16 .* _start \+ 0
90 
.* R_MIPS_NONE *
91 
.* R_MIPS_NONE *
92 
.* R_MIPS_LO16 .* _start \+ 0
93 
.* R_MIPS_NONE *
94 
.* R_MIPS_NONE *
95 
.* R_MIPS_HI16 .* _start \+ 7ff0
96 
.* R_MIPS_NONE *
97 
.* R_MIPS_NONE *
98 
.* R_MIPS_LO16 .* _start \+ 7ff0
99 
.* R_MIPS_NONE *
100 
.* R_MIPS_NONE *
101 
.* R_MIPS_HI16 .* _start \+ 8010
102 
.* R_MIPS_NONE *
103 
.* R_MIPS_NONE *
104 
.* R_MIPS_LO16 .* _start \+ 8010
105 
.* R_MIPS_NONE *
106 
.* R_MIPS_NONE *
107 
#
108 
# Relocations against tstarta
109 
#
110 
.* R_MIPS_GOT16 .* \.text \+ f+7ff0
111 
.* R_MIPS_NONE *
112 
.* R_MIPS_NONE *
113 
.* R_MIPS_LO16 .* \.text \+ f+7ff0
114 
.* R_MIPS_NONE *
115 
.* R_MIPS_NONE *
116 
.* R_MIPS_GOT16 .* \.text \+ f+8000
117 
.* R_MIPS_NONE *
118 
.* R_MIPS_NONE *
119 
.* R_MIPS_LO16 .* \.text \+ f+8000
120 
.* R_MIPS_NONE *
121 
.* R_MIPS_NONE *
122 
.* R_MIPS_GOT16 .* \.text \+ 0
123 
.* R_MIPS_NONE *
124 
.* R_MIPS_NONE *
125 
.* R_MIPS_LO16 .* \.text \+ 0
126 
.* R_MIPS_NONE *
127 
.* R_MIPS_NONE *
128 
.* R_MIPS_GOT16 .* \.text \+ 7ff0
129 
.* R_MIPS_NONE *
130 
.* R_MIPS_NONE *
131 
.* R_MIPS_LO16 .* \.text \+ 7ff0
132 
.* R_MIPS_NONE *
133 
.* R_MIPS_NONE *
134 
.* R_MIPS_GOT16 .* \.text \+ 8010
135 
.* R_MIPS_NONE *
136 
.* R_MIPS_NONE *
137 
.* R_MIPS_LO16 .* \.text \+ 8010
138 
.* R_MIPS_NONE *
139 
.* R_MIPS_NONE *
140 
#
141 
# Relocations against t32a
142 
#
143 
.* R_MIPS_GOT16 .* \.text \+ f+8010
144 
.* R_MIPS_NONE *
145 
.* R_MIPS_NONE *
146 
.* R_MIPS_LO16 .* \.text \+ f+8010
147 
.* R_MIPS_NONE *
148 
.* R_MIPS_NONE *
149 
.* R_MIPS_GOT16 .* \.text \+ f+8020
150 
.* R_MIPS_NONE *
151 
.* R_MIPS_NONE *
152 
.* R_MIPS_LO16 .* \.text \+ f+8020
153 
.* R_MIPS_NONE *
154 
.* R_MIPS_NONE *
155 
.* R_MIPS_GOT16 .* \.text \+ 20
156 
.* R_MIPS_NONE *
157 
.* R_MIPS_NONE *
158 
.* R_MIPS_LO16 .* \.text \+ 20
159 
.* R_MIPS_NONE *
160 
.* R_MIPS_NONE *
161 
.* R_MIPS_GOT16 .* \.text \+ 8010
162 
.* R_MIPS_NONE *
163 
.* R_MIPS_NONE *
164 
.* R_MIPS_LO16 .* \.text \+ 8010
165 
.* R_MIPS_NONE *
166 
.* R_MIPS_NONE *
167 
.* R_MIPS_GOT16 .* \.text \+ 8030
168 
.* R_MIPS_NONE *
169 
.* R_MIPS_NONE *
170 
.* R_MIPS_LO16 .* \.text \+ 8030
171 
.* R_MIPS_NONE *
172 
.* R_MIPS_NONE *
173 
#
174 
# Relocations against sdg
175 
#
176 
.* R_MIPS_GPREL16 .* sdg \+ f+fffc
177 
.* R_MIPS_NONE *
178 
.* R_MIPS_NONE *
179 
.* R_MIPS_GPREL16 .* sdg \+ 0
180 
.* R_MIPS_NONE *
181 
.* R_MIPS_NONE *
182 
.* R_MIPS_GPREL16 .* sdg \+ 4
183 
.* R_MIPS_NONE *
184 
.* R_MIPS_NONE *
185 
#
186 
# Relocations against sdla.  .sdata should be the first piece of gp-relative
187 
# data, which the linker script should put _gp - 0x7ff0.
188 
#
189 
.* R_MIPS_GPREL16 .* \.sdata \+ f+801c
190 
.* R_MIPS_NONE *
191 
.* R_MIPS_NONE *
192 
.* R_MIPS_GPREL16 .* \.sdata \+ f+8020
193 
.* R_MIPS_NONE *
194 
.* R_MIPS_NONE *
195 
.* R_MIPS_GPREL16 .* \.sdata \+ f+8024
196 
.* R_MIPS_NONE *
197 
.* R_MIPS_NONE *
198 
#
199 
# Relocations against tstarta
200 
#
201 
.* R_MIPS_26 .* \.text \+ f+fffc
202 
.* R_MIPS_NONE *
203 
.* R_MIPS_NONE *
204 
.* R_MIPS_26 .* \.text \+ 0
205 
.* R_MIPS_NONE *
206 
.* R_MIPS_NONE *
207 
.* R_MIPS_26 .* \.text \+ 4
208 
.* R_MIPS_NONE *
209 
.* R_MIPS_NONE *
210 
#
211 
# Relocations against t32a
212 
#
213 
.* R_MIPS_26 .* \.text \+ 1c
214 
.* R_MIPS_NONE *
215 
.* R_MIPS_NONE *
216 
.* R_MIPS_26 .* \.text \+ 20
217 
.* R_MIPS_NONE *
218 
.* R_MIPS_NONE *
219 
.* R_MIPS_26 .* \.text \+ 24
220 
.* R_MIPS_NONE *
221 
.* R_MIPS_NONE *
222 
#
223 
# Relocations against _start
224 
#
225 
.* R_MIPS_26 .* _start \+ f+fffc
226 
.* R_MIPS_NONE *
227 
.* R_MIPS_NONE *
228 
.* R_MIPS_26 .* _start \+ 0
229 
.* R_MIPS_NONE *
230 
.* R_MIPS_NONE *
231 
.* R_MIPS_26 .* _start \+ 4
232 
.* R_MIPS_NONE *
233 
.* R_MIPS_NONE *
234 
#
235 
# Relocations against tstartb
236 
#
237 
.* R_MIPS_HI16 .* \.text \+ 7fe0
238 
.* R_MIPS_NONE *
239 
.* R_MIPS_NONE *
240 
.* R_MIPS_LO16 .* \.text \+ 7fe0
241 
.* R_MIPS_NONE *
242 
.* R_MIPS_NONE *
243 
.* R_MIPS_HI16 .* \.text \+ 7ff0
244 
.* R_MIPS_NONE *
245 
.* R_MIPS_NONE *
246 
.* R_MIPS_LO16 .* \.text \+ 7ff0
247 
.* R_MIPS_NONE *
248 
.* R_MIPS_NONE *
249 
.* R_MIPS_HI16 .* \.text \+ fff0
250 
.* R_MIPS_NONE *
251 
.* R_MIPS_NONE *
252 
.* R_MIPS_LO16 .* \.text \+ fff0
253 
.* R_MIPS_NONE *
254 
.* R_MIPS_NONE *
255 
.* R_MIPS_HI16 .* \.text \+ 17fe0
256 
.* R_MIPS_NONE *
257 
.* R_MIPS_NONE *
258 
.* R_MIPS_LO16 .* \.text \+ 17fe0
259 
.* R_MIPS_NONE *
260 
.* R_MIPS_NONE *
261 
.* R_MIPS_HI16 .* \.text \+ 18000
262 
.* R_MIPS_NONE *
263 
.* R_MIPS_NONE *
264 
.* R_MIPS_LO16 .* \.text \+ 18000
265 
.* R_MIPS_NONE *
266 
.* R_MIPS_NONE *
267 
#
268 
# Relocations against t32b
269 
#
270 
.* R_MIPS_HI16 .* \.text \+ 8000
271 
.* R_MIPS_NONE *
272 
.* R_MIPS_NONE *
273 
.* R_MIPS_LO16 .* \.text \+ 8000
274 
.* R_MIPS_NONE *
275 
.* R_MIPS_NONE *
276 
.* R_MIPS_HI16 .* \.text \+ 8010
277 
.* R_MIPS_NONE *
278 
.* R_MIPS_NONE *
279 
.* R_MIPS_LO16 .* \.text \+ 8010
280 
.* R_MIPS_NONE *
281 
.* R_MIPS_NONE *
282 
.* R_MIPS_HI16 .* \.text \+ 10010
283 
.* R_MIPS_NONE *
284 
.* R_MIPS_NONE *
285 
.* R_MIPS_LO16 .* \.text \+ 10010
286 
.* R_MIPS_NONE *
287 
.* R_MIPS_NONE *
288 
.* R_MIPS_HI16 .* \.text \+ 18000
289 
.* R_MIPS_NONE *
290 
.* R_MIPS_NONE *
291 
.* R_MIPS_LO16 .* \.text \+ 18000
292 
.* R_MIPS_NONE *
293 
.* R_MIPS_NONE *
294 
.* R_MIPS_HI16 .* \.text \+ 18020
295 
.* R_MIPS_NONE *
296 
.* R_MIPS_NONE *
297 
.* R_MIPS_LO16 .* \.text \+ 18020
298 
.* R_MIPS_NONE *
299 
.* R_MIPS_NONE *
300 
#
301 
# Relocations against _start
302 
#
303 
.* R_MIPS_HI16 .* _start \+ f+7ff0
304 
.* R_MIPS_NONE *
305 
.* R_MIPS_NONE *
306 
.* R_MIPS_LO16 .* _start \+ f+7ff0
307 
.* R_MIPS_NONE *
308 
.* R_MIPS_NONE *
309 
.* R_MIPS_HI16 .* _start \+ f+8000
310 
.* R_MIPS_NONE *
311 
.* R_MIPS_NONE *
312 
.* R_MIPS_LO16 .* _start \+ f+8000
313 
.* R_MIPS_NONE *
314 
.* R_MIPS_NONE *
315 
.* R_MIPS_HI16 .* _start \+ 0
316 
.* R_MIPS_NONE *
317 
.* R_MIPS_NONE *
318 
.* R_MIPS_LO16 .* _start \+ 0
319 
.* R_MIPS_NONE *
320 
.* R_MIPS_NONE *
321 
.* R_MIPS_HI16 .* _start \+ 7ff0
322 
.* R_MIPS_NONE *
323 
.* R_MIPS_NONE *
324 
.* R_MIPS_LO16 .* _start \+ 7ff0
325 
.* R_MIPS_NONE *
326 
.* R_MIPS_NONE *
327 
.* R_MIPS_HI16 .* _start \+ 8010
328 
.* R_MIPS_NONE *
329 
.* R_MIPS_NONE *
330 
.* R_MIPS_LO16 .* _start \+ 8010
331 
.* R_MIPS_NONE *
332 
.* R_MIPS_NONE *
333 
#
334 
# Relocations against tstartb
335 
#
336 
.* R_MIPS_GOT16 .* \.text \+ 7fe0
337 
.* R_MIPS_NONE *
338 
.* R_MIPS_NONE *
339 
.* R_MIPS_LO16 .* \.text \+ 7fe0
340 
.* R_MIPS_NONE *
341 
.* R_MIPS_NONE *
342 
.* R_MIPS_GOT16 .* \.text \+ 7ff0
343 
.* R_MIPS_NONE *
344 
.* R_MIPS_NONE *
345 
.* R_MIPS_LO16 .* \.text \+ 7ff0
346 
.* R_MIPS_NONE *
347 
.* R_MIPS_NONE *
348 
.* R_MIPS_GOT16 .* \.text \+ fff0
349 
.* R_MIPS_NONE *
350 
.* R_MIPS_NONE *
351 
.* R_MIPS_LO16 .* \.text \+ fff0
352 
.* R_MIPS_NONE *
353 
.* R_MIPS_NONE *
354 
.* R_MIPS_GOT16 .* \.text \+ 17fe0
355 
.* R_MIPS_NONE *
356 
.* R_MIPS_NONE *
357 
.* R_MIPS_LO16 .* \.text \+ 17fe0
358 
.* R_MIPS_NONE *
359 
.* R_MIPS_NONE *
360 
.* R_MIPS_GOT16 .* \.text \+ 18000
361 
.* R_MIPS_NONE *
362 
.* R_MIPS_NONE *
363 
.* R_MIPS_LO16 .* \.text \+ 18000
364 
.* R_MIPS_NONE *
365 
.* R_MIPS_NONE *
366 
#
367 
# Relocations against t32b
368 
#
369 
.* R_MIPS_GOT16 .* \.text \+ 8000
370 
.* R_MIPS_NONE *
371 
.* R_MIPS_NONE *
372 
.* R_MIPS_LO16 .* \.text \+ 8000
373 
.* R_MIPS_NONE *
374 
.* R_MIPS_NONE *
375 
.* R_MIPS_GOT16 .* \.text \+ 8010
376 
.* R_MIPS_NONE *
377 
.* R_MIPS_NONE *
378 
.* R_MIPS_LO16 .* \.text \+ 8010
379 
.* R_MIPS_NONE *
380 
.* R_MIPS_NONE *
381 
.* R_MIPS_GOT16 .* \.text \+ 10010
382 
.* R_MIPS_NONE *
383 
.* R_MIPS_NONE *
384 
.* R_MIPS_LO16 .* \.text \+ 10010
385 
.* R_MIPS_NONE *
386 
.* R_MIPS_NONE *
387 
.* R_MIPS_GOT16 .* \.text \+ 18000
388 
.* R_MIPS_NONE *
389 
.* R_MIPS_NONE *
390 
.* R_MIPS_LO16 .* \.text \+ 18000
391 
.* R_MIPS_NONE *
392 
.* R_MIPS_NONE *
393 
.* R_MIPS_GOT16 .* \.text \+ 18020
394 
.* R_MIPS_NONE *
395 
.* R_MIPS_NONE *
396 
.* R_MIPS_LO16 .* \.text \+ 18020
397 
.* R_MIPS_NONE *
398 
.* R_MIPS_NONE *
399 
#
400 
# Relocations against sdg
401 
#
402 
.* R_MIPS_GPREL16 .* sdg \+ f+fffc
403 
.* R_MIPS_NONE *
404 
.* R_MIPS_NONE *
405 
.* R_MIPS_GPREL16 .* sdg \+ 0
406 
.* R_MIPS_NONE *
407 
.* R_MIPS_NONE *
408 
.* R_MIPS_GPREL16 .* sdg \+ 4
409 
.* R_MIPS_NONE *
410 
.* R_MIPS_NONE *
411 
#
412 
# Relocations against sdlb
413 
#
414 
.* R_MIPS_GPREL16 .* \.sdata \+ f+803c
415 
.* R_MIPS_NONE *
416 
.* R_MIPS_NONE *
417 
.* R_MIPS_GPREL16 .* \.sdata \+ f+8040
418 
.* R_MIPS_NONE *
419 
.* R_MIPS_NONE *
420 
.* R_MIPS_GPREL16 .* \.sdata \+ f+8044
421 
.* R_MIPS_NONE *
422 
.* R_MIPS_NONE *
423 
#
424 
# Relocations against tstartb
425 
#
426 
.* R_MIPS_26 .* \.text \+ ffec
427 
.* R_MIPS_NONE *
428 
.* R_MIPS_NONE *
429 
.* R_MIPS_26 .* \.text \+ fff0
430 
.* R_MIPS_NONE *
431 
.* R_MIPS_NONE *
432 
.* R_MIPS_26 .* \.text \+ fff4
433 
.* R_MIPS_NONE *
434 
.* R_MIPS_NONE *
435 
#
436 
# Relocations against t32b
437 
#
438 
.* R_MIPS_26 .* \.text \+ 1000c
439 
.* R_MIPS_NONE *
440 
.* R_MIPS_NONE *
441 
.* R_MIPS_26 .* \.text \+ 10010
442 
.* R_MIPS_NONE *
443 
.* R_MIPS_NONE *
444 
.* R_MIPS_26 .* \.text \+ 10014
445 
.* R_MIPS_NONE *
446 
.* R_MIPS_NONE *
447 
#
448 
# Relocations against _start
449 
#
450 
.* R_MIPS_26 .* _start \+ f+fffc
451 
.* R_MIPS_NONE *
452 
.* R_MIPS_NONE *
453 
.* R_MIPS_26 .* _start \+ 0
454 
.* R_MIPS_NONE *
455 
.* R_MIPS_NONE *
456 
.* R_MIPS_26 .* _start \+ 4
457 
.* R_MIPS_NONE *
458 
.* R_MIPS_NONE *
459 
#pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.