OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [ld/] [testsuite/] [ld-mmix/] [greg-3.d] - Blame information for rev 831

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
#source: greg-1.s
2
#source: gregget1.s
3
#source: start.s
4
#source: a.s
5
#as: -x
6
#ld: -m elf64mmix
7
#objdump: -dt
8
 
9
# A greg usage with an expanding insn.  The register reloc must be
10
# evaluated before the expanding reloc.  Here, it doesn't appear in the
11
# wrong order, and it doesn't seem like they would naturally appear in the
12
# wrong order, but anyway.
13
 
14
.*:     file format elf64-mmix
15
 
16
SYMBOL TABLE:
17
0+ l    d  \.text       0+ (|\.text)
18
0+7f0 l    d  \.MMIX\.reg_contents      0+ (|\.MMIX\.reg_contents)
19
0+10 g       \.text     0+ _start
20
0+fe g       \*REG\*    0+ areg
21
#...
22
0+14 g       \.text     0+ a
23
 
24
Disassembly of section \.text:
25
 
26
0+ <_start-0x10>:
27
   0:   e3fe0014        setl \$254,0x14
28
   4:   e6fe0000        incml \$254,0x0
29
   8:   e5fe0000        incmh \$254,0x0
30
   c:   e4fe0000        inch \$254,0x0
31
 
32
0+10 <_start>:
33
  10:   e3fd0001        setl \$253,0x1
34
 
35
0+14 :
36
  14:   e3fd0004        setl \$253,0x4

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.