OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [ld/] [testsuite/] [ld-powerpc/] [tlstoc.d] - Blame information for rev 156

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius 
#source: tlslib.s
2 
#source: tlstoc.s
3 
#as: -a64
4 
#ld: -melf64ppc
5 
#objdump: -dr
6 
#target: powerpc64*-*-*
7 
 
8 
.*: +file format elf64-powerpc
9 
 
10 
Disassembly of section \.text:
11 
 
12 
.* <\.__tls_get_addr>:
13 
.*      4e 80 00 20     blr
14 
 
15 
.* <_start>:
16 
.*      3c 6d 00 00     addis   r3,r13,0
17 
.*      60 00 00 00     nop
18 
.*      38 63 90 40     addi    r3,r3,-28608
19 
.*      3c 6d 00 00     addis   r3,r13,0
20 
.*      60 00 00 00     nop
21 
.*      38 63 10 00     addi    r3,r3,4096
22 
.*      3c 6d 00 00     addis   r3,r13,0
23 
.*      60 00 00 00     nop
24 
.*      38 63 90 48     addi    r3,r3,-28600
25 
.*      3c 6d 00 00     addis   r3,r13,0
26 
.*      60 00 00 00     nop
27 
.*      38 63 10 00     addi    r3,r3,4096
28 
.*      39 23 80 50     addi    r9,r3,-32688
29 
.*      3d 23 00 00     addis   r9,r3,0
30 
.*      81 49 80 58     lwz     r10,-32680\(r9\)
31 
.*      e9 22 80 40     ld      r9,-32704\(r2\)
32 
.*      7d 49 18 2a     ldx     r10,r9,r3
33 
.*      3d 2d 00 00     addis   r9,r13,0
34 
.*      a1 49 90 68     lhz     r10,-28568\(r9\)
35 
.*      89 4d 90 70     lbz     r10,-28560\(r13\)
36 
.*      3d 2d 00 00     addis   r9,r13,0
37 
.*      99 49 90 78     stb     r10,-28552\(r9\)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.