OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [ld/] [testsuite/] [ld-spu/] [ovl.d] - Blame information for rev 866

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
#source: ovl.s
2
#ld: -N -T ovl1.lnk -T ovl.lnk --emit-relocs
3
#objdump: -D -r
4
 
5
.*elf32-spu
6
 
7
Disassembly of section \.text:
8
 
9
00000100 <_start>:
10
.*      ai      \$1,\$1,-32
11
.*      xor     \$0,\$0,\$0
12
.*      stqd    \$0,0\(\$1\)
13
.*      stqd    \$0,16\(\$1\)
14
.*      brsl    \$0,.* <00000000\.ovl_call\.f1_a1>.*
15
.*SPU_REL16     f1_a1
16
.*      brsl    \$0,.* <00000000\.ovl_call\.f2_a1>.*
17
.*SPU_REL16     f2_a1
18
.*      brsl    \$0,.* <00000000\.ovl_call\.f1_a2>.*
19
.*SPU_REL16     f1_a2
20
#.*     ila     \$9,328 # 148
21
.*      ila     \$9,352 # 160
22
.*SPU_ADDR18    f2_a2
23
.*      bisl    \$0,\$9
24
.*      ai      \$1,\$1,32      # 20
25
.*      br      100 <_start>    # 100
26
.*SPU_REL16     _start
27
 
28
0000012c :
29
.*      bi      \$0
30
 
31
#00000130 <00000000\.ovl_call\.f1_a1>:
32
#.*     brsl    \$75,.* <__ovly_load>.*
33
#.*00 04 04 00.*
34
#
35
#00000138 <00000000\.ovl_call\.f2_a1>:
36
#.*     brsl    \$75,.* <__ovly_load>.*
37
#.*00 04 04 04.*
38
#
39
#00000140 <00000000\.ovl_call\.f1_a2>:
40
#.*     brsl    \$75,.* <__ovly_load>.*
41
#.*00 08 04 00.*
42
#
43
#00000148 <00000000\.ovl_call\.f2_a2>:
44
#.*     brsl    \$75,.* <__ovly_load>.*
45
#.*00 08 04 24.*
46
#
47
#00000150 <00000000\.ovl_call\.f4_a1>:
48
#.*     brsl    \$75,.* <__ovly_load>.*
49
#.*00 04 04 10.*
50
#
51
#00000158 <00000000.ovl_call.14:8>:
52
#.*     brsl    \$75,.* <__ovly_load>.*
53
#.*00 08 04 34.*
54
 
55
00000130 <00000000\.ovl_call\.f1_a1>:
56
.*      ila     \$78,1
57
.*      lnop
58
.*      ila     \$79,1024       # 400
59
.*      br      .* <__ovly_load>.*
60
 
61
00000140 <00000000\.ovl_call\.f2_a1>:
62
.*      ila     \$78,1
63
.*      lnop
64
.*      ila     \$79,1028       # 404
65
.*      br      .* <__ovly_load>.*
66
 
67
00000150 <00000000.ovl_call.f1_a2>:
68
.*      ila     \$78,2
69
.*      lnop
70
.*      ila     \$79,1024       # 400
71
.*      br      .* <__ovly_load>.*
72
 
73
00000160 <00000000\.ovl_call\.f2_a2>:
74
.*      ila     \$78,2
75
.*      lnop
76
.*      ila     \$79,1060       # 424
77
.*      br      .* <__ovly_load>.*
78
 
79
00000170 <00000000\.ovl_call\.f4_a1>:
80
.*      ila     \$78,1
81
.*      lnop
82
.*      ila     \$79,1040       # 410
83
.*      br      .* <__ovly_load>.*
84
 
85
00000180 <00000000.ovl_call.14:8>:
86
.*      ila     \$78,2
87
.*      lnop
88
.*      ila     \$79,1076       # 434
89
.*      br      .* <__ovly_load>.*
90
 
91
#...
92
[0-9a-f]+ <__ovly_return>:
93
#...
94
[0-9a-f]+ <__ovly_load>:
95
#...
96
[0-9a-f]+ <_ovly_debug_event>:
97
#...
98
Disassembly of section \.ov_a1:
99
 
100
00000400 :
101
.*      br      .* .*
102
.*SPU_REL16     f3_a1
103
 
104
00000404 :
105
#.*     ila     \$3,336 # 150
106
.*      ila     \$3,368 # 170
107
.*SPU_ADDR18    f4_a1
108
.*      bi      \$0
109
 
110
0000040c :
111
.*      bi      \$0
112
 
113
00000410 :
114
.*      bi      \$0
115
        \.\.\.
116
Disassembly of section \.ov_a2:
117
 
118
00000400 :
119
.*      stqd    \$0,16\(\$1\)
120
.*      stqd    \$1,-32\(\$1\)
121
.*      ai      \$1,\$1,-32
122
.*      brsl    \$0,12c         # 12c
123
.*SPU_REL16     f0
124
.*      brsl    \$0,130 <00000000\.ovl_call\.f1_a1>        # 130
125
.*SPU_REL16     f1_a1
126
.*      brsl    \$0,430         # 430
127
.*SPU_REL16     f3_a2
128
.*      lqd     \$0,48\(\$1\)   # 30
129
.*      ai      \$1,\$1,32      # 20
130
.*      bi      \$0
131
 
132
00000424 :
133
.*      ilhu    \$3,0
134
.*SPU_ADDR16_HI f4_a2
135
#.*     iohl    \$3,344 # 158
136
.*      iohl    \$3,384 # 180
137
.*SPU_ADDR16_LO f4_a2
138
.*      bi      \$0
139
 
140
00000430 :
141
.*      bi      \$0
142
 
143
00000434 :
144
.*      br      .* .*
145
.*SPU_REL16     f3_a2
146
        \.\.\.
147
Disassembly of section .data:
148
 
149
00000440 <_ovly_table-0x10>:
150
 440:   00 00 00 00 .*
151
 444:   00 00 00 01 .*
152
        \.\.\.
153
00000450 <_ovly_table>:
154
 450:   00 00 04 00 .*
155
 454:   00 00 00 20 .*
156
# 458:  00 00 03 40 .*
157
 458:   00 00 03 70 .*
158
 45c:   00 00 00 01 .*
159
 460:   00 00 04 00 .*
160
 464:   00 00 00 40 .*
161
# 468:  00 00 03 60 .*
162
 468:   00 00 03 90 .*
163
 46c:   00 00 00 01 .*
164
 
165
00000470 <_ovly_buf_table>:
166
 470:   00 00 00 00 .*
167
 
168
Disassembly of section \.toe:
169
 
170
00000480 <_EAR_>:
171
        \.\.\.
172
Disassembly of section \.note\.spu_name:
173
 
174
.* <\.note\.spu_name>:
175
.*:     00 00 00 08 .*
176
.*:     00 00 00 0c .*
177
.*:     00 00 00 01 .*
178
.*:     53 50 55 4e .*
179
.*:     41 4d 45 00 .*
180
.*:     74 6d 70 64 .*
181
.*:     69 72 2f 64 .*
182
.*:     75 6d 70 00 .*

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.