OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [ld/] [testsuite/] [ld-v850/] [split-lo16.s] - Blame information for rev 840

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius 
        movhi   hi(lo16_nocarry),r0,r1
2 
        addi    lo(lo16_nocarry),r1,r2
3 
        ld.bu   lo(lo16_nocarry)[r1],r2
4 
        movhi   hi(lo16_nocarry + 0x18200),r0,r1
5 
        addi    lo(lo16_nocarry + 0x18200),r1,r2
6 
        ld.bu   lo(lo16_nocarry + 0x18200)[r1],r2
7 
        movhi   hi(split_lo16_nocarry),r0,r1
8 
        ld.bu   lo(split_lo16_nocarry)[r1],r2
9 
        addi    lo(split_lo16_nocarry),r1,r2
10 
        movhi   hi(split_lo16_nocarry + 0x18200),r0,r1
11 
        ld.bu   lo(split_lo16_nocarry + 0x18200)[r1],r2
12 
        addi    lo(split_lo16_nocarry + 0x18200),r1,r2
13 
        movhi   hi(lo16_carry),r0,r1
14 
        addi    lo(lo16_carry),r1,r2
15 
        ld.bu   lo(lo16_carry)[r1],r2
16 
        movhi   hi(split_lo16_carry),r0,r1
17 
        ld.bu   lo(split_lo16_carry)[r1],r2
18 
        addi    lo(split_lo16_carry),r1,r2
19 
        movhi   hi(odd),r0,r1
20 
        ld.bu   lo(odd)[r1],r2

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.