OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [opcodes/] [arc-dis.h] - Blame information for rev 866

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 julius
/* Disassembler structures definitions for the ARC.
2
   Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2007
3
   Free Software Foundation, Inc.
4
   Contributed by Doug Evans (dje@cygnus.com).
5
 
6
   This file is part of libopcodes.
7
 
8
   This library is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3, or (at your option)
11
   any later version.
12
 
13
   It is distributed in the hope that it will be useful, but WITHOUT
14
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
   License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this program; if not, write to the Free Software Foundation,
20
   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
21
 
22
#ifndef ARCDIS_H
23
#define ARCDIS_H
24
 
25
enum
26
{
27
  BR_exec_when_no_jump,
28
  BR_exec_always,
29
  BR_exec_when_jump
30
};
31
 
32
enum Flow
33
{
34
  noflow,
35
  direct_jump,
36
  direct_call,
37
  indirect_jump,
38
  indirect_call,
39
  invalid_instr
40
};
41
 
42
enum { no_reg = 99 };
43
enum { allOperandsSize = 256 };
44
 
45
struct arcDisState
46
{
47
  void *_this;
48
  int instructionLen;
49
  void (*err)(void*, const char*);
50
  const char *(*coreRegName)(void*, int);
51
  const char *(*auxRegName)(void*, int);
52
  const char *(*condCodeName)(void*, int);
53
  const char *(*instName)(void*, int, int, int*);
54
 
55
  unsigned char* instruction;
56
  unsigned index;
57
  const char *comm[6]; /* instr name, cond, NOP, 3 operands  */
58
  int opWidth;
59
  int targets[4];
60
  int addresses[4];
61
  /* Set as a side-effect of calling the disassembler.
62
     Used only by the debugger.  */
63
  enum Flow flow;
64
  int register_for_indirect_jump;
65
  int ea_reg1, ea_reg2, _offset;
66
  int _cond, _opcode;
67
  unsigned long words[2];
68
  char *commentBuffer;
69
  char instrBuffer[40];
70
  char operandBuffer[allOperandsSize];
71
  char _ea_present;
72
  char _mem_load;
73
  char _load_len;
74
  char nullifyMode;
75
  unsigned char commNum;
76
  unsigned char isBranch;
77
  unsigned char tcnt;
78
  unsigned char acnt;
79
};
80
 
81
#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0)
82
 
83
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.